^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2014-2015 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "cygnus-ssp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Register offset needed for ASoC PCM module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define INTH_R5F_STATUS_OFFSET 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define INTH_R5F_CLEAR_OFFSET 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define INTH_R5F_MASK_SET_OFFSET 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define INTH_R5F_MASK_CLEAR_OFFSET 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BF_REARM_FREE_MARK_OFFSET 0x344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BF_REARM_FULL_MARK_OFFSET 0x348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Ring Buffer Ctrl Regs --- Start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_RDADDR_REG_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SRC_RBUF_0_RDADDR_OFFSET 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SRC_RBUF_1_RDADDR_OFFSET 0x518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SRC_RBUF_2_RDADDR_OFFSET 0x530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SRC_RBUF_3_RDADDR_OFFSET 0x548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SRC_RBUF_4_RDADDR_OFFSET 0x560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SRC_RBUF_5_RDADDR_OFFSET 0x578
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SRC_RBUF_6_RDADDR_OFFSET 0x590
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_WRADDR_REG_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SRC_RBUF_0_WRADDR_OFFSET 0x504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SRC_RBUF_1_WRADDR_OFFSET 0x51c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SRC_RBUF_2_WRADDR_OFFSET 0x534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SRC_RBUF_3_WRADDR_OFFSET 0x54c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SRC_RBUF_4_WRADDR_OFFSET 0x564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SRC_RBUF_5_WRADDR_OFFSET 0x57c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SRC_RBUF_6_WRADDR_OFFSET 0x594
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_BASEADDR_REG_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SRC_RBUF_0_BASEADDR_OFFSET 0x508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SRC_RBUF_1_BASEADDR_OFFSET 0x520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SRC_RBUF_2_BASEADDR_OFFSET 0x538
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SRC_RBUF_3_BASEADDR_OFFSET 0x550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SRC_RBUF_4_BASEADDR_OFFSET 0x568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SRC_RBUF_5_BASEADDR_OFFSET 0x580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SRC_RBUF_6_BASEADDR_OFFSET 0x598
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_ENDADDR_REG_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SRC_RBUF_0_ENDADDR_OFFSET 0x50c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SRC_RBUF_1_ENDADDR_OFFSET 0x524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SRC_RBUF_2_ENDADDR_OFFSET 0x53c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SRC_RBUF_3_ENDADDR_OFFSET 0x554
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SRC_RBUF_4_ENDADDR_OFFSET 0x56c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SRC_RBUF_5_ENDADDR_OFFSET 0x584
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SRC_RBUF_6_ENDADDR_OFFSET 0x59c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_FREE_MARK_REG_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SRC_RBUF_0_FREE_MARK_OFFSET 0x510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SRC_RBUF_1_FREE_MARK_OFFSET 0x528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SRC_RBUF_2_FREE_MARK_OFFSET 0x540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SRC_RBUF_3_FREE_MARK_OFFSET 0x558
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SRC_RBUF_4_FREE_MARK_OFFSET 0x570
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SRC_RBUF_5_FREE_MARK_OFFSET 0x588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SRC_RBUF_6_FREE_MARK_OFFSET 0x5a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_RDADDR_REG_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DST_RBUF_0_RDADDR_OFFSET 0x5c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DST_RBUF_1_RDADDR_OFFSET 0x5d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DST_RBUF_2_RDADDR_OFFSET 0x5f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DST_RBUF_3_RDADDR_OFFSET 0x608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DST_RBUF_4_RDADDR_OFFSET 0x620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DST_RBUF_5_RDADDR_OFFSET 0x638
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_WRADDR_REG_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DST_RBUF_0_WRADDR_OFFSET 0x5c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DST_RBUF_1_WRADDR_OFFSET 0x5dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DST_RBUF_2_WRADDR_OFFSET 0x5f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DST_RBUF_3_WRADDR_OFFSET 0x60c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DST_RBUF_4_WRADDR_OFFSET 0x624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DST_RBUF_5_WRADDR_OFFSET 0x63c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_BASEADDR_REG_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DST_RBUF_0_BASEADDR_OFFSET 0x5c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DST_RBUF_1_BASEADDR_OFFSET 0x5e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DST_RBUF_2_BASEADDR_OFFSET 0x5f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DST_RBUF_3_BASEADDR_OFFSET 0x610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DST_RBUF_4_BASEADDR_OFFSET 0x628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DST_RBUF_5_BASEADDR_OFFSET 0x640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_ENDADDR_REG_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DST_RBUF_0_ENDADDR_OFFSET 0x5cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DST_RBUF_1_ENDADDR_OFFSET 0x5e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DST_RBUF_2_ENDADDR_OFFSET 0x5fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DST_RBUF_3_ENDADDR_OFFSET 0x614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DST_RBUF_4_ENDADDR_OFFSET 0x62c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DST_RBUF_5_ENDADDR_OFFSET 0x644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_FULL_MARK_REG_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DST_RBUF_0_FULL_MARK_OFFSET 0x5d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DST_RBUF_1_FULL_MARK_OFFSET 0x5e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DST_RBUF_2_FULL_MARK_OFFSET 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DST_RBUF_3_FULL_MARK_OFFSET 0x618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DST_RBUF_4_FULL_MARK_OFFSET 0x630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DST_RBUF_5_FULL_MARK_OFFSET 0x648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Ring Buffer Ctrl Regs --- End */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Error Status Regs --- Start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* AUD_FMM_BF_ESR_ESRX_STATUS_REG_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ESR0_STATUS_OFFSET 0x900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ESR1_STATUS_OFFSET 0x918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ESR2_STATUS_OFFSET 0x930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ESR3_STATUS_OFFSET 0x948
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ESR4_STATUS_OFFSET 0x960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* AUD_FMM_BF_ESR_ESRX_STATUS_CLEAR_REG_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ESR0_STATUS_CLR_OFFSET 0x908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ESR1_STATUS_CLR_OFFSET 0x920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ESR2_STATUS_CLR_OFFSET 0x938
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ESR3_STATUS_CLR_OFFSET 0x950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ESR4_STATUS_CLR_OFFSET 0x968
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* AUD_FMM_BF_ESR_ESRX_MASK_REG_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ESR0_MASK_STATUS_OFFSET 0x90c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ESR1_MASK_STATUS_OFFSET 0x924
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ESR2_MASK_STATUS_OFFSET 0x93c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ESR3_MASK_STATUS_OFFSET 0x954
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ESR4_MASK_STATUS_OFFSET 0x96c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* AUD_FMM_BF_ESR_ESRX_MASK_SET_REG_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ESR0_MASK_SET_OFFSET 0x910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ESR1_MASK_SET_OFFSET 0x928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ESR2_MASK_SET_OFFSET 0x940
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ESR3_MASK_SET_OFFSET 0x958
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ESR4_MASK_SET_OFFSET 0x970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* AUD_FMM_BF_ESR_ESRX_MASK_CLEAR_REG_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ESR0_MASK_CLR_OFFSET 0x914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ESR1_MASK_CLR_OFFSET 0x92c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ESR2_MASK_CLR_OFFSET 0x944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ESR3_MASK_CLR_OFFSET 0x95c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ESR4_MASK_CLR_OFFSET 0x974
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Error Status Regs --- End */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define R5F_ESR0_SHIFT 0 /* esr0 = fifo underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define R5F_ESR1_SHIFT 1 /* esr1 = ringbuf underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define R5F_ESR2_SHIFT 2 /* esr2 = ringbuf overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define R5F_ESR3_SHIFT 3 /* esr3 = freemark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define R5F_ESR4_SHIFT 4 /* esr4 = fullmark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Mask for R5F register. Set all relevant interrupt for playback handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ANY_PLAYBACK_IRQ (BIT(R5F_ESR0_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) BIT(R5F_ESR1_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) BIT(R5F_ESR3_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Mask for R5F register. Set all relevant interrupt for capture handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ANY_CAPTURE_IRQ (BIT(R5F_ESR2_SHIFT) | BIT(R5F_ESR4_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * PERIOD_BYTES_MIN is the number of bytes to at which the interrupt will tick.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * This number should be a multiple of 256. Minimum value is 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PERIOD_BYTES_MIN 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct snd_pcm_hardware cygnus_pcm_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) SNDRV_PCM_INFO_INTERLEAVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* A period is basically an interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .period_bytes_min = PERIOD_BYTES_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .period_bytes_max = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* period_min/max gives range of approx interrupts per buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .periods_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * maximum buffer size in bytes = period_bytes_max * periods_max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * We allocate this amount of data for each enabled channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .buffer_bytes_max = 4 * 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static u64 cygnus_dma_dmamask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct cygnus_aio_port *cygnus_dai_get_dma_data(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(soc_runtime, 0), substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static void ringbuf_set_initial(void __iomem *audio_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct ringbuf_regs *p_rbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) bool is_playback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 periodsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 bufsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 initial_rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 initial_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 fmark_val; /* free or full mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) p_rbuf->period_bytes = periodsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) p_rbuf->buf_size = bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (is_playback) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Set the pointers to indicate full (flip uppermost bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) initial_rd = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) initial_wr = initial_rd ^ BIT(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Set the pointers to indicate empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) initial_wr = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) initial_rd = initial_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) end = start + bufsize - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * The interrupt will fire when free/full mark is *exceeded*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * The fmark value must be multiple of PERIOD_BYTES_MIN so set fmark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * to be PERIOD_BYTES_MIN less than the period size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) fmark_val = periodsize - PERIOD_BYTES_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) writel(start, audio_io + p_rbuf->baseaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) writel(end, audio_io + p_rbuf->endaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) writel(fmark_val, audio_io + p_rbuf->fmark);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) writel(initial_rd, audio_io + p_rbuf->rdaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) writel(initial_wr, audio_io + p_rbuf->wraddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int configure_ringbuf_regs(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct cygnus_aio_port *aio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct ringbuf_regs *p_rbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) aio = cygnus_dai_get_dma_data(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Map the ssp portnum to a set of ring buffers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) p_rbuf = &aio->play_rb_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) switch (aio->portnum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) *p_rbuf = RINGBUF_REG_PLAYBACK(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *p_rbuf = RINGBUF_REG_PLAYBACK(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) *p_rbuf = RINGBUF_REG_PLAYBACK(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) case 3: /* SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *p_rbuf = RINGBUF_REG_PLAYBACK(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) status = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) p_rbuf = &aio->capture_rb_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) switch (aio->portnum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) *p_rbuf = RINGBUF_REG_CAPTURE(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) *p_rbuf = RINGBUF_REG_CAPTURE(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) *p_rbuf = RINGBUF_REG_CAPTURE(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) status = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static struct ringbuf_regs *get_ringbuf(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct cygnus_aio_port *aio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct ringbuf_regs *p_rbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) aio = cygnus_dai_get_dma_data(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) p_rbuf = &aio->play_rb_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) p_rbuf = &aio->capture_rb_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return p_rbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static void enable_intr(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct cygnus_aio_port *aio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 clear_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) aio = cygnus_dai_get_dma_data(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* The port number maps to the bit position to be cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) clear_mask = BIT(aio->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Clear interrupt status before enabling them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) writel(clear_mask, aio->cygaud->audio + ESR0_STATUS_CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) writel(clear_mask, aio->cygaud->audio + ESR1_STATUS_CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) writel(clear_mask, aio->cygaud->audio + ESR3_STATUS_CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Unmask the interrupts of the given port*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) writel(clear_mask, aio->cygaud->audio + ESR0_MASK_CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) writel(clear_mask, aio->cygaud->audio + ESR1_MASK_CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) writel(clear_mask, aio->cygaud->audio + ESR3_MASK_CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) writel(ANY_PLAYBACK_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) aio->cygaud->audio + INTH_R5F_MASK_CLEAR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) writel(clear_mask, aio->cygaud->audio + ESR2_STATUS_CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) writel(clear_mask, aio->cygaud->audio + ESR4_STATUS_CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) writel(clear_mask, aio->cygaud->audio + ESR2_MASK_CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) writel(clear_mask, aio->cygaud->audio + ESR4_MASK_CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) writel(ANY_CAPTURE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) aio->cygaud->audio + INTH_R5F_MASK_CLEAR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static void disable_intr(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct cygnus_aio_port *aio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 set_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) aio = cygnus_dai_get_dma_data(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s on port %d\n", __func__, aio->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* The port number maps to the bit position to be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) set_mask = BIT(aio->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Mask the interrupts of the given port*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) writel(set_mask, aio->cygaud->audio + ESR0_MASK_SET_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) writel(set_mask, aio->cygaud->audio + ESR1_MASK_SET_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) writel(set_mask, aio->cygaud->audio + ESR3_MASK_SET_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) writel(set_mask, aio->cygaud->audio + ESR2_MASK_SET_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) writel(set_mask, aio->cygaud->audio + ESR4_MASK_SET_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int cygnus_pcm_trigger(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) enable_intr(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) disable_intr(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static void cygnus_pcm_period_elapsed(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct cygnus_aio_port *aio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct ringbuf_regs *p_rbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) aio = cygnus_dai_get_dma_data(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) p_rbuf = get_ringbuf(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * If free/full mark interrupt occurs, provide timestamp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * to ALSA and update appropriate idx by period_bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) snd_pcm_period_elapsed(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Set the ring buffer to full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) regval = readl(aio->cygaud->audio + p_rbuf->rdaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) regval = regval ^ BIT(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) writel(regval, aio->cygaud->audio + p_rbuf->wraddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* Set the ring buffer to empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) regval = readl(aio->cygaud->audio + p_rbuf->wraddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) writel(regval, aio->cygaud->audio + p_rbuf->rdaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * ESR0/1/3 status Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * 0x1 I2S0_out port caused interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * 0x2 I2S1_out port caused interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * 0x4 I2S2_out port caused interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * 0x8 SPDIF_out port caused interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static void handle_playback_irq(struct cygnus_audio *cygaud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) void __iomem *audio_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u32 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u32 esr_status0, esr_status1, esr_status3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) audio_io = cygaud->audio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * ESR status gets updates with/without interrupts enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * So, check the ESR mask, which provides interrupt enable/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * disable status and use it to determine which ESR status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * should be serviced.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) esr_status0 = readl(audio_io + ESR0_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) esr_status0 &= ~readl(audio_io + ESR0_MASK_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) esr_status1 = readl(audio_io + ESR1_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) esr_status1 &= ~readl(audio_io + ESR1_MASK_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) esr_status3 = readl(audio_io + ESR3_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) esr_status3 &= ~readl(audio_io + ESR3_MASK_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) for (port = 0; port < CYGNUS_MAX_PLAYBACK_PORTS; port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u32 esrmask = BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * Ringbuffer or FIFO underflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * If we get this interrupt then, it is also true that we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * not yet responded to the freemark interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * Log a debug message. The freemark handler below will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * handle getting everything going again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if ((esrmask & esr_status1) || (esrmask & esr_status0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dev_dbg(cygaud->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "Underrun: esr0=0x%x, esr1=0x%x esr3=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) esr_status0, esr_status1, esr_status3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * Freemark is hit. This is the normal interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * In typical operation the read and write regs will be equal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (esrmask & esr_status3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct snd_pcm_substream *playstr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) playstr = cygaud->portinfo[port].play_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) cygnus_pcm_period_elapsed(playstr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Clear ESR interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) writel(esr_status0, audio_io + ESR0_STATUS_CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) writel(esr_status1, audio_io + ESR1_STATUS_CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) writel(esr_status3, audio_io + ESR3_STATUS_CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Rearm freemark logic by writing 1 to the correct bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) writel(esr_status3, audio_io + BF_REARM_FREE_MARK_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * ESR2/4 status Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * 0x1 I2S0_in port caused interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * 0x2 I2S1_in port caused interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * 0x4 I2S2_in port caused interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static void handle_capture_irq(struct cygnus_audio *cygaud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) void __iomem *audio_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u32 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u32 esr_status2, esr_status4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) audio_io = cygaud->audio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * ESR status gets updates with/without interrupts enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * So, check the ESR mask, which provides interrupt enable/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * disable status and use it to determine which ESR status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * should be serviced.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) esr_status2 = readl(audio_io + ESR2_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) esr_status2 &= ~readl(audio_io + ESR2_MASK_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) esr_status4 = readl(audio_io + ESR4_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) esr_status4 &= ~readl(audio_io + ESR4_MASK_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) for (port = 0; port < CYGNUS_MAX_CAPTURE_PORTS; port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u32 esrmask = BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * Ringbuffer or FIFO overflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * If we get this interrupt then, it is also true that we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * not yet responded to the fullmark interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * Log a debug message. The fullmark handler below will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * handle getting everything going again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (esrmask & esr_status2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dev_dbg(cygaud->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) "Overflow: esr2=0x%x\n", esr_status2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (esrmask & esr_status4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct snd_pcm_substream *capstr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) capstr = cygaud->portinfo[port].capture_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) cygnus_pcm_period_elapsed(capstr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) writel(esr_status2, audio_io + ESR2_STATUS_CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) writel(esr_status4, audio_io + ESR4_STATUS_CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* Rearm fullmark logic by writing 1 to the correct bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) writel(esr_status4, audio_io + BF_REARM_FULL_MARK_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static irqreturn_t cygnus_dma_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u32 r5_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct cygnus_audio *cygaud = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * R5 status bits Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * 0 ESR0 (playback FIFO interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * 1 ESR1 (playback rbuf interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * 2 ESR2 (capture rbuf interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * 3 ESR3 (Freemark play. interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * 4 ESR4 (Fullmark capt. interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) r5_status = readl(cygaud->audio + INTH_R5F_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!(r5_status & (ANY_PLAYBACK_IRQ | ANY_CAPTURE_IRQ)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* If playback interrupt happened */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (ANY_PLAYBACK_IRQ & r5_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) handle_playback_irq(cygaud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) writel(ANY_PLAYBACK_IRQ & r5_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) cygaud->audio + INTH_R5F_CLEAR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* If capture interrupt happened */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (ANY_CAPTURE_IRQ & r5_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) handle_capture_irq(cygaud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) writel(ANY_CAPTURE_IRQ & r5_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) cygaud->audio + INTH_R5F_CLEAR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static int cygnus_pcm_open(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct cygnus_aio_port *aio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) aio = cygnus_dai_get_dma_data(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (!aio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s port %d\n", __func__, aio->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) snd_soc_set_runtime_hwparams(substream, &cygnus_pcm_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ret = snd_pcm_hw_constraint_step(runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) SNDRV_PCM_HW_PARAM_PERIOD_BYTES, PERIOD_BYTES_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ret = snd_pcm_hw_constraint_step(runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) SNDRV_PCM_HW_PARAM_BUFFER_BYTES, PERIOD_BYTES_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * Keep track of which substream belongs to which port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * This info is needed by snd_pcm_period_elapsed() in irq_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) aio->play_stream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) aio->capture_stream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int cygnus_pcm_close(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct cygnus_aio_port *aio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) aio = cygnus_dai_get_dma_data(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s port %d\n", __func__, aio->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) aio->play_stream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) aio->capture_stream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (!aio->play_stream && !aio->capture_stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "freed port %d\n", aio->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static int cygnus_pcm_hw_params(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct cygnus_aio_port *aio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) aio = cygnus_dai_get_dma_data(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s port %d\n", __func__, aio->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) runtime->dma_bytes = params_buffer_bytes(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static int cygnus_pcm_hw_free(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct cygnus_aio_port *aio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) aio = cygnus_dai_get_dma_data(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s port %d\n", __func__, aio->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) snd_pcm_set_runtime_buffer(substream, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static int cygnus_pcm_prepare(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct cygnus_aio_port *aio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) unsigned long bufsize, periodsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) bool is_play;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u32 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct ringbuf_regs *p_rbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) aio = cygnus_dai_get_dma_data(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s port %d\n", __func__, aio->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) bufsize = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) periodsize = snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s (buf_size %lu) (period_size %lu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) __func__, bufsize, periodsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) configure_ringbuf_regs(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) p_rbuf = get_ringbuf(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) start = runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ringbuf_set_initial(aio->cygaud->audio, p_rbuf, is_play, start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) periodsize, bufsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static snd_pcm_uframes_t cygnus_pcm_pointer(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct cygnus_aio_port *aio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) unsigned int res = 0, cur = 0, base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct ringbuf_regs *p_rbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) aio = cygnus_dai_get_dma_data(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * Get the offset of the current read (for playack) or write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * index (for capture). Report this value back to the asoc framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) p_rbuf = get_ringbuf(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) cur = readl(aio->cygaud->audio + p_rbuf->rdaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) cur = readl(aio->cygaud->audio + p_rbuf->wraddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) base = readl(aio->cygaud->audio + p_rbuf->baseaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * Mask off the MSB of the rdaddr,wraddr and baseaddr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * since MSB is not part of the address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) res = (cur & 0x7fffffff) - (base & 0x7fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return bytes_to_frames(substream->runtime, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static int cygnus_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct snd_pcm_substream *substream = pcm->streams[stream].substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct snd_dma_buffer *buf = &substream->dma_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) size = cygnus_pcm_hw.buffer_bytes_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) buf->dev.type = SNDRV_DMA_TYPE_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) buf->dev.dev = pcm->card->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) buf->private_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) buf->area = dma_alloc_coherent(pcm->card->dev, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) &buf->addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s: size 0x%zx @ %pK\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) __func__, size, buf->area);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (!buf->area) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dev_err(asoc_rtd_to_cpu(rtd, 0)->dev, "%s: dma_alloc failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) buf->bytes = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static void cygnus_dma_free_dma_buffers(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct snd_pcm *pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct snd_dma_buffer *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) buf = &substream->dma_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (buf->area) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dma_free_coherent(pcm->card->dev, buf->bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) buf->area, buf->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) buf->area = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) substream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) buf = &substream->dma_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (buf->area) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) dma_free_coherent(pcm->card->dev, buf->bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) buf->area, buf->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) buf->area = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static int cygnus_dma_new(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct snd_soc_pcm_runtime *rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct snd_card *card = rtd->card->snd_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct snd_pcm *pcm = rtd->pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (!card->dev->dma_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) card->dev->dma_mask = &cygnus_dma_dmamask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (!card->dev->coherent_dma_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ret = cygnus_pcm_preallocate_dma_buffer(pcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) SNDRV_PCM_STREAM_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ret = cygnus_pcm_preallocate_dma_buffer(pcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) SNDRV_PCM_STREAM_CAPTURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) cygnus_dma_free_dma_buffers(component, pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static struct snd_soc_component_driver cygnus_soc_platform = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .open = cygnus_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .close = cygnus_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .hw_params = cygnus_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .hw_free = cygnus_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .prepare = cygnus_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .trigger = cygnus_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .pointer = cygnus_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .pcm_construct = cygnus_dma_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .pcm_destruct = cygnus_dma_free_dma_buffers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) int cygnus_soc_platform_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct cygnus_audio *cygaud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dev_dbg(dev, "%s Enter\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) rc = devm_request_irq(dev, cygaud->irq_num, cygnus_dma_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) IRQF_SHARED, "cygnus-audio", cygaud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dev_err(dev, "%s request_irq error %d\n", __func__, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) rc = devm_snd_soc_register_component(dev, &cygnus_soc_platform,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) dev_err(dev, "%s failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) int cygnus_soc_platform_unregister(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) MODULE_AUTHOR("Broadcom");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) MODULE_DESCRIPTION("Cygnus ASoC PCM module");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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