^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // linux/sound/bcm/bcm63xx-pcm-whistler.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // BCM63xx whistler pcm interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Copyright (c) 2020 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Author: Kevin-Ke Li <kevin-ke.li@broadcom.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "bcm63xx-i2s.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct i2s_dma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) unsigned char *dma_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) unsigned int dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct bcm63xx_runtime_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) int dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) dma_addr_t dma_addr_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const struct snd_pcm_hardware bcm63xx_pcm_hardware = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) SNDRV_PCM_INFO_RESUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .formats = SNDRV_PCM_FMTBIT_S32_LE, /* support S32 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .period_bytes_max = 8192 - 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .periods_max = PAGE_SIZE/sizeof(struct i2s_dma_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .buffer_bytes_max = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .fifo_size = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int bcm63xx_pcm_hw_params(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct i2s_dma_desc *dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) runtime->dma_bytes = params_buffer_bytes(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (!dma_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) snd_soc_dai_set_dma_data(asoc_rtd_to_cpu(rtd, 0), substream, dma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int bcm63xx_pcm_hw_free(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct i2s_dma_desc *dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) dma_desc = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) kfree(dma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) snd_pcm_set_runtime_buffer(substream, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int bcm63xx_pcm_trigger(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct snd_soc_pcm_runtime *rtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct bcm_i2s_priv *i2s_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct regmap *regmap_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) i2s_priv = dev_get_drvdata(asoc_rtd_to_cpu(rtd, 0)->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) regmap_i2s = i2s_priv->regmap_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) regmap_update_bits(regmap_i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) I2S_TX_IRQ_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) I2S_TX_DESC_OFF_INTR_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) I2S_TX_DESC_OFF_INTR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) regmap_update_bits(regmap_i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) I2S_TX_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) I2S_TX_ENABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) I2S_TX_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) regmap_write(regmap_i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) I2S_TX_IRQ_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) regmap_update_bits(regmap_i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) I2S_TX_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) I2S_TX_ENABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) regmap_update_bits(regmap_i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) I2S_RX_IRQ_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) I2S_RX_DESC_OFF_INTR_EN_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) I2S_RX_DESC_OFF_INTR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) regmap_update_bits(regmap_i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) I2S_RX_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) I2S_RX_ENABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) I2S_RX_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) regmap_update_bits(regmap_i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) I2S_RX_IRQ_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) I2S_RX_DESC_OFF_INTR_EN_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) regmap_update_bits(regmap_i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) I2S_RX_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) I2S_RX_ENABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int bcm63xx_pcm_prepare(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct i2s_dma_desc *dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct regmap *regmap_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct bcm_i2s_priv *i2s_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) uint32_t regaddr_desclen, regaddr_descaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dma_desc = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dma_desc->dma_len = snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dma_desc->dma_addr = runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dma_desc->dma_area = runtime->dma_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) regaddr_desclen = I2S_TX_DESC_IFF_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) regaddr_descaddr = I2S_TX_DESC_IFF_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) regaddr_desclen = I2S_RX_DESC_IFF_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) regaddr_descaddr = I2S_RX_DESC_IFF_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) i2s_priv = dev_get_drvdata(asoc_rtd_to_cpu(rtd, 0)->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) regmap_i2s = i2s_priv->regmap_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) regmap_write(regmap_i2s, regaddr_desclen, dma_desc->dma_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) regmap_write(regmap_i2s, regaddr_descaddr, dma_desc->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) bcm63xx_pcm_pointer(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) snd_pcm_uframes_t x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct bcm63xx_runtime_data *prtd = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!prtd->dma_addr_next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) prtd->dma_addr_next = substream->runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) x = bytes_to_frames(substream->runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) prtd->dma_addr_next - substream->runtime->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return x == substream->runtime->buffer_size ? 0 : x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int bcm63xx_pcm_mmap(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct vm_area_struct *vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return dma_mmap_wc(substream->pcm->card->dev, vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) runtime->dma_area,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) runtime->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) runtime->dma_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int bcm63xx_pcm_open(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct bcm63xx_runtime_data *prtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) runtime->hw = bcm63xx_pcm_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = snd_pcm_hw_constraint_step(runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret = snd_pcm_hw_constraint_step(runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = snd_pcm_hw_constraint_integer(runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) SNDRV_PCM_HW_PARAM_PERIODS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) prtd = kzalloc(sizeof(*prtd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!prtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) runtime->private_data = prtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int bcm63xx_pcm_close(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct bcm63xx_runtime_data *prtd = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) kfree(prtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static irqreturn_t i2s_dma_isr(int irq, void *bcm_i2s_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned int availdepth, ifflevel, offlevel, int_status, val_1, val_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct bcm63xx_runtime_data *prtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct snd_pcm_runtime *runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct regmap *regmap_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct i2s_dma_desc *dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct snd_soc_pcm_runtime *rtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct bcm_i2s_priv *i2s_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) i2s_priv = (struct bcm_i2s_priv *)bcm_i2s_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) regmap_i2s = i2s_priv->regmap_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) regmap_read(regmap_i2s, I2S_RX_IRQ_CTL, &int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (int_status & I2S_RX_DESC_OFF_INTR_EN_MSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) substream = i2s_priv->capture_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) prtd = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dma_desc = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) offlevel = (int_status & I2S_RX_DESC_OFF_LEVEL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) I2S_RX_DESC_OFF_LEVEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) while (offlevel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) regmap_read(regmap_i2s, I2S_RX_DESC_OFF_ADDR, &val_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) regmap_read(regmap_i2s, I2S_RX_DESC_OFF_LEN, &val_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) offlevel--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) prtd->dma_addr_next = val_1 + val_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ifflevel = (int_status & I2S_RX_DESC_IFF_LEVEL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) I2S_RX_DESC_IFF_LEVEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) availdepth = I2S_DESC_FIFO_DEPTH - ifflevel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) while (availdepth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dma_desc->dma_addr +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dma_desc->dma_area +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (dma_desc->dma_addr - runtime->dma_addr >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) runtime->dma_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dma_desc->dma_addr = runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dma_desc->dma_area = runtime->dma_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) prtd->dma_addr = dma_desc->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) regmap_write(regmap_i2s, I2S_RX_DESC_IFF_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) snd_pcm_lib_period_bytes(substream));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) regmap_write(regmap_i2s, I2S_RX_DESC_IFF_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dma_desc->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) availdepth--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) snd_pcm_period_elapsed(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Clear interrupt by writing 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) regmap_update_bits(regmap_i2s, I2S_RX_IRQ_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) I2S_RX_INTR_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) regmap_read(regmap_i2s, I2S_TX_IRQ_CTL, &int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (int_status & I2S_TX_DESC_OFF_INTR_EN_MSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) substream = i2s_priv->play_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) prtd = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dma_desc = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) offlevel = (int_status & I2S_TX_DESC_OFF_LEVEL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) I2S_TX_DESC_OFF_LEVEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) while (offlevel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) regmap_read(regmap_i2s, I2S_TX_DESC_OFF_ADDR, &val_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) regmap_read(regmap_i2s, I2S_TX_DESC_OFF_LEN, &val_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) prtd->dma_addr_next = val_1 + val_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) offlevel--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ifflevel = (int_status & I2S_TX_DESC_IFF_LEVEL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) I2S_TX_DESC_IFF_LEVEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) availdepth = I2S_DESC_FIFO_DEPTH - ifflevel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) while (availdepth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dma_desc->dma_addr +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dma_desc->dma_area +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (dma_desc->dma_addr - runtime->dma_addr >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) runtime->dma_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dma_desc->dma_addr = runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dma_desc->dma_area = runtime->dma_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) prtd->dma_addr = dma_desc->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) regmap_write(regmap_i2s, I2S_TX_DESC_IFF_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) snd_pcm_lib_period_bytes(substream));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) regmap_write(regmap_i2s, I2S_TX_DESC_IFF_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dma_desc->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) availdepth--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) snd_pcm_period_elapsed(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Clear interrupt by writing 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) regmap_update_bits(regmap_i2s, I2S_TX_IRQ_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) I2S_TX_INTR_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int bcm63xx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct snd_pcm_substream *substream = pcm->streams[stream].substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct snd_dma_buffer *buf = &substream->dma_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) size_t size = bcm63xx_pcm_hardware.buffer_bytes_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) buf->dev.type = SNDRV_DMA_TYPE_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) buf->dev.dev = pcm->card->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) buf->private_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) buf->area = dma_alloc_wc(pcm->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) size, &buf->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (!buf->area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) buf->bytes = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int bcm63xx_soc_pcm_new(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct snd_soc_pcm_runtime *rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct snd_pcm *pcm = rtd->pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct bcm_i2s_priv *i2s_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) i2s_priv = dev_get_drvdata(asoc_rtd_to_cpu(rtd, 0)->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) of_dma_configure(pcm->card->dev, pcm->card->dev->of_node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ret = dma_coerce_mask_and_coherent(pcm->card->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = bcm63xx_pcm_preallocate_dma_buffer(pcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) SNDRV_PCM_STREAM_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) i2s_priv->play_substream =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = bcm63xx_pcm_preallocate_dma_buffer(pcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) SNDRV_PCM_STREAM_CAPTURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) i2s_priv->capture_substream =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static void bcm63xx_pcm_free_dma_buffers(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct snd_pcm *pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct snd_dma_buffer *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) for (stream = 0; stream < 2; stream++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) substream = pcm->streams[stream].substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (!substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) buf = &substream->dma_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!buf->area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dma_free_wc(pcm->card->dev, buf->bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) buf->area, buf->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) buf->area = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const struct snd_soc_component_driver bcm63xx_soc_platform = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .open = bcm63xx_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .close = bcm63xx_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .hw_params = bcm63xx_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .hw_free = bcm63xx_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .prepare = bcm63xx_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .trigger = bcm63xx_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .pointer = bcm63xx_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .mmap = bcm63xx_pcm_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .pcm_construct = bcm63xx_soc_pcm_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .pcm_destruct = bcm63xx_pcm_free_dma_buffers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int bcm63xx_soc_platform_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct bcm_i2s_priv *i2s_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) i2s_priv->r_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (!i2s_priv->r_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev_err(&pdev->dev, "Unable to get register irq resource.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = devm_request_irq(&pdev->dev, i2s_priv->r_irq->start, i2s_dma_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) i2s_priv->r_irq->flags, "i2s_dma", (void *)i2s_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) "i2s_init: failed to request interrupt.ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) &bcm63xx_soc_platform, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int bcm63xx_soc_platform_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MODULE_AUTHOR("Kevin,Li <kevin-ke.li@broadcom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MODULE_DESCRIPTION("Broadcom DSL XPON ASOC PCM Interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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