^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // linux/sound/soc/bcm/bcm63xx-i2s.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2020 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Author: Kevin-Ke Li <kevin-ke.li@broadcom.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __BCM63XX_I2S_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __BCM63XX_I2S_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define I2S_DESC_FIFO_DEPTH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define I2S_MISC_CFG (0x003C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define I2S_PAD_LVL_LOOP_DIS_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define I2S_PAD_LVL_LOOP_DIS_ENABLE I2S_PAD_LVL_LOOP_DIS_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define I2S_TX_ENABLE_MASK (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define I2S_TX_ENABLE I2S_TX_ENABLE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define I2S_TX_OUT_R (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define I2S_TX_DATA_ALIGNMENT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define I2S_TX_DATA_ENABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define I2S_TX_CLOCK_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define I2S_TX_DESC_OFF_LEVEL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define I2S_TX_DESC_OFF_LEVEL_MASK (0x0F << I2S_TX_DESC_OFF_LEVEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define I2S_TX_DESC_IFF_LEVEL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define I2S_TX_DESC_IFF_LEVEL_MASK (0x0F << I2S_TX_DESC_IFF_LEVEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define I2S_TX_DESC_OFF_INTR_EN_MSK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define I2S_TX_DESC_OFF_INTR_EN I2S_TX_DESC_OFF_INTR_EN_MSK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define I2S_TX_CFG (0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define I2S_TX_IRQ_CTL (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define I2S_TX_IRQ_EN (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define I2S_TX_IRQ_IFF_THLD (0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define I2S_TX_IRQ_OFF_THLD (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define I2S_TX_DESC_IFF_ADDR (0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define I2S_TX_DESC_IFF_LEN (0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define I2S_TX_DESC_OFF_ADDR (0x001C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define I2S_TX_DESC_OFF_LEN (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define I2S_TX_CFG_2 (0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define I2S_TX_SLAVE_MODE_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define I2S_TX_SLAVE_MODE_MASK (1 << I2S_TX_SLAVE_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I2S_TX_SLAVE_MODE I2S_TX_SLAVE_MODE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I2S_TX_MASTER_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define I2S_TX_INTR_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I2S_RX_ENABLE_MASK (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define I2S_RX_ENABLE I2S_RX_ENABLE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define I2S_RX_IN_R (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define I2S_RX_DATA_ALIGNMENT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define I2S_RX_CLOCK_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define I2S_RX_DESC_OFF_LEVEL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define I2S_RX_DESC_OFF_LEVEL_MASK (0x0F << I2S_RX_DESC_OFF_LEVEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define I2S_RX_DESC_IFF_LEVEL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define I2S_RX_DESC_IFF_LEVEL_MASK (0x0F << I2S_RX_DESC_IFF_LEVEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define I2S_RX_DESC_OFF_INTR_EN_MSK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define I2S_RX_DESC_OFF_INTR_EN I2S_RX_DESC_OFF_INTR_EN_MSK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define I2S_RX_CFG (0x0040) /* 20c0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define I2S_RX_IRQ_CTL (0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define I2S_RX_IRQ_EN (0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define I2S_RX_IRQ_IFF_THLD (0x004C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I2S_RX_IRQ_OFF_THLD (0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I2S_RX_DESC_IFF_ADDR (0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I2S_RX_DESC_IFF_LEN (0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define I2S_RX_DESC_OFF_ADDR (0x005C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define I2S_RX_DESC_OFF_LEN (0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define I2S_RX_CFG_2 (0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define I2S_RX_SLAVE_MODE_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define I2S_RX_SLAVE_MODE_MASK (1 << I2S_RX_SLAVE_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define I2S_RX_SLAVE_MODE I2S_RX_SLAVE_MODE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define I2S_RX_MASTER_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define I2S_RX_INTR_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define I2S_REG_MAX 0x007C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct bcm_i2s_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct resource *r_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct regmap *regmap_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct clk *i2s_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct snd_pcm_substream *play_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct snd_pcm_substream *capture_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct i2s_dma_desc *play_dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct i2s_dma_desc *capture_dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) extern int bcm63xx_soc_platform_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct bcm_i2s_priv *i2s_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) extern int bcm63xx_soc_platform_remove(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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