^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // linux/sound/bcm/bcm63xx-i2s-whistler.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // BCM63xx whistler i2s driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Copyright (c) 2020 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Author: Kevin-Ke Li <kevin-ke.li@broadcom.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "bcm63xx-i2s.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DRV_NAME "brcm-i2s"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static bool brcm_i2s_wr_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) case I2S_TX_CFG ... I2S_TX_DESC_IFF_LEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) case I2S_TX_CFG_2 ... I2S_RX_DESC_IFF_LEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) case I2S_RX_CFG_2 ... I2S_REG_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static bool brcm_i2s_rd_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) case I2S_TX_CFG ... I2S_REG_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static bool brcm_i2s_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) case I2S_TX_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) case I2S_TX_IRQ_CTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) case I2S_TX_DESC_IFF_ADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) case I2S_TX_DESC_IFF_LEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) case I2S_TX_DESC_OFF_ADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) case I2S_TX_DESC_OFF_LEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) case I2S_TX_CFG_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) case I2S_RX_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) case I2S_RX_IRQ_CTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) case I2S_RX_DESC_OFF_ADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) case I2S_RX_DESC_OFF_LEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) case I2S_RX_DESC_IFF_LEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) case I2S_RX_DESC_IFF_ADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) case I2S_RX_CFG_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const struct regmap_config brcm_i2s_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .max_register = I2S_REG_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .writeable_reg = brcm_i2s_wr_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .readable_reg = brcm_i2s_rd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .volatile_reg = brcm_i2s_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int bcm63xx_i2s_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct bcm_i2s_priv *i2s_priv = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ret = clk_set_rate(i2s_priv->i2s_clk, params_rate(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dev_err(i2s_priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "Can't set sample rate, err: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int bcm63xx_i2s_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int slavemode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct bcm_i2s_priv *i2s_priv = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct regmap *regmap_i2s = i2s_priv->regmap_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) regmap_update_bits(regmap_i2s, I2S_TX_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) I2S_TX_OUT_R | I2S_TX_DATA_ALIGNMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) I2S_TX_DATA_ENABLE | I2S_TX_CLOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) I2S_TX_OUT_R | I2S_TX_DATA_ALIGNMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) I2S_TX_DATA_ENABLE | I2S_TX_CLOCK_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) regmap_write(regmap_i2s, I2S_TX_IRQ_CTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) regmap_write(regmap_i2s, I2S_TX_IRQ_IFF_THLD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) regmap_write(regmap_i2s, I2S_TX_IRQ_OFF_THLD, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* TX and RX block each have an independent bit to indicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * if it is generating the clock for the I2S bus. The bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * clocks need to be generated from either the TX or RX block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * but not both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) regmap_read(regmap_i2s, I2S_RX_CFG_2, &slavemode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (slavemode & I2S_RX_SLAVE_MODE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) I2S_TX_SLAVE_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) I2S_TX_MASTER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) I2S_TX_SLAVE_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) I2S_TX_SLAVE_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) regmap_update_bits(regmap_i2s, I2S_RX_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) I2S_RX_IN_R | I2S_RX_DATA_ALIGNMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) I2S_RX_CLOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) I2S_RX_IN_R | I2S_RX_DATA_ALIGNMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) I2S_RX_CLOCK_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) regmap_write(regmap_i2s, I2S_RX_IRQ_CTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) regmap_write(regmap_i2s, I2S_RX_IRQ_IFF_THLD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) regmap_write(regmap_i2s, I2S_RX_IRQ_OFF_THLD, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) regmap_read(regmap_i2s, I2S_TX_CFG_2, &slavemode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (slavemode & I2S_TX_SLAVE_MODE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) I2S_RX_SLAVE_MODE_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) I2S_RX_SLAVE_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) I2S_RX_SLAVE_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void bcm63xx_i2s_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int enabled, slavemode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct bcm_i2s_priv *i2s_priv = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct regmap *regmap_i2s = i2s_priv->regmap_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) regmap_update_bits(regmap_i2s, I2S_TX_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) I2S_TX_OUT_R | I2S_TX_DATA_ALIGNMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) I2S_TX_DATA_ENABLE | I2S_TX_CLOCK_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) regmap_write(regmap_i2s, I2S_TX_IRQ_CTL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) regmap_write(regmap_i2s, I2S_TX_IRQ_IFF_THLD, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) regmap_write(regmap_i2s, I2S_TX_IRQ_OFF_THLD, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) regmap_read(regmap_i2s, I2S_TX_CFG_2, &slavemode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) slavemode = slavemode & I2S_TX_SLAVE_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!slavemode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) regmap_read(regmap_i2s, I2S_RX_CFG, &enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) enabled = enabled & I2S_RX_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) I2S_RX_SLAVE_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) I2S_RX_MASTER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) I2S_TX_SLAVE_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) I2S_TX_SLAVE_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) regmap_update_bits(regmap_i2s, I2S_RX_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) I2S_RX_IN_R | I2S_RX_DATA_ALIGNMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) I2S_RX_CLOCK_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) regmap_write(regmap_i2s, I2S_RX_IRQ_CTL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) regmap_write(regmap_i2s, I2S_RX_IRQ_IFF_THLD, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) regmap_write(regmap_i2s, I2S_RX_IRQ_OFF_THLD, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) regmap_read(regmap_i2s, I2S_RX_CFG_2, &slavemode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) slavemode = slavemode & I2S_RX_SLAVE_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (!slavemode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) regmap_read(regmap_i2s, I2S_TX_CFG, &enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) enabled = enabled & I2S_TX_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) I2S_TX_SLAVE_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) I2S_TX_MASTER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) I2S_RX_SLAVE_MODE_MASK, I2S_RX_SLAVE_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct snd_soc_dai_ops bcm63xx_i2s_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .startup = bcm63xx_i2s_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .shutdown = bcm63xx_i2s_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .hw_params = bcm63xx_i2s_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct snd_soc_dai_driver bcm63xx_i2s_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .formats = SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .formats = SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .ops = &bcm63xx_i2s_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .symmetric_rates = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .symmetric_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const struct snd_soc_component_driver bcm63xx_i2s_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .name = "bcm63xx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int bcm63xx_i2s_dev_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct resource *r_mem, *region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct bcm_i2s_priv *i2s_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct regmap *regmap_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct clk *i2s_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) i2s_priv = devm_kzalloc(&pdev->dev, sizeof(*i2s_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (!i2s_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) i2s_clk = devm_clk_get(&pdev->dev, "i2sclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (IS_ERR(i2s_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_err(&pdev->dev, "%s: cannot get a brcm clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) __func__, PTR_ERR(i2s_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return PTR_ERR(i2s_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (!r_mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_err(&pdev->dev, "Unable to get register resource.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) region = devm_request_mem_region(&pdev->dev, r_mem->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) resource_size(r_mem), DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!region) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dev_err(&pdev->dev, "Memory region already claimed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) regs = devm_ioremap_resource(&pdev->dev, r_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (IS_ERR(regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) regmap_i2s = devm_regmap_init_mmio(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) regs, &brcm_i2s_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (IS_ERR(regmap_i2s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return PTR_ERR(regmap_i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) regmap_update_bits(regmap_i2s, I2S_MISC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) I2S_PAD_LVL_LOOP_DIS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) I2S_PAD_LVL_LOOP_DIS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ret = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) &bcm63xx_i2s_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) &bcm63xx_i2s_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_err(&pdev->dev, "failed to register the dai\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) i2s_priv->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) i2s_priv->i2s_clk = i2s_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) i2s_priv->regmap_i2s = regmap_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dev_set_drvdata(&pdev->dev, i2s_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = bcm63xx_soc_platform_probe(pdev, i2s_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dev_err(&pdev->dev, "failed to register the pcm\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int bcm63xx_i2s_dev_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) bcm63xx_soc_platform_remove(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const struct of_device_id snd_soc_bcm_audio_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {.compatible = "brcm,bcm63xx-i2s"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static struct platform_driver bcm63xx_i2s_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .of_match_table = of_match_ptr(snd_soc_bcm_audio_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .probe = bcm63xx_i2s_dev_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .remove = bcm63xx_i2s_dev_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) module_platform_driver(bcm63xx_i2s_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MODULE_AUTHOR("Kevin,Li <kevin-ke.li@broadcom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MODULE_DESCRIPTION("Broadcom DSL XPON ASOC I2S Interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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