^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA SoC I2S Audio Layer for Broadcom BCM2835 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Florian Meier <florian.meier@koalo.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Raspberry Pi PCM I2S ALSA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (c) by Phil Poole 2013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Vladimir Barinov, <vbarinov@embeddedalley.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * OMAP ALSA SoC DAI driver using McBSP port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Copyright (C) 2008 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Peter Ujfalusi <peter.ujfalusi@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Author: Timur Tabi <timur@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Copyright 2007-2010 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* I2S registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BCM2835_I2S_CS_A_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BCM2835_I2S_FIFO_A_REG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BCM2835_I2S_MODE_A_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BCM2835_I2S_RXC_A_REG 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BCM2835_I2S_TXC_A_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BCM2835_I2S_DREQ_A_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BCM2835_I2S_INTEN_A_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BCM2835_I2S_INTSTC_A_REG 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BCM2835_I2S_GRAY_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* I2S register settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BCM2835_I2S_STBY BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BCM2835_I2S_SYNC BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BCM2835_I2S_RXSEX BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BCM2835_I2S_RXF BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BCM2835_I2S_TXE BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BCM2835_I2S_RXD BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BCM2835_I2S_TXD BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BCM2835_I2S_RXR BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BCM2835_I2S_TXW BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define BCM2835_I2S_CS_RXERR BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BCM2835_I2S_CS_TXERR BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define BCM2835_I2S_RXSYNC BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define BCM2835_I2S_TXSYNC BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BCM2835_I2S_DMAEN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BCM2835_I2S_RXTHR(v) ((v) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BCM2835_I2S_TXTHR(v) ((v) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BCM2835_I2S_RXCLR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BCM2835_I2S_TXCLR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BCM2835_I2S_TXON BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define BCM2835_I2S_RXON BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BCM2835_I2S_EN (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define BCM2835_I2S_CLKDIS BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BCM2835_I2S_PDMN BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BCM2835_I2S_PDME BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BCM2835_I2S_FRXP BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define BCM2835_I2S_FTXP BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BCM2835_I2S_CLKM BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BCM2835_I2S_CLKI BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BCM2835_I2S_FSM BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BCM2835_I2S_FSI BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BCM2835_I2S_FLEN(v) ((v) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define BCM2835_I2S_FSLEN(v) (v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define BCM2835_I2S_CHWEX BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define BCM2835_I2S_CHEN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define BCM2835_I2S_CHPOS(v) ((v) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define BCM2835_I2S_CHWID(v) (v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define BCM2835_I2S_CH1(v) ((v) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define BCM2835_I2S_CH2(v) (v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define BCM2835_I2S_CH1_POS(v) BCM2835_I2S_CH1(BCM2835_I2S_CHPOS(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define BCM2835_I2S_CH2_POS(v) BCM2835_I2S_CH2(BCM2835_I2S_CHPOS(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define BCM2835_I2S_TX_PANIC(v) ((v) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define BCM2835_I2S_RX_PANIC(v) ((v) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define BCM2835_I2S_TX(v) ((v) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BCM2835_I2S_RX(v) (v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BCM2835_I2S_INT_RXERR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BCM2835_I2S_INT_TXERR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BCM2835_I2S_INT_RXR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BCM2835_I2S_INT_TXW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Frame length register is 10 bit, maximum length 1024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BCM2835_I2S_MAX_FRAME_LENGTH 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* General device struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct bcm2835_i2s_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct snd_dmaengine_dai_dma_data dma_data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int tdm_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int rx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int tx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int frame_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct regmap *i2s_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) bool clk_prepared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void bcm2835_i2s_start_clock(struct bcm2835_i2s_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (dev->clk_prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) switch (master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case SND_SOC_DAIFMT_CBS_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) clk_prepare_enable(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dev->clk_prepared = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void bcm2835_i2s_stop_clock(struct bcm2835_i2s_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (dev->clk_prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) clk_disable_unprepare(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dev->clk_prepared = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void bcm2835_i2s_clear_fifos(struct bcm2835_i2s_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) bool tx, bool rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) uint32_t syncval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) uint32_t csreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) uint32_t i2s_active_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) bool clk_was_prepared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) uint32_t off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) uint32_t clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) off = tx ? BCM2835_I2S_TXON : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) off |= rx ? BCM2835_I2S_RXON : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) clr = tx ? BCM2835_I2S_TXCLR : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) clr |= rx ? BCM2835_I2S_RXCLR : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Backup the current state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) i2s_active_state = csreg & (BCM2835_I2S_RXON | BCM2835_I2S_TXON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Start clock if not running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) clk_was_prepared = dev->clk_prepared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (!clk_was_prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) bcm2835_i2s_start_clock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Stop I2S module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, off, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Clear the FIFOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Requires at least 2 PCM clock cycles to take effect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, clr, clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Wait for 2 PCM clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Toggle the SYNC flag. After 2 PCM clock cycles it can be read back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * FIXME: This does not seem to work for slave mode!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &syncval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) syncval &= BCM2835_I2S_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) BCM2835_I2S_SYNC, ~syncval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Wait for the SYNC flag changing it's state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) while (--timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if ((csreg & BCM2835_I2S_SYNC) != syncval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev_err(dev->dev, "I2S SYNC error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Stop clock if it was not running before */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (!clk_was_prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) bcm2835_i2s_stop_clock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Restore I2S state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) BCM2835_I2S_RXON | BCM2835_I2S_TXON, i2s_active_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int bcm2835_i2s_set_dai_fmt(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev->fmt = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int bcm2835_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned int ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (!ratio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev->tdm_slots = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ratio > BCM2835_I2S_MAX_FRAME_LENGTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dev->tdm_slots = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dev->rx_mask = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev->tx_mask = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dev->slot_width = ratio / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev->frame_length = ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int bcm2835_i2s_set_dai_tdm_slot(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned int tx_mask, unsigned int rx_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int slots, int width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (slots) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (slots < 0 || width < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Limit masks to available slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) rx_mask &= GENMASK(slots - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) tx_mask &= GENMASK(slots - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * The driver is limited to 2-channel setups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * Check that exactly 2 bits are set in the masks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (hweight_long((unsigned long) rx_mask) != 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) || hweight_long((unsigned long) tx_mask) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (slots * width > BCM2835_I2S_MAX_FRAME_LENGTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev->tdm_slots = slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev->rx_mask = rx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dev->tx_mask = tx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dev->slot_width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev->frame_length = slots * width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * Convert logical slot number into physical slot number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * If odd_offset is 0 sequential number is identical to logical number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * This is used for DSP modes with slot numbering 0 1 2 3 ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * Otherwise odd_offset defines the physical offset for odd numbered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * slots. This is used for I2S and left/right justified modes to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * translate from logical slot numbers 0 1 2 3 ... into physical slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * numbers 0 2 ... 3 4 ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int bcm2835_i2s_convert_slot(unsigned int slot, unsigned int odd_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!odd_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (slot & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return (slot >> 1) + odd_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return slot >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * Calculate channel position from mask and slot width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * Mask must contain exactly 2 set bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * Lowest set bit is channel 1 position, highest set bit channel 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * The constant offset is added to both channel positions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * If odd_offset is > 0 slot positions are translated to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * I2S-style TDM slot numbering ( 0 2 ... 3 4 ...) with odd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * logical slot numbers starting at physical slot odd_offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static void bcm2835_i2s_calc_channel_pos(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned int *ch1_pos, unsigned int *ch2_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned int mask, unsigned int width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned int bit_offset, unsigned int odd_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) *ch1_pos = bcm2835_i2s_convert_slot((ffs(mask) - 1), odd_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * width + bit_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) *ch2_pos = bcm2835_i2s_convert_slot((fls(mask) - 1), odd_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * width + bit_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned int data_length, data_delay, framesync_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned int slots, slot_width, odd_slot_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int frame_length, bclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int rx_mask, tx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned int rx_ch1_pos, rx_ch2_pos, tx_ch1_pos, tx_ch2_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned int mode, format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) bool bit_clock_master = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bool frame_sync_master = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) bool frame_start_falling_edge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) uint32_t csreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * If a stream is already enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * the registers are already set properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (csreg & (BCM2835_I2S_TXON | BCM2835_I2S_RXON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) data_length = params_width(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) data_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) odd_slot_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (dev->tdm_slots) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) slots = dev->tdm_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) slot_width = dev->slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) frame_length = dev->frame_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) rx_mask = dev->rx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) tx_mask = dev->tx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) bclk_rate = dev->frame_length * params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) slots = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) slot_width = params_width(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) rx_mask = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) tx_mask = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) frame_length = snd_soc_params_to_frame_size(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (frame_length < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return frame_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) bclk_rate = snd_soc_params_to_bclk(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (bclk_rate < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return bclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Check if data fits into slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (data_length > slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Check if CPU is bit clock master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case SND_SOC_DAIFMT_CBS_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) bit_clock_master = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case SND_SOC_DAIFMT_CBM_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) bit_clock_master = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Check if CPU is frame sync master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case SND_SOC_DAIFMT_CBM_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) frame_sync_master = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) case SND_SOC_DAIFMT_CBS_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) frame_sync_master = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Clock should only be set up here if CPU is clock master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (bit_clock_master &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) (!dev->clk_prepared || dev->clk_rate != bclk_rate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (dev->clk_prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) bcm2835_i2s_stop_clock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (dev->clk_rate != bclk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ret = clk_set_rate(dev->clk, bclk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev->clk_rate = bclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) bcm2835_i2s_start_clock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* Setup the frame format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) format = BCM2835_I2S_CHEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (data_length >= 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) format |= BCM2835_I2S_CHWEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) format |= BCM2835_I2S_CHWID((data_length-8)&0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* CH2 format is the same as for CH1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) format = BCM2835_I2S_CH1(format) | BCM2835_I2S_CH2(format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* I2S mode needs an even number of slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (slots & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * Use I2S-style logical slot numbering: even slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * are in first half of frame, odd slots in second half.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) odd_slot_offset = slots >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* MSB starts one cycle after frame start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) data_delay = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Setup frame sync signal for 50% duty cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) framesync_length = frame_length / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) frame_start_falling_edge = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (slots & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) odd_slot_offset = slots >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) data_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) framesync_length = frame_length / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) frame_start_falling_edge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) case SND_SOC_DAIFMT_RIGHT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (slots & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Odd frame lengths aren't supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (frame_length & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) odd_slot_offset = slots >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) data_delay = slot_width - data_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) framesync_length = frame_length / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) frame_start_falling_edge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) data_delay = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) framesync_length = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) frame_start_falling_edge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) case SND_SOC_DAIFMT_DSP_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) data_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) framesync_length = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) frame_start_falling_edge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) bcm2835_i2s_calc_channel_pos(&rx_ch1_pos, &rx_ch2_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) rx_mask, slot_width, data_delay, odd_slot_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) bcm2835_i2s_calc_channel_pos(&tx_ch1_pos, &tx_ch2_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) tx_mask, slot_width, data_delay, odd_slot_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * Transmitting data immediately after frame start, eg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * in left-justified or DSP mode A, only works stable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * if bcm2835 is the frame clock master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if ((!rx_ch1_pos || !tx_ch1_pos) && !frame_sync_master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_warn(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) "Unstable slave config detected, L/R may be swapped");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * Set format for both streams.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * We cannot set another frame length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * (and therefore word length) anyway,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * so the format will be the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) regmap_write(dev->i2s_regmap, BCM2835_I2S_RXC_A_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) | BCM2835_I2S_CH1_POS(rx_ch1_pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) | BCM2835_I2S_CH2_POS(rx_ch2_pos));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) regmap_write(dev->i2s_regmap, BCM2835_I2S_TXC_A_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) | BCM2835_I2S_CH1_POS(tx_ch1_pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) | BCM2835_I2S_CH2_POS(tx_ch2_pos));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* Setup the I2S mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (data_length <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * Use frame packed mode (2 channels per 32 bit word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * We cannot set another frame length in the second stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * (and therefore word length) anyway,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * so the format will be the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) mode |= BCM2835_I2S_FTXP | BCM2835_I2S_FRXP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) mode |= BCM2835_I2S_FLEN(frame_length - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) mode |= BCM2835_I2S_FSLEN(framesync_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* CLKM selects bcm2835 clock slave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (!bit_clock_master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mode |= BCM2835_I2S_CLKM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* FSM selects bcm2835 frame sync slave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!frame_sync_master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) mode |= BCM2835_I2S_FSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* CLKI selects normal clocking mode, sampling on rising edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) mode |= BCM2835_I2S_CLKI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* FSI selects frame start on falling edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (frame_start_falling_edge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mode |= BCM2835_I2S_FSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (!frame_start_falling_edge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) mode |= BCM2835_I2S_FSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) regmap_write(dev->i2s_regmap, BCM2835_I2S_MODE_A_REG, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Setup the DMA parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) BCM2835_I2S_RXTHR(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) | BCM2835_I2S_TXTHR(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) | BCM2835_I2S_DMAEN, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_DREQ_A_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) BCM2835_I2S_TX_PANIC(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) | BCM2835_I2S_RX_PANIC(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) | BCM2835_I2S_TX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) | BCM2835_I2S_RX(0x20), 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* Clear FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) bcm2835_i2s_clear_fifos(dev, true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dev_dbg(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) "slots: %d width: %d rx mask: 0x%02x tx_mask: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) slots, slot_width, rx_mask, tx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dev_dbg(dev->dev, "frame len: %d sync len: %d data len: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) frame_length, framesync_length, data_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dev_dbg(dev->dev, "rx pos: %d,%d tx pos: %d,%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) rx_ch1_pos, rx_ch2_pos, tx_ch1_pos, tx_ch2_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) dev_dbg(dev->dev, "sampling rate: %d bclk rate: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) params_rate(params), bclk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dev_dbg(dev->dev, "CLKM: %d CLKI: %d FSM: %d FSI: %d frame start: %s edge\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) !!(mode & BCM2835_I2S_CLKM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) !!(mode & BCM2835_I2S_CLKI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) !!(mode & BCM2835_I2S_FSM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) !!(mode & BCM2835_I2S_FSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) (mode & BCM2835_I2S_FSI) ? "falling" : "rising");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int bcm2835_i2s_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) uint32_t cs_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * Clear both FIFOs if the one that should be started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * is not empty at the moment. This should only happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * after overrun. Otherwise, hw_params would have cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * the FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &cs_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) && !(cs_reg & BCM2835_I2S_TXE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) bcm2835_i2s_clear_fifos(dev, true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) && (cs_reg & BCM2835_I2S_RXD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) bcm2835_i2s_clear_fifos(dev, false, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static void bcm2835_i2s_stop(struct bcm2835_i2s_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) uint32_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) mask = BCM2835_I2S_RXON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) mask = BCM2835_I2S_TXON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) regmap_update_bits(dev->i2s_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) BCM2835_I2S_CS_A_REG, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* Stop also the clock when not SND_SOC_DAIFMT_CONT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (!snd_soc_dai_active(dai) && !(dev->fmt & SND_SOC_DAIFMT_CONT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) bcm2835_i2s_stop_clock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int bcm2835_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) uint32_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) bcm2835_i2s_start_clock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) mask = BCM2835_I2S_RXON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) mask = BCM2835_I2S_TXON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) regmap_update_bits(dev->i2s_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) BCM2835_I2S_CS_A_REG, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) bcm2835_i2s_stop(dev, substream, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static int bcm2835_i2s_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (snd_soc_dai_active(dai))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* Should this still be running stop it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) bcm2835_i2s_stop_clock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* Enable PCM block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) BCM2835_I2S_EN, BCM2835_I2S_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * Disable STBY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * Requires at least 4 PCM clock cycles to take effect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) BCM2835_I2S_STBY, BCM2835_I2S_STBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static void bcm2835_i2s_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) bcm2835_i2s_stop(dev, substream, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* If both streams are stopped, disable module and clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (snd_soc_dai_active(dai))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* Disable the module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) BCM2835_I2S_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * Stopping clock is necessary, because stop does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * not stop the clock when SND_SOC_DAIFMT_CONT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) bcm2835_i2s_stop_clock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static const struct snd_soc_dai_ops bcm2835_i2s_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .startup = bcm2835_i2s_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .shutdown = bcm2835_i2s_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .prepare = bcm2835_i2s_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .trigger = bcm2835_i2s_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .hw_params = bcm2835_i2s_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .set_fmt = bcm2835_i2s_set_dai_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .set_bclk_ratio = bcm2835_i2s_set_dai_bclk_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .set_tdm_slot = bcm2835_i2s_set_dai_tdm_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static int bcm2835_i2s_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) snd_soc_dai_init_dma_data(dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static struct snd_soc_dai_driver bcm2835_i2s_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .name = "bcm2835-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .probe = bcm2835_i2s_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .rates = SNDRV_PCM_RATE_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .rate_max = 384000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .formats = SNDRV_PCM_FMTBIT_S16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) | SNDRV_PCM_FMTBIT_S24_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) | SNDRV_PCM_FMTBIT_S32_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .rates = SNDRV_PCM_RATE_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .rate_max = 384000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .formats = SNDRV_PCM_FMTBIT_S16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) | SNDRV_PCM_FMTBIT_S24_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) | SNDRV_PCM_FMTBIT_S32_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .ops = &bcm2835_i2s_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .symmetric_rates = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .symmetric_samplebits = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static bool bcm2835_i2s_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) case BCM2835_I2S_CS_A_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) case BCM2835_I2S_FIFO_A_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) case BCM2835_I2S_INTSTC_A_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) case BCM2835_I2S_GRAY_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static bool bcm2835_i2s_precious_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) case BCM2835_I2S_FIFO_A_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static const struct regmap_config bcm2835_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .max_register = BCM2835_I2S_GRAY_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .precious_reg = bcm2835_i2s_precious_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .volatile_reg = bcm2835_i2s_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static const struct snd_soc_component_driver bcm2835_i2s_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .name = "bcm2835-i2s-comp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static int bcm2835_i2s_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct bcm2835_i2s_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) const __be32 *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) dma_addr_t dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dev = devm_kzalloc(&pdev->dev, sizeof(*dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* get the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) dev->clk_prepared = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) dev->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (IS_ERR(dev->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ret = PTR_ERR(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) dev_dbg(&pdev->dev, "could not get clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dev_err(&pdev->dev, "could not get clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* Request ioarea */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) dev->i2s_regmap = devm_regmap_init_mmio(&pdev->dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) &bcm2835_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (IS_ERR(dev->i2s_regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return PTR_ERR(dev->i2s_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* Set the DMA address - we have to parse DT ourselves */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) addr = of_get_address(pdev->dev.of_node, 0, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) dev_err(&pdev->dev, "could not get DMA-register address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dma_base = be32_to_cpup(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dma_base + BCM2835_I2S_FIFO_A_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) dma_base + BCM2835_I2S_FIFO_A_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* Set the bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* Set burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * Set the PACK flag to enable S16_LE support (2 S16_LE values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * packed into 32-bit transfers).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) SND_DMAENGINE_PCM_DAI_FLAG_PACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) SND_DMAENGINE_PCM_DAI_FLAG_PACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* Store the pdev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) dev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) dev_set_drvdata(&pdev->dev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) ret = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) &bcm2835_i2s_component, &bcm2835_i2s_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static const struct of_device_id bcm2835_i2s_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) { .compatible = "brcm,bcm2835-i2s", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) MODULE_DEVICE_TABLE(of, bcm2835_i2s_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static struct platform_driver bcm2835_i2s_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .probe = bcm2835_i2s_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .name = "bcm2835-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .of_match_table = bcm2835_i2s_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) module_platform_driver(bcm2835_i2s_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) MODULE_ALIAS("platform:bcm2835-i2s");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) MODULE_DESCRIPTION("BCM2835 I2S interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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