Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Alchemy ALSA ASoC audio support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * (c) 2007-2011 MSC Vertriebsges.m.b.H.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *	Manuel Lauss <manuel.lauss@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef _AU1X_PCM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _AU1X_PCM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct au1xpsc_audio_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	unsigned long cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	struct snd_soc_dai_driver dai_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	unsigned long pm[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	int dmaids[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* easy access macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PSC_CTRL(x)	((x)->mmio + PSC_CTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PSC_SEL(x)	((x)->mmio + PSC_SEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define I2S_STAT(x)	((x)->mmio + PSC_I2SSTAT_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define I2S_CFG(x)	((x)->mmio + PSC_I2SCFG_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define I2S_PCR(x)	((x)->mmio + PSC_I2SPCR_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AC97_CFG(x)	((x)->mmio + PSC_AC97CFG_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AC97_CDC(x)	((x)->mmio + PSC_AC97CDC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AC97_EVNT(x)	((x)->mmio + PSC_AC97EVNT_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AC97_PCR(x)	((x)->mmio + PSC_AC97PCR_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AC97_RST(x)	((x)->mmio + PSC_AC97RST_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AC97_STAT(x)	((x)->mmio + PSC_AC97STAT_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif