^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Au12x0/Au1550 PSC ALSA ASoC audio support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (c) 2007-2008 MSC Vertriebsges.m.b.H.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Manuel Lauss <manuel.lauss@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Au1xxx-PSC I2S glue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * NOTE: so far only PSC slave mode (bit- and frameclock) is supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/mach-au1x00/au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mach-au1x00/au1xxx_psc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "psc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* supported I2S DAI hardware formats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AU1XPSC_I2S_DAIFMT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) SND_SOC_DAIFMT_NB_NF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* supported I2S direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AU1XPSC_I2S_DIR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) (SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AU1XPSC_I2S_RATES \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) SNDRV_PCM_RATE_8000_192000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AU1XPSC_I2S_FMTS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I2SSTAT_BUSY(stype) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_I2SSTAT_TB : PSC_I2SSTAT_RB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I2SPCR_START(stype) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_I2SPCR_TS : PSC_I2SPCR_RS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define I2SPCR_STOP(stype) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_I2SPCR_TP : PSC_I2SPCR_RP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define I2SPCR_CLRFIFO(stype) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_I2SPCR_TC : PSC_I2SPCR_RC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int au1xpsc_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned long ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ct = pscdata->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ct &= ~(PSC_I2SCFG_XM | PSC_I2SCFG_MLJ); /* left-justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ct |= PSC_I2SCFG_XM; /* enable I2S mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) case SND_SOC_DAIFMT_MSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) case SND_SOC_DAIFMT_LSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ct |= PSC_I2SCFG_MLJ; /* LSB (right-) justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ct &= ~(PSC_I2SCFG_BI | PSC_I2SCFG_WI); /* IB-IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ct |= PSC_I2SCFG_BI | PSC_I2SCFG_WI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ct |= PSC_I2SCFG_BI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ct |= PSC_I2SCFG_WI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case SND_SOC_DAIFMT_CBM_CFM: /* CODEC master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ct |= PSC_I2SCFG_MS; /* PSC I2S slave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) case SND_SOC_DAIFMT_CBS_CFS: /* CODEC slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ct &= ~PSC_I2SCFG_MS; /* PSC I2S Master mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) pscdata->cfg = ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int au1xpsc_i2s_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int cfgbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* check if the PSC is already streaming data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) stat = __raw_readl(I2S_STAT(pscdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* reject parameters not currently set up in hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) cfgbits = __raw_readl(I2S_CFG(pscdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if ((PSC_I2SCFG_GET_LEN(cfgbits) != params->msbits) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) (params_rate(params) != pscdata->rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* set sample bitdepth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pscdata->cfg &= ~(0x1f << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pscdata->cfg |= PSC_I2SCFG_SET_LEN(params->msbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* remember current rate for other stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pscdata->rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Configure PSC late: on my devel systems the codec is I2S master and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * supplies the i2sbitclock __AND__ i2sMclk (!) to the PSC unit. ASoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * uses aggressive PM and switches the codec off when it is not in use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * which also means the PSC unit doesn't get any clocks and is therefore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * dead. That's why this chunk here gets called from the trigger callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * because I can be reasonably certain the codec is driving the clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int au1xpsc_i2s_configure(struct au1xpsc_audio_data *pscdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned long tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* bring PSC out of sleep, and configure I2S unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) __raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) tmo = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) while (!(__raw_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_SR) && tmo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) tmo--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (!tmo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) goto psc_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) __raw_writel(0, I2S_CFG(pscdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) __raw_writel(pscdata->cfg | PSC_I2SCFG_DE_ENABLE, I2S_CFG(pscdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* wait for I2S controller to become ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) tmo = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) while (!(__raw_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_DR) && tmo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) tmo--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (tmo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) psc_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) __raw_writel(0, I2S_CFG(pscdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) __raw_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int au1xpsc_i2s_start(struct au1xpsc_audio_data *pscdata, int stype)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned long tmo, stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* if both TX and RX are idle, configure the PSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) stat = __raw_readl(I2S_STAT(pscdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (!(stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = au1xpsc_i2s_configure(pscdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) __raw_writel(I2SPCR_CLRFIFO(stype), I2S_PCR(pscdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __raw_writel(I2SPCR_START(stype), I2S_PCR(pscdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* wait for start confirmation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) tmo = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) while (!(__raw_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) tmo--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!tmo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) __raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int au1xpsc_i2s_stop(struct au1xpsc_audio_data *pscdata, int stype)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned long tmo, stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) __raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* wait for stop confirmation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) tmo = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) while ((__raw_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) tmo--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* if both TX and RX are idle, disable PSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) stat = __raw_readl(I2S_STAT(pscdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (!(stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) __raw_writel(0, I2S_CFG(pscdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) __raw_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int au1xpsc_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int ret, stype = substream->stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = au1xpsc_i2s_start(pscdata, stype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret = au1xpsc_i2s_stop(pscdata, stype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int au1xpsc_i2s_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) snd_soc_dai_set_dma_data(dai, substream, &pscdata->dmaids[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct snd_soc_dai_ops au1xpsc_i2s_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .startup = au1xpsc_i2s_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .trigger = au1xpsc_i2s_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .hw_params = au1xpsc_i2s_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .set_fmt = au1xpsc_i2s_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const struct snd_soc_dai_driver au1xpsc_i2s_dai_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .rates = AU1XPSC_I2S_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .formats = AU1XPSC_I2S_FMTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .channels_max = 8, /* 2 without external help */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .rates = AU1XPSC_I2S_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .formats = AU1XPSC_I2S_FMTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .channels_max = 8, /* 2 without external help */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .ops = &au1xpsc_i2s_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct snd_soc_component_driver au1xpsc_i2s_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .name = "au1xpsc-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int au1xpsc_i2s_drvprobe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct resource *dmares;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned long sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct au1xpsc_audio_data *wd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) wd = devm_kzalloc(&pdev->dev, sizeof(struct au1xpsc_audio_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (!wd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) wd->mmio = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (IS_ERR(wd->mmio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return PTR_ERR(wd->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (!dmares)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) wd->dmaids[SNDRV_PCM_STREAM_PLAYBACK] = dmares->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dmares = platform_get_resource(pdev, IORESOURCE_DMA, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (!dmares)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) wd->dmaids[SNDRV_PCM_STREAM_CAPTURE] = dmares->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* preserve PSC clock source set up by platform (dev.platform_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * is already occupied by soc layer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) __raw_writel(PSC_SEL_PS_I2SMODE | sel, PSC_SEL(wd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) __raw_writel(0, I2S_CFG(wd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* preconfigure: set max rx/tx fifo depths */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) wd->cfg |= PSC_I2SCFG_RT_FIFO8 | PSC_I2SCFG_TT_FIFO8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* don't wait for I2S core to become ready now; clocks may not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * be running yet; depending on clock input for PSC a wait might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * time out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* name the DAI like this device instance ("au1xpsc-i2s.PSCINDEX") */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) memcpy(&wd->dai_drv, &au1xpsc_i2s_dai_template,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) sizeof(struct snd_soc_dai_driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) wd->dai_drv.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) platform_set_drvdata(pdev, wd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) &au1xpsc_i2s_component, &wd->dai_drv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int au1xpsc_i2s_drvremove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct au1xpsc_audio_data *wd = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) __raw_writel(0, I2S_CFG(wd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int au1xpsc_i2s_drvsuspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* save interesting register and disable PSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) wd->pm[0] = __raw_readl(PSC_SEL(wd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) __raw_writel(0, I2S_CFG(wd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int au1xpsc_i2s_drvresume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* select I2S mode and PSC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) __raw_writel(0, PSC_SEL(wd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) __raw_writel(wd->pm[0], PSC_SEL(wd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const struct dev_pm_ops au1xpsci2s_pmops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .suspend = au1xpsc_i2s_drvsuspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .resume = au1xpsc_i2s_drvresume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define AU1XPSCI2S_PMOPS &au1xpsci2s_pmops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define AU1XPSCI2S_PMOPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static struct platform_driver au1xpsc_i2s_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .name = "au1xpsc_i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .pm = AU1XPSCI2S_PMOPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .probe = au1xpsc_i2s_drvprobe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .remove = au1xpsc_i2s_drvremove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) module_platform_driver(au1xpsc_i2s_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MODULE_DESCRIPTION("Au12x0/Au1550 PSC I2S ALSA ASoC audio driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MODULE_AUTHOR("Manuel Lauss");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags