Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Au12x0/Au1550 PSC ALSA ASoC audio support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * (c) 2007-2008 MSC Vertriebsges.m.b.H.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	Manuel Lauss <manuel.lauss@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * DMA glue for Au1x-PSC audio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/mach-au1x00/au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/mach-au1x00/au1xxx_dbdma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/mach-au1x00/au1xxx_psc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include "psc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /*#define PCM_DEBUG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define DRV_NAME "dbdma2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MSG(x...)	printk(KERN_INFO "au1xpsc_pcm: " x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #ifdef PCM_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DBG		MSG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DBG(x...)	do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) struct au1xpsc_audio_dmadata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	/* DDMA control data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	unsigned int ddma_id;		/* DDMA direction ID for this PSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	u32 ddma_chan;			/* DDMA context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	/* PCM context (for irq handlers) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	unsigned long curr_period;	/* current segment DDMA is working on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	unsigned long q_period;		/* queue period(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	dma_addr_t dma_area;		/* address of queued DMA area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	dma_addr_t dma_area_s;		/* start address of DMA area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	unsigned long pos;		/* current byte position being played */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	unsigned long periods;		/* number of SG segments in total */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	unsigned long period_bytes;	/* size in bytes of one SG segment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	/* runtime data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	int msbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * These settings are somewhat okay, at least on my machine audio plays
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * almost skip-free. Especially the 64kB buffer seems to help a LOT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define AU1XPSC_PERIOD_MIN_BYTES	1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define AU1XPSC_BUFFER_MIN_BYTES	65536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* PCM hardware DMA capabilities - platform specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static const struct snd_pcm_hardware au1xpsc_pcm_hardware = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	.info		  = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			    SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.period_bytes_min = AU1XPSC_PERIOD_MIN_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	.period_bytes_max = 4096 * 1024 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	.periods_min	  = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	.periods_max	  = 4096,	/* 2 to as-much-as-you-like */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.buffer_bytes_max = 4096 * 1024 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.fifo_size	  = 16,		/* fifo entries of AC97/I2S PSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static void au1x_pcm_queue_tx(struct au1xpsc_audio_dmadata *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	au1xxx_dbdma_put_source(cd->ddma_chan, cd->dma_area,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 				cd->period_bytes, DDMA_FLAGS_IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/* update next-to-queue period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	++cd->q_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	cd->dma_area += cd->period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	if (cd->q_period >= cd->periods) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		cd->q_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		cd->dma_area = cd->dma_area_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static void au1x_pcm_queue_rx(struct au1xpsc_audio_dmadata *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	au1xxx_dbdma_put_dest(cd->ddma_chan, cd->dma_area,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			      cd->period_bytes, DDMA_FLAGS_IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/* update next-to-queue period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	++cd->q_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	cd->dma_area += cd->period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (cd->q_period >= cd->periods) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		cd->q_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		cd->dma_area = cd->dma_area_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void au1x_pcm_dmatx_cb(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct au1xpsc_audio_dmadata *cd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	cd->pos += cd->period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	if (++cd->curr_period >= cd->periods) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		cd->pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		cd->curr_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	snd_pcm_period_elapsed(cd->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	au1x_pcm_queue_tx(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void au1x_pcm_dmarx_cb(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct au1xpsc_audio_dmadata *cd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	cd->pos += cd->period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (++cd->curr_period >= cd->periods) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		cd->pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		cd->curr_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	snd_pcm_period_elapsed(cd->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	au1x_pcm_queue_rx(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void au1x_pcm_dbdma_free(struct au1xpsc_audio_dmadata *pcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (pcd->ddma_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		au1xxx_dbdma_stop(pcd->ddma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		au1xxx_dbdma_reset(pcd->ddma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		au1xxx_dbdma_chan_free(pcd->ddma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		pcd->ddma_chan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		pcd->msbits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* in case of missing DMA ring or changed TX-source / RX-dest bit widths,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * allocate (or reallocate) a 2-descriptor DMA ring with bit depth according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * to ALSA-supplied sample depth.  This is due to limitations in the dbdma api
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * (cannot adjust source/dest widths of already allocated descriptor ring).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int au1x_pcm_dbdma_realloc(struct au1xpsc_audio_dmadata *pcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 				 int stype, int msbits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* DMA only in 8/16/32 bit widths */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (msbits == 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		msbits = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	/* check current config: correct bits and descriptors allocated? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if ((pcd->ddma_chan) && (msbits == pcd->msbits))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		goto out;	/* all ok! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	au1x_pcm_dbdma_free(pcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (stype == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		pcd->ddma_chan = au1xxx_dbdma_chan_alloc(pcd->ddma_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 					DSCR_CMD0_ALWAYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 					au1x_pcm_dmarx_cb, (void *)pcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		pcd->ddma_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 					pcd->ddma_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 					au1x_pcm_dmatx_cb, (void *)pcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (!pcd->ddma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	au1xxx_dbdma_set_devwidth(pcd->ddma_chan, msbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	au1xxx_dbdma_ring_alloc(pcd->ddma_chan, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	pcd->msbits = msbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	au1xxx_dbdma_stop(pcd->ddma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	au1xxx_dbdma_reset(pcd->ddma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static inline struct au1xpsc_audio_dmadata *to_dmadata(struct snd_pcm_substream *ss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 						       struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct au1xpsc_audio_dmadata *pcd = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return &pcd[ss->stream];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int au1xpsc_pcm_hw_params(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 				 struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 				 struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	struct au1xpsc_audio_dmadata *pcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	int stype, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	stype = substream->stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	pcd = to_dmadata(substream, component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	DBG("runtime->dma_area = 0x%08lx dma_addr_t = 0x%08lx dma_size = %zu "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	    "runtime->min_align %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		(unsigned long)runtime->dma_area,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		(unsigned long)runtime->dma_addr, runtime->dma_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		runtime->min_align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	DBG("bits %d  frags %d  frag_bytes %d  is_rx %d\n", params->msbits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		params_periods(params), params_period_bytes(params), stype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	ret = au1x_pcm_dbdma_realloc(pcd, stype, params->msbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		MSG("DDMA channel (re)alloc failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	pcd->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	pcd->period_bytes = params_period_bytes(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	pcd->periods = params_periods(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	pcd->dma_area_s = pcd->dma_area = runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	pcd->q_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	pcd->curr_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	pcd->pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int au1xpsc_pcm_prepare(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			       struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	struct au1xpsc_audio_dmadata *pcd = to_dmadata(substream, component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	au1xxx_dbdma_reset(pcd->ddma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		au1x_pcm_queue_rx(pcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		au1x_pcm_queue_rx(pcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		au1x_pcm_queue_tx(pcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		au1x_pcm_queue_tx(pcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int au1xpsc_pcm_trigger(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			       struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	u32 c = to_dmadata(substream, component)->ddma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		au1xxx_dbdma_start(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		au1xxx_dbdma_stop(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) au1xpsc_pcm_pointer(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		    struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	return bytes_to_frames(substream->runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			       to_dmadata(substream, component)->pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int au1xpsc_pcm_open(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			    struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	struct au1xpsc_audio_dmadata *pcd = to_dmadata(substream, component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	int stype = substream->stream, *dmaids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	dmaids = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (!dmaids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		return -ENODEV;	/* whoa, has ordering changed? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	pcd->ddma_id = dmaids[stype];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	snd_soc_set_runtime_hwparams(substream, &au1xpsc_pcm_hardware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int au1xpsc_pcm_close(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			     struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	au1x_pcm_dbdma_free(to_dmadata(substream, component));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int au1xpsc_pcm_new(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			   struct snd_soc_pcm_runtime *rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	struct snd_card *card = rtd->card->snd_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	struct snd_pcm *pcm = rtd->pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		card->dev, AU1XPSC_BUFFER_MIN_BYTES, (4096 * 1024) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* au1xpsc audio platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static struct snd_soc_component_driver au1xpsc_soc_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.open		= au1xpsc_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.close		= au1xpsc_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.hw_params	= au1xpsc_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.prepare	= au1xpsc_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.trigger	= au1xpsc_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.pointer	= au1xpsc_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.pcm_construct	= au1xpsc_pcm_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int au1xpsc_pcm_drvprobe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	struct au1xpsc_audio_dmadata *dmadata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	dmadata = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			       2, sizeof(struct au1xpsc_audio_dmadata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			       GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (!dmadata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	platform_set_drvdata(pdev, dmadata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	return devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 					&au1xpsc_soc_component, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static struct platform_driver au1xpsc_pcm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		.name	= "au1xpsc-pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	.probe		= au1xpsc_pcm_drvprobe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) module_platform_driver(au1xpsc_pcm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) MODULE_DESCRIPTION("Au12x0/Au1550 PSC Audio DMA driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MODULE_AUTHOR("Manuel Lauss");