Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Au1000/Au1500/Au1100 AC97C controller driver for ASoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * based on the old ALSA driver originally written by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *			Charles Eidsness <charles@cooper-street.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/mach-au1x00/au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "psc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* register offsets and bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AC97_CONFIG	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AC97_STATUS	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define AC97_DATA	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AC97_CMDRESP	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AC97_ENABLE	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CFG_RC(x)	(((x) & 0x3ff) << 13)	/* valid rx slots mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CFG_XS(x)	(((x) & 0x3ff) << 3)	/* valid tx slots mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CFG_SG		(1 << 2)	/* sync gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CFG_SN		(1 << 1)	/* sync control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CFG_RS		(1 << 0)	/* acrst# control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define STAT_XU		(1 << 11)	/* tx underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define STAT_XO		(1 << 10)	/* tx overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define STAT_RU		(1 << 9)	/* rx underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define STAT_RO		(1 << 8)	/* rx overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define STAT_RD		(1 << 7)	/* codec ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define STAT_CP		(1 << 6)	/* command pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define STAT_TE		(1 << 4)	/* tx fifo empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define STAT_TF		(1 << 3)	/* tx fifo full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define STAT_RE		(1 << 1)	/* rx fifo empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define STAT_RF		(1 << 0)	/* rx fifo full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CMD_SET_DATA(x)	(((x) & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CMD_GET_DATA(x)	((x) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CMD_READ	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CMD_WRITE	(0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CMD_IDX(x)	((x) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define EN_D		(1 << 1)	/* DISable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define EN_CE		(1 << 0)	/* clock enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /* how often to retry failed codec register reads/writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define AC97_RW_RETRIES	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define AC97_RATES	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	SNDRV_PCM_RATE_CONTINUOUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define AC97_FMTS	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* instance data. There can be only one, MacLeod!!!!, fortunately there IS only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * once AC97C on early Alchemy chips. The newer ones aren't so lucky.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static struct au1xpsc_audio_data *ac97c_workdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define ac97_to_ctx(x)		ac97c_workdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static inline unsigned long RD(struct au1xpsc_audio_data *ctx, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	return __raw_readl(ctx->mmio + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	__raw_writel(v, ctx->mmio + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static unsigned short au1xac97c_ac97_read(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 					  unsigned short r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	unsigned int tmo, retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	unsigned long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	data = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	retry = AC97_RW_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		mutex_lock(&ctx->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		tmo = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		while ((RD(ctx, AC97_STATUS) & STAT_CP) && --tmo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			udelay(21);	/* wait an ac97 frame time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		if (!tmo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			pr_debug("ac97rd timeout #1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		WR(ctx, AC97_CMDRESP, CMD_IDX(r) | CMD_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		/* stupid errata: data is only valid for 21us, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		 * poll, Forrest, poll...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		tmo = 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		while ((RD(ctx, AC97_STATUS) & STAT_CP) && --tmo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			asm volatile ("nop");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		data = RD(ctx, AC97_CMDRESP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		if (!tmo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			pr_debug("ac97rd timeout #2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		mutex_unlock(&ctx->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	} while (--retry && !tmo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	pr_debug("AC97RD %04x %04lx %d\n", r, data, retry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	return retry ? data & 0xffff : 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void au1xac97c_ac97_write(struct snd_ac97 *ac97, unsigned short r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 				 unsigned short v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	unsigned int tmo, retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	retry = AC97_RW_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		mutex_lock(&ctx->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		for (tmo = 5; (RD(ctx, AC97_STATUS) & STAT_CP) && tmo; tmo--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			udelay(21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		if (!tmo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			pr_debug("ac97wr timeout #1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		WR(ctx, AC97_CMDRESP, CMD_WRITE | CMD_IDX(r) | CMD_SET_DATA(v));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		for (tmo = 10; (RD(ctx, AC97_STATUS) & STAT_CP) && tmo; tmo--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			udelay(21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		if (!tmo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			pr_debug("ac97wr timeout #2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		mutex_unlock(&ctx->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	} while (--retry && !tmo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	pr_debug("AC97WR %04x %04x %d\n", r, v, retry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void au1xac97c_ac97_warm_reset(struct snd_ac97 *ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG | CFG_SN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	WR(ctx, AC97_CONFIG, ctx->cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void au1xac97c_ac97_cold_reset(struct snd_ac97 *ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	WR(ctx, AC97_CONFIG, ctx->cfg | CFG_RS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	msleep(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	WR(ctx, AC97_CONFIG, ctx->cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* wait for codec ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	i = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	while (((RD(ctx, AC97_STATUS) & STAT_RD) == 0) && --i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (!i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		printk(KERN_ERR "ac97c: codec not ready after cold reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* AC97 controller operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static struct snd_ac97_bus_ops ac97c_bus_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.read		= au1xac97c_ac97_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.write		= au1xac97c_ac97_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.reset		= au1xac97c_ac97_cold_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.warm_reset	= au1xac97c_ac97_warm_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int alchemy_ac97c_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 				 struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	snd_soc_dai_set_dma_data(dai, substream, &ctx->dmaids[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct snd_soc_dai_ops alchemy_ac97c_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.startup		= alchemy_ac97c_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int au1xac97c_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return ac97c_workdata ? 0 : -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct snd_soc_dai_driver au1xac97c_dai_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.name			= "alchemy-ac97c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.probe			= au1xac97c_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		.rates		= AC97_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		.formats	= AC97_FMTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		.channels_min	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		.channels_max	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		.rates		= AC97_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		.formats	= AC97_FMTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		.channels_min	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		.channels_max	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.ops			= &alchemy_ac97c_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const struct snd_soc_component_driver au1xac97c_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	.name		= "au1xac97c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int au1xac97c_drvprobe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	struct resource *iores, *dmares;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct au1xpsc_audio_data *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	mutex_init(&ctx->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (!iores)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (!devm_request_mem_region(&pdev->dev, iores->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 				     resource_size(iores),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 				     pdev->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	ctx->mmio = devm_ioremap(&pdev->dev, iores->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 					 resource_size(iores));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (!ctx->mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (!dmares)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	ctx->dmaids[SNDRV_PCM_STREAM_PLAYBACK] = dmares->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	dmares = platform_get_resource(pdev, IORESOURCE_DMA, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (!dmares)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	ctx->dmaids[SNDRV_PCM_STREAM_CAPTURE] = dmares->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	/* switch it on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	WR(ctx, AC97_ENABLE, EN_D | EN_CE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	WR(ctx, AC97_ENABLE, EN_CE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	ctx->cfg = CFG_RC(3) | CFG_XS(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	WR(ctx, AC97_CONFIG, ctx->cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	platform_set_drvdata(pdev, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	ret = snd_soc_set_ac97_ops(&ac97c_bus_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	ret = snd_soc_register_component(&pdev->dev, &au1xac97c_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 					 &au1xac97c_dai_driver, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	ac97c_workdata = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int au1xac97c_drvremove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	struct au1xpsc_audio_data *ctx = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	snd_soc_unregister_component(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	WR(ctx, AC97_ENABLE, EN_D);	/* clock off, disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	ac97c_workdata = NULL;	/* MDEV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int au1xac97c_drvsuspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	struct au1xpsc_audio_data *ctx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	WR(ctx, AC97_ENABLE, EN_D);	/* clock off, disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int au1xac97c_drvresume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	struct au1xpsc_audio_data *ctx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	WR(ctx, AC97_ENABLE, EN_D | EN_CE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	WR(ctx, AC97_ENABLE, EN_CE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	WR(ctx, AC97_CONFIG, ctx->cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const struct dev_pm_ops au1xpscac97_pmops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.suspend	= au1xac97c_drvsuspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	.resume		= au1xac97c_drvresume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define AU1XPSCAC97_PMOPS (&au1xpscac97_pmops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define AU1XPSCAC97_PMOPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static struct platform_driver au1xac97c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		.name	= "alchemy-ac97c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		.pm	= AU1XPSCAC97_PMOPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	.probe		= au1xac97c_drvprobe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	.remove		= au1xac97c_drvremove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) module_platform_driver(au1xac97c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MODULE_DESCRIPTION("Au1000/1500/1100 AC97C ASoC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MODULE_AUTHOR("Manuel Lauss");