^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Driver for Microchip S/PDIF TX Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/asoundef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * ---- S/PDIF Transmitter Controller Register map ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPDIFTX_CR 0x00 /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SPDIFTX_MR 0x04 /* Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPDIFTX_CDR 0x0C /* Common Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPDIFTX_IER 0x14 /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPDIFTX_IDR 0x18 /* Interrupt Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPDIFTX_IMR 0x1C /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPDIFTX_ISR 0x20 /* Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPDIFTX_CH1UD(reg) (0x50 + (reg) * 4) /* User Data 1 Register x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPDIFTX_CH1S(reg) (0x80 + (reg) * 4) /* Channel Status 1 Register x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPDIFTX_VERSION 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * ---- Control Register (Write-only) ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPDIFTX_CR_SWRST BIT(0) /* Software Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPDIFTX_CR_FCLR BIT(1) /* FIFO clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * ---- Mode Register (Read/Write) ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Transmit Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPDIFTX_MR_TXEN_MASK GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPDIFTX_MR_TXEN_DISABLE (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPDIFTX_MR_TXEN_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Multichannel Transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPDIFTX_MR_MULTICH_MASK GENAMSK(1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPDIFTX_MR_MULTICH_MONO (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPDIFTX_MR_MULTICH_DUAL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Data Word Endian Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPDIFTX_MR_ENDIAN_MASK GENMASK(2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPDIFTX_MR_ENDIAN_LITTLE (0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPDIFTX_MR_ENDIAN_BIG (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Data Justification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SPDIFTX_MR_JUSTIFY_MASK GENMASK(3, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SPDIFTX_MR_JUSTIFY_LSB (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SPDIFTX_MR_JUSTIFY_MSB (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Common Audio Register Transfer Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SPDIFTX_MR_CMODE_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SPDIFTX_MR_CMODE_INDEX_ACCESS (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SPDIFTX_MR_CMODE_TOGGLE_ACCESS (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SPDIFTX_MR_CMODE_INTERLVD_ACCESS (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Valid Bits per Sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SPDIFTX_MR_VBPS_MASK GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SPDIFTX_MR_VBPS(bps) (((bps) << 8) & SPDIFTX_MR_VBPS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Chunk Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SPDIFTX_MR_CHUNK_MASK GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SPDIFTX_MR_CHUNK(size) (((size) << 16) & SPDIFTX_MR_CHUNK_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Validity Bits for Channels 1 and 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SPDIFTX_MR_VALID1 BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SPDIFTX_MR_VALID2 BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Disable Null Frame on underrrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SPDIFTX_MR_DNFR_MASK GENMASK(27, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SPDIFTX_MR_DNFR_INVALID (0 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SPDIFTX_MR_DNFR_VALID (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Bytes per Sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SPDIFTX_MR_BPS_MASK GENMASK(29, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SPDIFTX_MR_BPS(bytes) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ((((bytes) - 1) << 28) & SPDIFTX_MR_BPS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * ---- Interrupt Enable/Disable/Mask/Status Register (Write/Read-only) ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SPDIFTX_IR_TXRDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SPDIFTX_IR_TXEMPTY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SPDIFTX_IR_TXFULL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SPDIFTX_IR_TXCHUNK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SPDIFTX_IR_TXUDR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SPDIFTX_IR_TXOVR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SPDIFTX_IR_CSRDY BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SPDIFTX_IR_UDRDY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SPDIFTX_IR_TXRDYCH(ch) BIT((ch) + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SPDIFTX_IR_SECE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SPDIFTX_IR_TXUDRCH(ch) BIT((ch) + 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SPDIFTX_IR_BEND BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static bool mchp_spdiftx_readable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case SPDIFTX_MR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case SPDIFTX_IMR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) case SPDIFTX_ISR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) case SPDIFTX_CH1UD(0):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case SPDIFTX_CH1UD(1):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case SPDIFTX_CH1UD(2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case SPDIFTX_CH1UD(3):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case SPDIFTX_CH1UD(4):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case SPDIFTX_CH1UD(5):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) case SPDIFTX_CH1S(0):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case SPDIFTX_CH1S(1):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case SPDIFTX_CH1S(2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case SPDIFTX_CH1S(3):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) case SPDIFTX_CH1S(4):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case SPDIFTX_CH1S(5):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static bool mchp_spdiftx_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) case SPDIFTX_CR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case SPDIFTX_MR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case SPDIFTX_CDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case SPDIFTX_IER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case SPDIFTX_IDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case SPDIFTX_CH1UD(0):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case SPDIFTX_CH1UD(1):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case SPDIFTX_CH1UD(2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case SPDIFTX_CH1UD(3):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case SPDIFTX_CH1UD(4):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case SPDIFTX_CH1UD(5):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case SPDIFTX_CH1S(0):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case SPDIFTX_CH1S(1):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case SPDIFTX_CH1S(2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) case SPDIFTX_CH1S(3):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case SPDIFTX_CH1S(4):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case SPDIFTX_CH1S(5):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static bool mchp_spdiftx_precious_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case SPDIFTX_CDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) case SPDIFTX_ISR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct regmap_config mchp_spdiftx_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .max_register = SPDIFTX_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .readable_reg = mchp_spdiftx_readable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .writeable_reg = mchp_spdiftx_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .precious_reg = mchp_spdiftx_precious_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SPDIFTX_GCLK_RATIO 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SPDIFTX_CS_BITS 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SPDIFTX_UD_BITS 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct mchp_spdiftx_mixer_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned char ch_stat[SPDIFTX_CS_BITS / 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned char user_data[SPDIFTX_UD_BITS / 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) spinlock_t lock; /* exclusive access to control data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct mchp_spdiftx_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct mchp_spdiftx_mixer_control control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct snd_dmaengine_dai_dma_data playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct clk *gclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) const struct mchp_i2s_caps *caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int gclk_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static inline int mchp_spdiftx_is_running(struct mchp_spdiftx_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) regmap_read(dev->regmap, SPDIFTX_MR, &mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return !!(mr & SPDIFTX_MR_TXEN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void mchp_spdiftx_channel_status_write(struct mchp_spdiftx_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat) / 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) val = (ctrl->ch_stat[(i * 4) + 0] << 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) (ctrl->ch_stat[(i * 4) + 1] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) (ctrl->ch_stat[(i * 4) + 2] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) (ctrl->ch_stat[(i * 4) + 3] << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) regmap_write(dev->regmap, SPDIFTX_CH1S(i), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void mchp_spdiftx_user_data_write(struct mchp_spdiftx_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) for (i = 0; i < ARRAY_SIZE(ctrl->user_data) / 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) val = (ctrl->user_data[(i * 4) + 0] << 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) (ctrl->user_data[(i * 4) + 1] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) (ctrl->user_data[(i * 4) + 2] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) (ctrl->user_data[(i * 4) + 3] << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) regmap_write(dev->regmap, SPDIFTX_CH1UD(i), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static irqreturn_t mchp_spdiftx_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct mchp_spdiftx_dev *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 sr, imr, pending, idr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) regmap_read(dev->regmap, SPDIFTX_ISR, &sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) regmap_read(dev->regmap, SPDIFTX_IMR, &imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) pending = sr & imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (!pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (pending & SPDIFTX_IR_TXUDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_warn(dev->dev, "underflow detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) idr |= SPDIFTX_IR_TXUDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (pending & SPDIFTX_IR_TXOVR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_warn(dev->dev, "overflow detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) idr |= SPDIFTX_IR_TXOVR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (pending & SPDIFTX_IR_UDRDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) spin_lock(&ctrl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mchp_spdiftx_user_data_write(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) spin_unlock(&ctrl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) idr |= SPDIFTX_IR_UDRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (pending & SPDIFTX_IR_CSRDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) spin_lock(&ctrl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) mchp_spdiftx_channel_status_write(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) spin_unlock(&ctrl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) idr |= SPDIFTX_IR_CSRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) regmap_write(dev->regmap, SPDIFTX_IDR, idr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int mchp_spdiftx_dai_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Software reset the IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) regmap_write(dev->regmap, SPDIFTX_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static void mchp_spdiftx_dai_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) regmap_write(dev->regmap, SPDIFTX_IDR, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int mchp_spdiftx_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* do not start/stop while channel status or user data is updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) spin_lock(&ctrl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) regmap_read(dev->regmap, SPDIFTX_MR, &mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) running = !!(mr & SPDIFTX_MR_TXEN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (!running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) mr &= ~SPDIFTX_MR_TXEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) mr |= SPDIFTX_MR_TXEN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) mr &= ~SPDIFTX_MR_TXEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) mr |= SPDIFTX_MR_TXEN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) spin_unlock(&ctrl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ret = regmap_write(dev->regmap, SPDIFTX_MR, mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) spin_unlock(&ctrl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev_err(dev->dev, "unable to disable TX: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static int mchp_spdiftx_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned int bps = params_physical_width(params) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) __func__, params_rate(params), params_format(params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) params_width(params), params_channels(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dev_err(dev->dev, "Capture is not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) regmap_read(dev->regmap, SPDIFTX_MR, &mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (mr & SPDIFTX_MR_TXEN_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev_err(dev->dev, "PCM already running\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Defaults: Toggle mode, justify to LSB, chunksize 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) mr = SPDIFTX_MR_CMODE_TOGGLE_ACCESS | SPDIFTX_MR_JUSTIFY_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev->playback.maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) switch (params_channels(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) mr |= SPDIFTX_MR_MULTICH_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) mr |= SPDIFTX_MR_MULTICH_DUAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (bps > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev->playback.maxburst = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_err(dev->dev, "unsupported number of channels: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) params_channels(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) mr |= SPDIFTX_MR_CHUNK(dev->playback.maxburst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case SNDRV_PCM_FORMAT_S8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) mr |= SPDIFTX_MR_VBPS(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case SNDRV_PCM_FORMAT_S16_BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) mr |= SPDIFTX_MR_ENDIAN_BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) mr |= SPDIFTX_MR_VBPS(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) case SNDRV_PCM_FORMAT_S18_3BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) mr |= SPDIFTX_MR_ENDIAN_BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) case SNDRV_PCM_FORMAT_S18_3LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) mr |= SPDIFTX_MR_VBPS(18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) case SNDRV_PCM_FORMAT_S20_3BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) mr |= SPDIFTX_MR_ENDIAN_BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) case SNDRV_PCM_FORMAT_S20_3LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) mr |= SPDIFTX_MR_VBPS(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) case SNDRV_PCM_FORMAT_S24_3BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) mr |= SPDIFTX_MR_ENDIAN_BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case SNDRV_PCM_FORMAT_S24_3LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) mr |= SPDIFTX_MR_VBPS(24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case SNDRV_PCM_FORMAT_S24_BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) mr |= SPDIFTX_MR_ENDIAN_BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case SNDRV_PCM_FORMAT_S24_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mr |= SPDIFTX_MR_VBPS(24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case SNDRV_PCM_FORMAT_S32_BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) mr |= SPDIFTX_MR_ENDIAN_BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case SNDRV_PCM_FORMAT_S32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) mr |= SPDIFTX_MR_VBPS(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dev_err(dev->dev, "unsupported PCM format: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) params_format(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) mr |= SPDIFTX_MR_BPS(bps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) spin_lock_irqsave(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ctrl->ch_stat[3] &= ~IEC958_AES3_CON_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) switch (params_rate(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) case 22050:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_22050;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case 24000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_24000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_88200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) case 176400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_176400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_192000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) case 11025:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case 64000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_NOTID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev_err(dev->dev, "unsupported sample frequency: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) params_rate(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) spin_unlock_irqrestore(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) mchp_spdiftx_channel_status_write(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) spin_unlock_irqrestore(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (dev->gclk_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) clk_disable_unprepare(dev->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dev->gclk_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ret = clk_set_rate(dev->gclk, params_rate(params) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) SPDIFTX_GCLK_RATIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dev_err(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) "unable to change gclk rate to: rate %u * ratio %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) params_rate(params), SPDIFTX_GCLK_RATIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ret = clk_prepare_enable(dev->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev_err(dev->dev, "unable to enable gclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev->gclk_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_dbg(dev->dev, "%s(): GCLK set to %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) params_rate(params) * SPDIFTX_GCLK_RATIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) regmap_write(dev->regmap, SPDIFTX_IER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) regmap_write(dev->regmap, SPDIFTX_MR, mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static int mchp_spdiftx_hw_free(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) regmap_write(dev->regmap, SPDIFTX_IDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (dev->gclk_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) clk_disable_unprepare(dev->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dev->gclk_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return regmap_write(dev->regmap, SPDIFTX_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static const struct snd_soc_dai_ops mchp_spdiftx_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .startup = mchp_spdiftx_dai_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .shutdown = mchp_spdiftx_dai_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .trigger = mchp_spdiftx_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .hw_params = mchp_spdiftx_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .hw_free = mchp_spdiftx_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define MCHP_SPDIFTX_RATES SNDRV_PCM_RATE_8000_192000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define MCHP_SPDIFTX_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) SNDRV_PCM_FMTBIT_S16_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) SNDRV_PCM_FMTBIT_U16_BE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) SNDRV_PCM_FMTBIT_S18_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) SNDRV_PCM_FMTBIT_S18_3BE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) SNDRV_PCM_FMTBIT_S20_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) SNDRV_PCM_FMTBIT_S20_3BE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) SNDRV_PCM_FMTBIT_S24_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) SNDRV_PCM_FMTBIT_S24_3BE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) SNDRV_PCM_FMTBIT_S24_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) SNDRV_PCM_FMTBIT_S24_BE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) SNDRV_PCM_FMTBIT_S32_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) SNDRV_PCM_FMTBIT_S32_BE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static int mchp_spdiftx_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static int mchp_spdiftx_cs_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct snd_ctl_elem_value *uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) spin_lock_irqsave(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) memcpy(uvalue->value.iec958.status, ctrl->ch_stat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) sizeof(ctrl->ch_stat));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) spin_unlock_irqrestore(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static int mchp_spdiftx_cs_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct snd_ctl_elem_value *uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int changed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) spin_lock_irqsave(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (ctrl->ch_stat[i] != uvalue->value.iec958.status[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) changed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ctrl->ch_stat[i] = uvalue->value.iec958.status[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (changed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* don't enable IP while we copy the channel status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (mchp_spdiftx_is_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * if SPDIF is running, wait for interrupt to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * channel status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) regmap_write(dev->regmap, SPDIFTX_IER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) SPDIFTX_IR_CSRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) mchp_spdiftx_channel_status_write(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) spin_unlock_irqrestore(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int mchp_spdiftx_cs_mask(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct snd_ctl_elem_value *uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) memset(uvalue->value.iec958.status, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) sizeof(uvalue->value.iec958.status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static int mchp_spdiftx_subcode_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct snd_ctl_elem_value *uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) spin_lock_irqsave(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) memcpy(uvalue->value.iec958.subcode, ctrl->user_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) sizeof(ctrl->user_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) spin_unlock_irqrestore(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int mchp_spdiftx_subcode_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct snd_ctl_elem_value *uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) int changed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) spin_lock_irqsave(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) for (i = 0; i < ARRAY_SIZE(ctrl->user_data); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (ctrl->user_data[i] != uvalue->value.iec958.subcode[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) changed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ctrl->user_data[i] = uvalue->value.iec958.subcode[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (changed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (mchp_spdiftx_is_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * if SPDIF is running, wait for interrupt to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * user data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) regmap_write(dev->regmap, SPDIFTX_IER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) SPDIFTX_IR_UDRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) mchp_spdiftx_user_data_write(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) spin_unlock_irqrestore(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static struct snd_kcontrol_new mchp_spdiftx_ctrls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Channel status controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .info = mchp_spdiftx_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .get = mchp_spdiftx_cs_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .put = mchp_spdiftx_cs_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .info = mchp_spdiftx_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .get = mchp_spdiftx_cs_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* User bits controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .name = "IEC958 Subcode Playback Default",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .info = mchp_spdiftx_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .get = mchp_spdiftx_subcode_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .put = mchp_spdiftx_subcode_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static int mchp_spdiftx_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) snd_soc_dai_init_dma_data(dai, &dev->playback, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ret = clk_prepare_enable(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) dev_err(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) "failed to enable the peripheral clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* Add controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) snd_soc_add_dai_controls(dai, mchp_spdiftx_ctrls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ARRAY_SIZE(mchp_spdiftx_ctrls));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static int mchp_spdiftx_dai_remove(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) clk_disable_unprepare(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static struct snd_soc_dai_driver mchp_spdiftx_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .name = "mchp-spdiftx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .probe = mchp_spdiftx_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .remove = mchp_spdiftx_dai_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .stream_name = "S/PDIF Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .rates = MCHP_SPDIFTX_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .formats = MCHP_SPDIFTX_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .ops = &mchp_spdiftx_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static const struct snd_soc_component_driver mchp_spdiftx_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .name = "mchp-spdiftx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static const struct of_device_id mchp_spdiftx_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .compatible = "microchip,sama7g5-spdiftx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) MODULE_DEVICE_TABLE(of, mchp_spdiftx_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static int mchp_spdiftx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct mchp_spdiftx_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct mchp_spdiftx_mixer_control *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* Get memory for driver data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* Get hardware capabilities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) match = of_match_node(mchp_spdiftx_dt_ids, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dev->caps = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* Map I/O registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) regmap = devm_regmap_init_mmio(&pdev->dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) &mchp_spdiftx_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* Request IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) err = devm_request_irq(&pdev->dev, irq, mchp_spdiftx_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_name(&pdev->dev), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* Get the peripheral clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) dev->pclk = devm_clk_get(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (IS_ERR(dev->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) err = PTR_ERR(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) "failed to get the peripheral clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* Get the generic clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dev->gclk = devm_clk_get(&pdev->dev, "gclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (IS_ERR(dev->gclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) err = PTR_ERR(dev->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) "failed to get the PMC generic clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) ctrl = &dev->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) spin_lock_init(&ctrl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* Init channel status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ctrl->ch_stat[0] = IEC958_AES0_CON_NOT_COPYRIGHT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) IEC958_AES0_CON_EMPHASIS_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dev->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dev->playback.addr = (dma_addr_t)mem->start + SPDIFTX_CDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dev->playback.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) dev_err(&pdev->dev, "failed to register PMC: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) err = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) &mchp_spdiftx_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) &mchp_spdiftx_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) dev_err(&pdev->dev, "failed to register component: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static struct platform_driver mchp_spdiftx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .probe = mchp_spdiftx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .name = "mchp_spdiftx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .of_match_table = of_match_ptr(mchp_spdiftx_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) module_platform_driver(mchp_spdiftx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) MODULE_DESCRIPTION("Microchip S/PDIF TX Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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