^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Driver for Microchip S/PDIF RX Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * ---- S/PDIF Receiver Controller Register map ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPDIFRX_CR 0x00 /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SPDIFRX_MR 0x04 /* Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPDIFRX_IER 0x10 /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPDIFRX_IDR 0x14 /* Interrupt Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPDIFRX_IMR 0x18 /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPDIFRX_ISR 0x1c /* Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPDIFRX_RSR 0x20 /* Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPDIFRX_RHR 0x24 /* Holding Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPDIFRX_CHSR(channel, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) (0x30 + (channel) * 0x30 + (reg) * 4) /* Channel x Status Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPDIFRX_CHUD(channel, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) (0x48 + (channel) * 0x30 + (reg) * 4) /* Channel x User Data Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPDIFRX_WPMR 0xE4 /* Write Protection Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPDIFRX_WPSR 0xE8 /* Write Protection Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPDIFRX_VERSION 0xFC /* Version Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * ---- Control Register (Write-only) ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPDIFRX_CR_SWRST BIT(0) /* Software Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * ---- Mode Register (Read/Write) ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Receive Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPDIFRX_MR_RXEN_MASK GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPDIFRX_MR_RXEN_DISABLE (0 << 0) /* SPDIF Receiver Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPDIFRX_MR_RXEN_ENABLE (1 << 0) /* SPDIF Receiver Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Validity Bit Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPDIFRX_MR_VBMODE_MASK GENAMSK(1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPDIFRX_MR_VBMODE_ALWAYS_LOAD \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) (0 << 1) /* Load sample regardles of validity bit value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPDIFRX_MR_VBMODE_DISCARD_IF_VB1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) (1 << 1) /* Load sample only if validity bit is 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Data Word Endian Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPDIFRX_MR_ENDIAN_MASK GENMASK(2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPDIFRX_MR_ENDIAN_LITTLE (0 << 2) /* Little Endian Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SPDIFRX_MR_ENDIAN_BIG (1 << 2) /* Big Endian Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Parity Bit Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SPDIFRX_MR_PBMODE_MASK GENMASK(3, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SPDIFRX_MR_PBMODE_PARCHECK (0 << 3) /* Parity Check Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SPDIFRX_MR_PBMODE_NOPARCHECK (1 << 3) /* Parity Check Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Sample Data Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SPDIFRX_MR_DATAWIDTH_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SPDIFRX_MR_DATAWIDTH(width) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) (((6 - (width) / 4) << 4) & SPDIFRX_MR_DATAWIDTH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Packed Data Mode in Receive Holding Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SPDIFRX_MR_PACK_MASK GENMASK(7, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SPDIFRX_MR_PACK_DISABLED (0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SPDIFRX_MR_PACK_ENABLED (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Start of Block Bit Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SPDIFRX_MR_SBMODE_MASK GENMASK(8, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SPDIFRX_MR_SBMODE_ALWAYS_LOAD (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SPDIFRX_MR_SBMODE_DISCARD (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Consecutive Preamble Error Threshold Automatic Restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SPDIFRX_MR_AUTORST_MASK GENMASK(24, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SPDIFRX_MR_AUTORST_NOACTION (0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SPDIFRX_MR_AUTORST_UNLOCK_ON_PRE_ERR (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * ---- Interrupt Enable/Disable/Mask/Status Register (Write/Read-only) ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SPDIFRX_IR_RXRDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SPDIFRX_IR_LOCKED BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SPDIFRX_IR_LOSS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SPDIFRX_IR_BLOCKEND BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SPDIFRX_IR_SFE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SPDIFRX_IR_PAR_ERR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SPDIFRX_IR_OVERRUN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SPDIFRX_IR_RXFULL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SPDIFRX_IR_CSC(ch) BIT((ch) + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SPDIFRX_IR_SECE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SPDIFRX_IR_BLOCKST BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SPDIFRX_IR_NRZ_ERR BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SPDIFRX_IR_PRE_ERR BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SPDIFRX_IR_CP_ERR BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * ---- Receiver Status Register (Read/Write) ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Enable Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SPDIFRX_RSR_ULOCK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SPDIFRX_RSR_BADF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SPDIFRX_RSR_LOWF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SPDIFRX_RSR_NOSIGNAL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SPDIFRX_RSR_IFS_MASK GENMASK(27, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SPDIFRX_RSR_IFS(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) (((reg) & SPDIFRX_RSR_IFS_MASK) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * ---- Version Register (Read-only) ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SPDIFRX_VERSION_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SPDIFRX_VERSION_MFN_MASK GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SPDIFRX_VERSION_MFN(reg) (((reg) & SPDIFRX_VERSION_MFN_MASK) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static bool mchp_spdifrx_readable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case SPDIFRX_MR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case SPDIFRX_IMR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case SPDIFRX_ISR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) case SPDIFRX_RSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case SPDIFRX_CHSR(0, 0):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case SPDIFRX_CHSR(0, 1):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case SPDIFRX_CHSR(0, 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case SPDIFRX_CHSR(0, 3):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case SPDIFRX_CHSR(0, 4):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case SPDIFRX_CHSR(0, 5):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case SPDIFRX_CHUD(0, 0):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case SPDIFRX_CHUD(0, 1):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case SPDIFRX_CHUD(0, 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case SPDIFRX_CHUD(0, 3):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case SPDIFRX_CHUD(0, 4):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case SPDIFRX_CHUD(0, 5):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case SPDIFRX_CHSR(1, 0):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) case SPDIFRX_CHSR(1, 1):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case SPDIFRX_CHSR(1, 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case SPDIFRX_CHSR(1, 3):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case SPDIFRX_CHSR(1, 4):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) case SPDIFRX_CHSR(1, 5):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case SPDIFRX_CHUD(1, 0):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) case SPDIFRX_CHUD(1, 1):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) case SPDIFRX_CHUD(1, 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) case SPDIFRX_CHUD(1, 3):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) case SPDIFRX_CHUD(1, 4):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case SPDIFRX_CHUD(1, 5):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case SPDIFRX_WPMR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case SPDIFRX_WPSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) case SPDIFRX_VERSION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static bool mchp_spdifrx_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) case SPDIFRX_CR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) case SPDIFRX_MR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case SPDIFRX_IER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) case SPDIFRX_IDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case SPDIFRX_WPMR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static bool mchp_spdifrx_precious_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case SPDIFRX_ISR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case SPDIFRX_RHR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const struct regmap_config mchp_spdifrx_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .max_register = SPDIFRX_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .readable_reg = mchp_spdifrx_readable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .writeable_reg = mchp_spdifrx_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .precious_reg = mchp_spdifrx_precious_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SPDIFRX_GCLK_RATIO_MIN (12 * 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SPDIFRX_CS_BITS 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SPDIFRX_UD_BITS 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SPDIFRX_CHANNELS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct mchp_spdifrx_ch_stat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned char data[SPDIFRX_CS_BITS / 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct mchp_spdifrx_user_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned char data[SPDIFRX_UD_BITS / 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) spinlock_t lock; /* protect access to user data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct mchp_spdifrx_mixer_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct mchp_spdifrx_ch_stat ch_stat[SPDIFRX_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct mchp_spdifrx_user_data user_data[SPDIFRX_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) bool ulock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) bool badf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) bool signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct mchp_spdifrx_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct snd_dmaengine_dai_dma_data capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct mchp_spdifrx_mixer_control control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) spinlock_t blockend_lock; /* protect access to blockend_refcount */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int blockend_refcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct clk *gclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned int fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned int gclk_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void mchp_spdifrx_channel_status_read(struct mchp_spdifrx_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u8 *ch_stat = &ctrl->ch_stat[channel].data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat[channel].data) / 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) regmap_read(dev->regmap, SPDIFRX_CHSR(channel, i), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) *ch_stat++ = val & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *ch_stat++ = (val >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) *ch_stat++ = (val >> 16) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *ch_stat++ = (val >> 24) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void mchp_spdifrx_channel_user_data_read(struct mchp_spdifrx_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u8 *user_data = &ctrl->user_data[channel].data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) for (i = 0; i < ARRAY_SIZE(ctrl->user_data[channel].data) / 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) regmap_read(dev->regmap, SPDIFRX_CHUD(channel, i), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *user_data++ = val & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) *user_data++ = (val >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *user_data++ = (val >> 16) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) *user_data++ = (val >> 24) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* called from non-atomic context only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static void mchp_spdifrx_isr_blockend_en(struct mchp_spdifrx_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) spin_lock_irqsave(&dev->blockend_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dev->blockend_refcount++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* don't enable BLOCKEND interrupt if it's already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (dev->blockend_refcount == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_BLOCKEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) spin_unlock_irqrestore(&dev->blockend_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* called from atomic context only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static void mchp_spdifrx_isr_blockend_dis(struct mchp_spdifrx_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) spin_lock(&dev->blockend_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev->blockend_refcount--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* don't enable BLOCKEND interrupt if it's already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (dev->blockend_refcount == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_BLOCKEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) spin_unlock(&dev->blockend_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static irqreturn_t mchp_spdif_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct mchp_spdifrx_dev *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 sr, imr, pending, idr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) regmap_read(dev->regmap, SPDIFRX_ISR, &sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) regmap_read(dev->regmap, SPDIFRX_IMR, &imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) pending = sr & imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev_dbg(dev->dev, "ISR: %#x, IMR: %#x, pending: %#x\n", sr, imr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (!pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (pending & SPDIFRX_IR_BLOCKEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) spin_lock(&ctrl->user_data[ch].lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) mchp_spdifrx_channel_user_data_read(dev, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) spin_unlock(&ctrl->user_data[ch].lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) complete(&ctrl->user_data[ch].done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) mchp_spdifrx_isr_blockend_dis(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (pending & SPDIFRX_IR_CSC(ch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) mchp_spdifrx_channel_status_read(dev, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) complete(&ctrl->ch_stat[ch].done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) idr |= SPDIFRX_IR_CSC(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (pending & SPDIFRX_IR_OVERRUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev_warn(dev->dev, "Overrun detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) regmap_write(dev->regmap, SPDIFRX_IDR, idr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int mchp_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) regmap_read(dev->regmap, SPDIFRX_MR, &mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) running = !!(mr & SPDIFRX_MR_RXEN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (!running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mr &= ~SPDIFRX_MR_RXEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) mr |= SPDIFRX_MR_RXEN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* enable overrun interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) regmap_write(dev->regmap, SPDIFRX_IER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) SPDIFRX_IR_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) mr &= ~SPDIFRX_MR_RXEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) mr |= SPDIFRX_MR_RXEN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* disable overrun interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) regmap_write(dev->regmap, SPDIFRX_IDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) SPDIFRX_IR_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = regmap_write(dev->regmap, SPDIFRX_MR, mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_err(dev->dev, "unable to enable/disable RX: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int mchp_spdifrx_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u32 mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) __func__, params_rate(params), params_format(params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) params_width(params), params_channels(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dev_err(dev->dev, "Playback is not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) regmap_read(dev->regmap, SPDIFRX_MR, &mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (mr & SPDIFRX_MR_RXEN_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dev_err(dev->dev, "PCM already running\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (params_channels(params) != SPDIFRX_CHANNELS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_err(dev->dev, "unsupported number of channels: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) params_channels(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) case SNDRV_PCM_FORMAT_S16_BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case SNDRV_PCM_FORMAT_S20_3BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case SNDRV_PCM_FORMAT_S24_3BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case SNDRV_PCM_FORMAT_S24_BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) mr |= SPDIFRX_MR_ENDIAN_BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case SNDRV_PCM_FORMAT_S20_3LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) case SNDRV_PCM_FORMAT_S24_3LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) case SNDRV_PCM_FORMAT_S24_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) mr |= SPDIFRX_MR_DATAWIDTH(params_width(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dev_err(dev->dev, "unsupported PCM format: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) params_format(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (dev->gclk_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) clk_disable_unprepare(dev->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dev->gclk_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = clk_set_min_rate(dev->gclk, params_rate(params) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) SPDIFRX_GCLK_RATIO_MIN + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dev_err(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) "unable to set gclk min rate: rate %u * ratio %u + 1\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) params_rate(params), SPDIFRX_GCLK_RATIO_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ret = clk_prepare_enable(dev->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dev_err(dev->dev, "unable to enable gclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev->gclk_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev_dbg(dev->dev, "GCLK range min set to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) params_rate(params) * SPDIFRX_GCLK_RATIO_MIN + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return regmap_write(dev->regmap, SPDIFRX_MR, mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static int mchp_spdifrx_hw_free(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (dev->gclk_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) clk_disable_unprepare(dev->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev->gclk_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static const struct snd_soc_dai_ops mchp_spdifrx_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .trigger = mchp_spdifrx_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .hw_params = mchp_spdifrx_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .hw_free = mchp_spdifrx_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define MCHP_SPDIF_RATES SNDRV_PCM_RATE_8000_192000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define MCHP_SPDIF_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) SNDRV_PCM_FMTBIT_U16_BE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) SNDRV_PCM_FMTBIT_S20_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) SNDRV_PCM_FMTBIT_S20_3BE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) SNDRV_PCM_FMTBIT_S24_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) SNDRV_PCM_FMTBIT_S24_3BE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) SNDRV_PCM_FMTBIT_S24_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) SNDRV_PCM_FMTBIT_S24_BE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int mchp_spdifrx_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int mchp_spdifrx_cs_get(struct mchp_spdifrx_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct snd_ctl_elem_value *uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct mchp_spdifrx_ch_stat *ch_stat = &ctrl->ch_stat[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_CSC(channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* check for new data available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ret = wait_for_completion_interruptible_timeout(&ch_stat->done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) msecs_to_jiffies(100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* IP might not be started or valid stream might not be prezent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dev_dbg(dev->dev, "channel status for channel %d timeout\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) memcpy(uvalue->value.iec958.status, ch_stat->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) sizeof(ch_stat->data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int mchp_spdifrx_cs1_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct snd_ctl_elem_value *uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return mchp_spdifrx_cs_get(dev, 0, uvalue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int mchp_spdifrx_cs2_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct snd_ctl_elem_value *uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return mchp_spdifrx_cs_get(dev, 1, uvalue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static int mchp_spdifrx_cs_mask(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct snd_ctl_elem_value *uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) memset(uvalue->value.iec958.status, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) sizeof(uvalue->value.iec958.status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static int mchp_spdifrx_subcode_ch_get(struct mchp_spdifrx_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct snd_ctl_elem_value *uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct mchp_spdifrx_user_data *user_data = &ctrl->user_data[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) reinit_completion(&user_data->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) mchp_spdifrx_isr_blockend_en(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ret = wait_for_completion_interruptible_timeout(&user_data->done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) msecs_to_jiffies(100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* IP might not be started or valid stream might not be prezent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (ret <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dev_dbg(dev->dev, "user data for channel %d timeout\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) spin_lock_irqsave(&user_data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) memcpy(uvalue->value.iec958.subcode, user_data->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) sizeof(user_data->data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) spin_unlock_irqrestore(&user_data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int mchp_spdifrx_subcode_ch1_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct snd_ctl_elem_value *uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return mchp_spdifrx_subcode_ch_get(dev, 0, uvalue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int mchp_spdifrx_subcode_ch2_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct snd_ctl_elem_value *uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return mchp_spdifrx_subcode_ch_get(dev, 1, uvalue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int mchp_spdifrx_boolean_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) uinfo->value.integer.max = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int mchp_spdifrx_ulock_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct snd_ctl_elem_value *uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) bool ulock_old = ctrl->ulock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) regmap_read(dev->regmap, SPDIFRX_RSR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ctrl->ulock = !(val & SPDIFRX_RSR_ULOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) uvalue->value.integer.value[0] = ctrl->ulock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return ulock_old != ctrl->ulock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static int mchp_spdifrx_badf_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct snd_ctl_elem_value *uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) bool badf_old = ctrl->badf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) regmap_read(dev->regmap, SPDIFRX_RSR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ctrl->badf = !!(val & SPDIFRX_RSR_BADF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) uvalue->value.integer.value[0] = ctrl->badf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return badf_old != ctrl->badf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int mchp_spdifrx_signal_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct snd_ctl_elem_value *uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) bool signal_old = ctrl->signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) regmap_read(dev->regmap, SPDIFRX_RSR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ctrl->signal = !(val & SPDIFRX_RSR_NOSIGNAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) uvalue->value.integer.value[0] = ctrl->signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return signal_old != ctrl->signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static int mchp_spdifrx_rate_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) uinfo->value.integer.max = 192000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static int mchp_spdifrx_rate_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) regmap_read(dev->regmap, SPDIFRX_RSR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* if the receiver is not locked, ISF data is invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (val & SPDIFRX_RSR_ULOCK || !(val & SPDIFRX_RSR_IFS_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ucontrol->value.integer.value[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) rate = clk_get_rate(dev->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ucontrol->value.integer.value[0] = rate / (32 * SPDIFRX_RSR_IFS(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static struct snd_kcontrol_new mchp_spdifrx_ctrls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* Channel status controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) " Channel 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .info = mchp_spdifrx_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .get = mchp_spdifrx_cs1_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) " Channel 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .info = mchp_spdifrx_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .get = mchp_spdifrx_cs2_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .info = mchp_spdifrx_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .get = mchp_spdifrx_cs_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* User bits controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .name = "IEC958 Subcode Capture Default Channel 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .info = mchp_spdifrx_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .get = mchp_spdifrx_subcode_ch1_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .name = "IEC958 Subcode Capture Default Channel 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .info = mchp_spdifrx_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .get = mchp_spdifrx_subcode_ch2_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* Lock status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Unlocked",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .info = mchp_spdifrx_boolean_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .get = mchp_spdifrx_ulock_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* Bad format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE)"Bad Format",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .info = mchp_spdifrx_boolean_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .get = mchp_spdifrx_badf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* Signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Signal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .info = mchp_spdifrx_boolean_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .get = mchp_spdifrx_signal_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* Sampling rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Rate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .info = mchp_spdifrx_rate_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .get = mchp_spdifrx_rate_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static int mchp_spdifrx_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) err = clk_prepare_enable(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dev_err(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) "failed to enable the peripheral clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) snd_soc_dai_init_dma_data(dai, NULL, &dev->capture);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* Software reset the IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) regmap_write(dev->regmap, SPDIFRX_CR, SPDIFRX_CR_SWRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* Default configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) regmap_write(dev->regmap, SPDIFRX_MR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) SPDIFRX_MR_VBMODE_DISCARD_IF_VB1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) SPDIFRX_MR_SBMODE_DISCARD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) SPDIFRX_MR_AUTORST_NOACTION |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) SPDIFRX_MR_PACK_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev->blockend_refcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) init_completion(&ctrl->ch_stat[ch].done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) init_completion(&ctrl->user_data[ch].done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) spin_lock_init(&ctrl->user_data[ch].lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* Add controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) snd_soc_add_dai_controls(dai, mchp_spdifrx_ctrls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ARRAY_SIZE(mchp_spdifrx_ctrls));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static int mchp_spdifrx_dai_remove(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) regmap_write(dev->regmap, SPDIFRX_IDR, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) clk_disable_unprepare(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static struct snd_soc_dai_driver mchp_spdifrx_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .name = "mchp-spdifrx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .probe = mchp_spdifrx_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .remove = mchp_spdifrx_dai_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .stream_name = "S/PDIF Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .channels_min = SPDIFRX_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .channels_max = SPDIFRX_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .rates = MCHP_SPDIF_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .formats = MCHP_SPDIF_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .ops = &mchp_spdifrx_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static const struct snd_soc_component_driver mchp_spdifrx_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .name = "mchp-spdifrx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static const struct of_device_id mchp_spdifrx_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .compatible = "microchip,sama7g5-spdifrx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) MODULE_DEVICE_TABLE(of, mchp_spdifrx_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static int mchp_spdifrx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct mchp_spdifrx_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u32 vers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* Get memory for driver data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /* Map I/O registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) regmap = devm_regmap_init_mmio(&pdev->dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) &mchp_spdifrx_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* Request IRQ. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) err = devm_request_irq(&pdev->dev, irq, mchp_spdif_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dev_name(&pdev->dev), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* Get the peripheral clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) dev->pclk = devm_clk_get(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (IS_ERR(dev->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) err = PTR_ERR(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dev_err(&pdev->dev, "failed to get the peripheral clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* Get the generated clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) dev->gclk = devm_clk_get(&pdev->dev, "gclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (IS_ERR(dev->gclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) err = PTR_ERR(dev->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) "failed to get the PMC generated clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) spin_lock_init(&dev->blockend_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dev->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) dev->capture.addr = (dma_addr_t)mem->start + SPDIFRX_RHR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) dev->capture.maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) dev_err(&pdev->dev, "failed to register PMC: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) err = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) &mchp_spdifrx_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) &mchp_spdifrx_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) dev_err(&pdev->dev, "fail to register dai\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) regmap_read(regmap, SPDIFRX_VERSION, &vers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) dev_info(&pdev->dev, "hw version: %#lx\n", vers & SPDIFRX_VERSION_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static struct platform_driver mchp_spdifrx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .probe = mchp_spdifrx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .name = "mchp_spdifrx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .of_match_table = of_match_ptr(mchp_spdifrx_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) module_platform_driver(mchp_spdifrx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) MODULE_DESCRIPTION("Microchip S/PDIF RX Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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