^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Driver for Microchip I2S Multi-channel controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/lcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * ---- I2S Controller Register map ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MCHP_I2SMCC_CR 0x0000 /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MCHP_I2SMCC_MRA 0x0004 /* Mode Register A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MCHP_I2SMCC_MRB 0x0008 /* Mode Register B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MCHP_I2SMCC_SR 0x000C /* Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MCHP_I2SMCC_IERA 0x0010 /* Interrupt Enable Register A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MCHP_I2SMCC_IDRA 0x0014 /* Interrupt Disable Register A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MCHP_I2SMCC_IMRA 0x0018 /* Interrupt Mask Register A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MCHP_I2SMCC_ISRA 0X001C /* Interrupt Status Register A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MCHP_I2SMCC_IERB 0x0020 /* Interrupt Enable Register B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MCHP_I2SMCC_IDRB 0x0024 /* Interrupt Disable Register B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MCHP_I2SMCC_IMRB 0x0028 /* Interrupt Mask Register B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MCHP_I2SMCC_ISRB 0X002C /* Interrupt Status Register B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MCHP_I2SMCC_RHR 0x0030 /* Receiver Holding Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MCHP_I2SMCC_THR 0x0034 /* Transmitter Holding Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MCHP_I2SMCC_RHL0R 0x0040 /* Receiver Holding Left 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MCHP_I2SMCC_RHR0R 0x0044 /* Receiver Holding Right 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MCHP_I2SMCC_RHL1R 0x0048 /* Receiver Holding Left 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MCHP_I2SMCC_RHR1R 0x004C /* Receiver Holding Right 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MCHP_I2SMCC_RHL2R 0x0050 /* Receiver Holding Left 2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MCHP_I2SMCC_RHR2R 0x0054 /* Receiver Holding Right 2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MCHP_I2SMCC_RHL3R 0x0058 /* Receiver Holding Left 3 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MCHP_I2SMCC_RHR3R 0x005C /* Receiver Holding Right 3 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MCHP_I2SMCC_THL0R 0x0060 /* Transmitter Holding Left 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MCHP_I2SMCC_THR0R 0x0064 /* Transmitter Holding Right 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MCHP_I2SMCC_THL1R 0x0068 /* Transmitter Holding Left 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MCHP_I2SMCC_THR1R 0x006C /* Transmitter Holding Right 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MCHP_I2SMCC_THL2R 0x0070 /* Transmitter Holding Left 2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MCHP_I2SMCC_THR2R 0x0074 /* Transmitter Holding Right 2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MCHP_I2SMCC_THL3R 0x0078 /* Transmitter Holding Left 3 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MCHP_I2SMCC_THR3R 0x007C /* Transmitter Holding Right 3 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MCHP_I2SMCC_VERSION 0x00FC /* Version Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * ---- Control Register (Write-only) ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MCHP_I2SMCC_CR_RXEN BIT(0) /* Receiver Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MCHP_I2SMCC_CR_RXDIS BIT(1) /* Receiver Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MCHP_I2SMCC_CR_CKEN BIT(2) /* Clock Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MCHP_I2SMCC_CR_CKDIS BIT(3) /* Clock Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MCHP_I2SMCC_CR_TXEN BIT(4) /* Transmitter Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MCHP_I2SMCC_CR_TXDIS BIT(5) /* Transmitter Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MCHP_I2SMCC_CR_SWRST BIT(7) /* Software Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * ---- Mode Register A (Read/Write) ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MCHP_I2SMCC_MRA_MODE_MASK GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MCHP_I2SMCC_MRA_MODE_SLAVE (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MCHP_I2SMCC_MRA_MODE_MASTER (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MCHP_I2SMCC_MRA_DATALENGTH_MASK GENMASK(3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MCHP_I2SMCC_MRA_DATALENGTH_32_BITS (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MCHP_I2SMCC_MRA_DATALENGTH_24_BITS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MCHP_I2SMCC_MRA_DATALENGTH_20_BITS (2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MCHP_I2SMCC_MRA_DATALENGTH_18_BITS (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MCHP_I2SMCC_MRA_DATALENGTH_16_BITS (4 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MCHP_I2SMCC_MRA_DATALENGTH_16_BITS_COMPACT (5 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MCHP_I2SMCC_MRA_DATALENGTH_8_BITS (6 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MCHP_I2SMCC_MRA_DATALENGTH_8_BITS_COMPACT (7 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MCHP_I2SMCC_MRA_WIRECFG_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MCHP_I2SMCC_MRA_WIRECFG_I2S_1_TDM_0 (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MCHP_I2SMCC_MRA_WIRECFG_I2S_2_TDM_1 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MCHP_I2SMCC_MRA_WIRECFG_I2S_4_TDM_2 (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MCHP_I2SMCC_MRA_WIRECFG_TDM_3 (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MCHP_I2SMCC_MRA_FORMAT_MASK GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MCHP_I2SMCC_MRA_FORMAT_I2S (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MCHP_I2SMCC_MRA_FORMAT_LJ (1 << 6) /* Left Justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MCHP_I2SMCC_MRA_FORMAT_TDM (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MCHP_I2SMCC_MRA_FORMAT_TDMLJ (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Transmitter uses one DMA channel ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Left audio samples duplicated to right audio channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MCHP_I2SMCC_MRA_RXMONO BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* I2SDO output of I2SC is internally connected to I2SDI input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MCHP_I2SMCC_MRA_RXLOOP BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Receiver uses one DMA channel ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Left audio samples duplicated to right audio channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MCHP_I2SMCC_MRA_TXMONO BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* x sample transmitted when underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MCHP_I2SMCC_MRA_TXSAME_ZERO (0 << 11) /* Zero sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MCHP_I2SMCC_MRA_TXSAME_PREVIOUS (1 << 11) /* Previous sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* select between peripheral clock and generated clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MCHP_I2SMCC_MRA_SRCCLK_PCLK (0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MCHP_I2SMCC_MRA_SRCCLK_GCLK (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Number of TDM Channels - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MCHP_I2SMCC_MRA_NBCHAN_MASK GENMASK(15, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MCHP_I2SMCC_MRA_NBCHAN(ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ((((ch) - 1) << 13) & MCHP_I2SMCC_MRA_NBCHAN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Selected Clock to I2SMCC Master Clock ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MCHP_I2SMCC_MRA_IMCKDIV_MASK GENMASK(21, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MCHP_I2SMCC_MRA_IMCKDIV(div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) (((div) << 16) & MCHP_I2SMCC_MRA_IMCKDIV_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* TDM Frame Synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MCHP_I2SMCC_MRA_TDMFS_MASK GENMASK(23, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MCHP_I2SMCC_MRA_TDMFS_SLOT (0 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MCHP_I2SMCC_MRA_TDMFS_HALF (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MCHP_I2SMCC_MRA_TDMFS_BIT (2 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Selected Clock to I2SMC Serial Clock ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MCHP_I2SMCC_MRA_ISCKDIV_MASK GENMASK(29, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MCHP_I2SMCC_MRA_ISCKDIV(div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) (((div) << 24) & MCHP_I2SMCC_MRA_ISCKDIV_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Master Clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MCHP_I2SMCC_MRA_IMCKMODE_MASK GENMASK(30, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* 0: No master clock generated*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MCHP_I2SMCC_MRA_IMCKMODE_NONE (0 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* 1: master clock generated (internally generated clock drives I2SMCK pin) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MCHP_I2SMCC_MRA_IMCKMODE_GEN (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Slot Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* 0: slot is 32 bits wide for DATALENGTH = 18/20/24 bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* 1: slot is 24 bits wide for DATALENGTH = 18/20/24 bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MCHP_I2SMCC_MRA_IWS BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * ---- Mode Register B (Read/Write) ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* all enabled I2S left channels are filled first, then I2S right channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MCHP_I2SMCC_MRB_CRAMODE_LEFT_FIRST (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * an enabled I2S left channel is filled, then the corresponding right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * channel, until all channels are filled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MCHP_I2SMCC_MRB_CRAMODE_REGULAR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MCHP_I2SMCC_MRB_FIFOEN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MCHP_I2SMCC_MRB_DMACHUNK_MASK GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MCHP_I2SMCC_MRB_DMACHUNK(no_words) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) (((fls(no_words) - 1) << 8) & MCHP_I2SMCC_MRB_DMACHUNK_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MCHP_I2SMCC_MRB_CLKSEL_MASK GENMASK(16, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MCHP_I2SMCC_MRB_CLKSEL_EXT (0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MCHP_I2SMCC_MRB_CLKSEL_INT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * ---- Status Registers (Read-only) ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MCHP_I2SMCC_SR_RXEN BIT(0) /* Receiver Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MCHP_I2SMCC_SR_TXEN BIT(4) /* Transmitter Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * ---- Interrupt Enable/Disable/Mask/Status Registers A ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MCHP_I2SMCC_INT_TXRDY_MASK(ch) GENMASK((ch) - 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MCHP_I2SMCC_INT_TXRDYCH(ch) BIT(ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define MCHP_I2SMCC_INT_TXUNF_MASK(ch) GENMASK((ch) + 7, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MCHP_I2SMCC_INT_TXUNFCH(ch) BIT((ch) + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MCHP_I2SMCC_INT_RXRDY_MASK(ch) GENMASK((ch) + 15, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MCHP_I2SMCC_INT_RXRDYCH(ch) BIT((ch) + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MCHP_I2SMCC_INT_RXOVF_MASK(ch) GENMASK((ch) + 23, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MCHP_I2SMCC_INT_RXOVFCH(ch) BIT((ch) + 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * ---- Interrupt Enable/Disable/Mask/Status Registers B ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MCHP_I2SMCC_INT_WERR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MCHP_I2SMCC_INT_TXFFRDY BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MCHP_I2SMCC_INT_TXFFEMP BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MCHP_I2SMCC_INT_RXFFRDY BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MCHP_I2SMCC_INT_RXFFFUL BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * ---- Version Register (Read-only) ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MCHP_I2SMCC_VERSION_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MCHP_I2SMCC_MAX_CHANNELS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MCHP_I2MCC_TDM_SLOT_WIDTH 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const struct regmap_config mchp_i2s_mcc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .max_register = MCHP_I2SMCC_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct mchp_i2s_mcc_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct wait_queue_head wq_txrdy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct wait_queue_head wq_rxrdy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct clk *gclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct snd_dmaengine_dai_dma_data playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct snd_dmaengine_dai_dma_data capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned int fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned int sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned int frame_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int tdm_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned int gclk_use:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned int gclk_running:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned int tx_rdy:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned int rx_rdy:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static irqreturn_t mchp_i2s_mcc_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct mchp_i2s_mcc_dev *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 sra, imra, srb, imrb, pendinga, pendingb, idra = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) regmap_read(dev->regmap, MCHP_I2SMCC_IMRA, &imra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) regmap_read(dev->regmap, MCHP_I2SMCC_ISRA, &sra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pendinga = imra & sra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) regmap_read(dev->regmap, MCHP_I2SMCC_IMRB, &imrb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) regmap_read(dev->regmap, MCHP_I2SMCC_ISRB, &srb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pendingb = imrb & srb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (!pendinga && !pendingb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * Tx/Rx ready interrupts are enabled when stopping only, to assure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * availability and to disable clocks if necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) idra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (idra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if ((imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) (idra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev->tx_rdy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) wake_up_interruptible(&dev->wq_txrdy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if ((imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) (idra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev->rx_rdy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) wake_up_interruptible(&dev->wq_rxrdy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int mchp_i2s_mcc_set_sysclk(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int clk_id, unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_dbg(dev->dev, "%s() clk_id=%d freq=%u dir=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) __func__, clk_id, freq, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* We do not need SYSCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (dir == SND_SOC_CLOCK_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev->sysclk = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int mchp_i2s_mcc_set_bclk_ratio(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned int ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev_dbg(dev->dev, "%s() ratio=%u\n", __func__, ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev->frame_length = ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int mchp_i2s_mcc_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_dbg(dev->dev, "%s() fmt=%#x\n", __func__, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* We don't support any kind of clock inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* We can't generate only FSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* We can only reconfigure the IP when it's stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (fmt & SND_SOC_DAIFMT_CONT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev->fmt = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int mchp_i2s_mcc_set_dai_tdm_slot(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned int tx_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned int rx_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int slots, int slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_dbg(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "%s() tx_mask=0x%08x rx_mask=0x%08x slots=%d width=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) __func__, tx_mask, rx_mask, slots, slot_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (slots < 0 || slots > MCHP_I2SMCC_MAX_CHANNELS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) slot_width != MCHP_I2MCC_TDM_SLOT_WIDTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (slots) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* We do not support daisy chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (rx_mask != GENMASK(slots - 1, 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) rx_mask != tx_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dev->tdm_slots = slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dev->frame_length = slots * MCHP_I2MCC_TDM_SLOT_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int mchp_i2s_mcc_clk_get_rate_diff(struct clk *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct clk **best_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned long *best_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned long *best_diff_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) long round_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned int diff_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) round_rate = clk_round_rate(clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (round_rate < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return (int)round_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) diff_rate = abs(rate - round_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (diff_rate < *best_diff_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) *best_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) *best_diff_rate = diff_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) *best_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static int mchp_i2s_mcc_config_divs(struct mchp_i2s_mcc_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned int bclk, unsigned int *mra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned long *best_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned long lcm_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) unsigned long best_diff_rate = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned int sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct clk *best_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* For code simplification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (!dev->sysclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) sysclk = bclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) sysclk = dev->sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * MCLK is Selected CLK / (2 * IMCKDIV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * BCLK is Selected CLK / (2 * ISCKDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * if IMCKDIV or ISCKDIV are 0, MCLK or BCLK = Selected CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) lcm_rate = lcm(sysclk, bclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if ((lcm_rate / sysclk % 2 == 1 && lcm_rate / sysclk > 2) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) (lcm_rate / bclk % 2 == 1 && lcm_rate / bclk > 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) lcm_rate *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) for (clk_rate = lcm_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) (clk_rate == sysclk || clk_rate / (sysclk * 2) <= GENMASK(5, 0)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) (clk_rate == bclk || clk_rate / (bclk * 2) <= GENMASK(5, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) clk_rate += lcm_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = mchp_i2s_mcc_clk_get_rate_diff(dev->gclk, clk_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) &best_clk, best_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) &best_diff_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev_err(dev->dev, "gclk error for rate %lu: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) clk_rate, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (!best_diff_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dev_dbg(dev->dev, "found perfect rate on gclk: %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ret = mchp_i2s_mcc_clk_get_rate_diff(dev->pclk, clk_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) &best_clk, best_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) &best_diff_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dev_err(dev->dev, "pclk error for rate %lu: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) clk_rate, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (!best_diff_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dev_dbg(dev->dev, "found perfect rate on pclk: %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* check if clocks returned only errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (!best_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dev_err(dev->dev, "unable to change rate to clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dev_dbg(dev->dev, "source CLK is %s with rate %lu, diff %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) best_clk == dev->pclk ? "pclk" : "gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) *best_rate, best_diff_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Configure divisors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (dev->sysclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) *mra |= MCHP_I2SMCC_MRA_IMCKDIV(*best_rate / (2 * sysclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) *mra |= MCHP_I2SMCC_MRA_ISCKDIV(*best_rate / (2 * bclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (best_clk == dev->gclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) *mra |= MCHP_I2SMCC_MRA_SRCCLK_GCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) *mra |= MCHP_I2SMCC_MRA_SRCCLK_PCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int mchp_i2s_mcc_is_running(struct mchp_i2s_mcc_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u32 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) regmap_read(dev->regmap, MCHP_I2SMCC_SR, &sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return !!(sr & (MCHP_I2SMCC_SR_TXEN | MCHP_I2SMCC_SR_RXEN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int mchp_i2s_mcc_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) unsigned long rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 mra = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u32 mrb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) unsigned int channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) unsigned int frame_length = dev->frame_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) unsigned int bclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int set_divs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) __func__, params_rate(params), params_format(params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) params_width(params), params_channels(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (dev->tdm_slots) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_err(dev->dev, "I2S with TDM is not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) mra |= MCHP_I2SMCC_MRA_FORMAT_I2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (dev->tdm_slots) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dev_err(dev->dev, "Left-Justified with TDM is not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) mra |= MCHP_I2SMCC_MRA_FORMAT_LJ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) mra |= MCHP_I2SMCC_MRA_FORMAT_TDM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_err(dev->dev, "unsupported bus format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* cpu is BCLK and LRC master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) mra |= MCHP_I2SMCC_MRA_MODE_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (dev->sysclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) mra |= MCHP_I2SMCC_MRA_IMCKMODE_GEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) set_divs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case SND_SOC_DAIFMT_CBS_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* cpu is BCLK master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) mrb |= MCHP_I2SMCC_MRB_CLKSEL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) set_divs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* cpu is slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mra |= MCHP_I2SMCC_MRA_MODE_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (dev->sysclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dev_warn(dev->dev, "Unable to generate MCLK in Slave mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dev_err(dev->dev, "unsupported master/slave mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (dev->fmt & (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) switch (channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (is_playback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) mra |= MCHP_I2SMCC_MRA_TXMONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mra |= MCHP_I2SMCC_MRA_RXMONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dev_err(dev->dev, "unsupported number of audio channels\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (!frame_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) frame_length = 2 * params_physical_width(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) } else if (dev->fmt & SND_SOC_DAIFMT_DSP_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (dev->tdm_slots) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (channels % 2 && channels * 2 <= dev->tdm_slots) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * Duplicate data for even-numbered channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * to odd-numbered channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (is_playback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) mra |= MCHP_I2SMCC_MRA_TXMONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) mra |= MCHP_I2SMCC_MRA_RXMONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) channels = dev->tdm_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) mra |= MCHP_I2SMCC_MRA_NBCHAN(channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (!frame_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) frame_length = channels * MCHP_I2MCC_TDM_SLOT_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * We must have the same burst size configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * in the DMA transfer and in out IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) mrb |= MCHP_I2SMCC_MRB_DMACHUNK(channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (is_playback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dev->playback.maxburst = 1 << (fls(channels) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dev->capture.maxburst = 1 << (fls(channels) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case SNDRV_PCM_FORMAT_S8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) mra |= MCHP_I2SMCC_MRA_DATALENGTH_8_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) mra |= MCHP_I2SMCC_MRA_DATALENGTH_16_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) case SNDRV_PCM_FORMAT_S18_3LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) mra |= MCHP_I2SMCC_MRA_DATALENGTH_18_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) MCHP_I2SMCC_MRA_IWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) case SNDRV_PCM_FORMAT_S20_3LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) mra |= MCHP_I2SMCC_MRA_DATALENGTH_20_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) MCHP_I2SMCC_MRA_IWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) case SNDRV_PCM_FORMAT_S24_3LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) mra |= MCHP_I2SMCC_MRA_DATALENGTH_24_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) MCHP_I2SMCC_MRA_IWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) case SNDRV_PCM_FORMAT_S24_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) mra |= MCHP_I2SMCC_MRA_DATALENGTH_24_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) case SNDRV_PCM_FORMAT_S32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) mra |= MCHP_I2SMCC_MRA_DATALENGTH_32_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) dev_err(dev->dev, "unsupported size/endianness for audio samples\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (set_divs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) bclk_rate = frame_length * params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ret = mchp_i2s_mcc_config_divs(dev, bclk_rate, &mra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) dev_err(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) "unable to configure the divisors: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * If we are already running, the wanted setup must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * the same with the one that's currently ongoing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (mchp_i2s_mcc_is_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u32 mra_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u32 mrb_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) regmap_read(dev->regmap, MCHP_I2SMCC_MRA, &mra_cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) regmap_read(dev->regmap, MCHP_I2SMCC_MRB, &mrb_cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (mra != mra_cur || mrb != mrb_cur)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (mra & MCHP_I2SMCC_MRA_SRCCLK_GCLK && !dev->gclk_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* set the rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ret = clk_set_rate(dev->gclk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) dev_err(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) "unable to set rate %lu to GCLK: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) rate, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ret = clk_prepare(dev->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dev_err(dev->dev, "unable to prepare GCLK: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) dev->gclk_use = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Save the number of channels to know what interrupts to enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) dev->channels = channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ret = regmap_write(dev->regmap, MCHP_I2SMCC_MRA, mra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (dev->gclk_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) clk_unprepare(dev->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dev->gclk_use = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return regmap_write(dev->regmap, MCHP_I2SMCC_MRB, mrb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int mchp_i2s_mcc_hw_free(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) long err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (is_playback) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) err = wait_event_interruptible_timeout(dev->wq_txrdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev->tx_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) msecs_to_jiffies(500));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (err == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dev_warn_once(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) "Timeout waiting for Tx ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) dev->tx_rdy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) err = wait_event_interruptible_timeout(dev->wq_rxrdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dev->rx_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) msecs_to_jiffies(500));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (err == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) dev_warn_once(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) "Timeout waiting for Rx ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dev->rx_rdy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (!mchp_i2s_mcc_is_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) regmap_write(dev->regmap, MCHP_I2SMCC_CR, MCHP_I2SMCC_CR_CKDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (dev->gclk_running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) clk_disable(dev->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dev->gclk_running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (dev->gclk_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) clk_unprepare(dev->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dev->gclk_use = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static int mchp_i2s_mcc_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) u32 cr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) u32 iera = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) u32 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (is_playback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) cr = MCHP_I2SMCC_CR_TXEN | MCHP_I2SMCC_CR_CKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) cr = MCHP_I2SMCC_CR_RXEN | MCHP_I2SMCC_CR_CKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) regmap_read(dev->regmap, MCHP_I2SMCC_SR, &sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (is_playback && (sr & MCHP_I2SMCC_SR_TXEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) cr = MCHP_I2SMCC_CR_TXDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) dev->tx_rdy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * Enable Tx Ready interrupts on all channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * to assure all data is sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) iera = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) } else if (!is_playback && (sr & MCHP_I2SMCC_SR_RXEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) cr = MCHP_I2SMCC_CR_RXDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) dev->rx_rdy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * Enable Rx Ready interrupts on all channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * to assure all data is received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) iera = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if ((cr & MCHP_I2SMCC_CR_CKEN) && dev->gclk_use &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) !dev->gclk_running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) err = clk_enable(dev->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dev_err_once(dev->dev, "failed to enable GCLK: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) dev->gclk_running = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) regmap_write(dev->regmap, MCHP_I2SMCC_IERA, iera);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) regmap_write(dev->regmap, MCHP_I2SMCC_CR, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static int mchp_i2s_mcc_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* Software reset the IP if it's not running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (!mchp_i2s_mcc_is_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return regmap_write(dev->regmap, MCHP_I2SMCC_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) MCHP_I2SMCC_CR_SWRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static const struct snd_soc_dai_ops mchp_i2s_mcc_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .set_sysclk = mchp_i2s_mcc_set_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .set_bclk_ratio = mchp_i2s_mcc_set_bclk_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .startup = mchp_i2s_mcc_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .trigger = mchp_i2s_mcc_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .hw_params = mchp_i2s_mcc_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .hw_free = mchp_i2s_mcc_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .set_fmt = mchp_i2s_mcc_set_dai_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .set_tdm_slot = mchp_i2s_mcc_set_dai_tdm_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static int mchp_i2s_mcc_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) init_waitqueue_head(&dev->wq_txrdy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) init_waitqueue_head(&dev->wq_rxrdy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dev->tx_rdy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) dev->rx_rdy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) snd_soc_dai_init_dma_data(dai, &dev->playback, &dev->capture);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define MCHP_I2SMCC_RATES SNDRV_PCM_RATE_8000_192000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define MCHP_I2SMCC_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) SNDRV_PCM_FMTBIT_S16_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) SNDRV_PCM_FMTBIT_S18_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) SNDRV_PCM_FMTBIT_S20_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) SNDRV_PCM_FMTBIT_S24_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) SNDRV_PCM_FMTBIT_S24_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static struct snd_soc_dai_driver mchp_i2s_mcc_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .probe = mchp_i2s_mcc_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .stream_name = "I2SMCC-Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .rates = MCHP_I2SMCC_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .formats = MCHP_I2SMCC_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .stream_name = "I2SMCC-Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .rates = MCHP_I2SMCC_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .formats = MCHP_I2SMCC_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .ops = &mchp_i2s_mcc_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .symmetric_rates = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .symmetric_samplebits = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .symmetric_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static const struct snd_soc_component_driver mchp_i2s_mcc_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .name = "mchp-i2s-mcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static const struct of_device_id mchp_i2s_mcc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .compatible = "microchip,sam9x60-i2smcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) MODULE_DEVICE_TABLE(of, mchp_i2s_mcc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static int mchp_i2s_mcc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct mchp_i2s_mcc_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) u32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) base = devm_ioremap_resource(&pdev->dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) regmap = devm_regmap_init_mmio(&pdev->dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) &mchp_i2s_mcc_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) err = devm_request_irq(&pdev->dev, irq, mchp_i2s_mcc_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) dev_name(&pdev->dev), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dev->pclk = devm_clk_get(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (IS_ERR(dev->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) err = PTR_ERR(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) "failed to get the peripheral clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* Get the optional generated clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) dev->gclk = devm_clk_get(&pdev->dev, "gclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (IS_ERR(dev->gclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (PTR_ERR(dev->gclk) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) "generated clock not found: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) dev->gclk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) dev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) dev->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) err = clk_prepare_enable(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) "failed to enable the peripheral clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) err = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) &mchp_i2s_mcc_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) &mchp_i2s_mcc_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) dev_err(&pdev->dev, "failed to register DAI: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) clk_disable_unprepare(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) dev->playback.addr = (dma_addr_t)mem->start + MCHP_I2SMCC_THR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) dev->capture.addr = (dma_addr_t)mem->start + MCHP_I2SMCC_RHR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) dev_err(&pdev->dev, "failed to register PCM: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) clk_disable_unprepare(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* Get IP version. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) regmap_read(dev->regmap, MCHP_I2SMCC_VERSION, &version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) dev_info(&pdev->dev, "hw version: %#lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) version & MCHP_I2SMCC_VERSION_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static int mchp_i2s_mcc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct mchp_i2s_mcc_dev *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) clk_disable_unprepare(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static struct platform_driver mchp_i2s_mcc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .name = "mchp_i2s_mcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .of_match_table = of_match_ptr(mchp_i2s_mcc_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .probe = mchp_i2s_mcc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .remove = mchp_i2s_mcc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) module_platform_driver(mchp_i2s_mcc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) MODULE_DESCRIPTION("Microchip I2S Multi-Channel Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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