^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __ATMEL_PDMIC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __ATMEL_PDMIC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define PDMIC_CR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define PDMIC_CR_SWRST 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PDMIC_CR_SWRST_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PDMIC_CR_SWRST_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PDMIC_CR_ENPDM_DIS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PDMIC_CR_ENPDM_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PDMIC_CR_ENPDM_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PDMIC_CR_ENPDM_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PDMIC_MR 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PDMIC_MR_CLKS_PCK 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PDMIC_MR_CLKS_GCK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PDMIC_MR_CLKS_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PDMIC_MR_CLKS_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PDMIC_MR_PRESCAL_MASK GENMASK(14, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PDMIC_MR_PRESCAL_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PDMIC_CDR 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PDMIC_IER 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PDMIC_IER_OVRE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PDMIC_IDR 0x0000001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PDMIC_IDR_OVRE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PDMIC_IMR 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PDMIC_ISR 0x00000024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PDMIC_ISR_OVRE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PDMIC_DSPR0 0x00000058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PDMIC_DSPR0_HPFBYP_DIS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PDMIC_DSPR0_HPFBYP_EN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PDMIC_DSPR0_HPFBYP_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PDMIC_DSPR0_HPFBYP_SHIFT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PDMIC_DSPR0_SINBYP_DIS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PDMIC_DSPR0_SINBYP_EN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PDMIC_DSPR0_SINBYP_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PDMIC_DSPR0_SINBYP_SHIFT (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PDMIC_DSPR0_SIZE_16_BITS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PDMIC_DSPR0_SIZE_32_BITS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PDMIC_DSPR0_SIZE_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PDMIC_DSPR0_SIZE_SHIFT (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PDMIC_DSPR0_OSR_128 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PDMIC_DSPR0_OSR_64 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PDMIC_DSPR0_OSR_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PDMIC_DSPR0_OSR_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PDMIC_DSPR0_SCALE_MASK GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PDMIC_DSPR0_SCALE_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PDMIC_DSPR0_SHIFT_MASK GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PDMIC_DSPR0_SHIFT_SHIFT (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PDMIC_DSPR1 0x0000005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PDMIC_DSPR1_DGAIN_MASK GENMASK(14, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PDMIC_DSPR1_DGAIN_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PDMIC_DSPR1_OFFSET_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PDMIC_DSPR1_OFFSET_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PDMIC_WPMR 0x000000e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PDMIC_WPSR 0x000000e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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