^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Atmel PDMIC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2015 Atmel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Songjun Wu <songjun.wu@atmel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "atmel-pdmic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct atmel_pdmic_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 mic_min_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 mic_max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) s32 mic_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) const char *card_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct atmel_pdmic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) dma_addr_t phy_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct clk *gclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) const struct atmel_pdmic_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const struct of_device_id atmel_pdmic_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .compatible = "atmel,sama5d2-pdmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MODULE_DEVICE_TABLE(of, atmel_pdmic_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PDMIC_OFFSET_MAX_VAL S16_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PDMIC_OFFSET_MIN_VAL S16_MIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static struct atmel_pdmic_pdata *atmel_pdmic_dt_init(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct atmel_pdmic_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) dev_err(dev, "device node not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (of_property_read_string(np, "atmel,model", &pdata->card_name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pdata->card_name = "PDMIC";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (of_property_read_u32(np, "atmel,mic-min-freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) &pdata->mic_min_freq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) dev_err(dev, "failed to get mic-min-freq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (of_property_read_u32(np, "atmel,mic-max-freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) &pdata->mic_max_freq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dev_err(dev, "failed to get mic-max-freq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (pdata->mic_max_freq < pdata->mic_min_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "mic-max-freq should not be less than mic-min-freq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (of_property_read_s32(np, "atmel,mic-offset", &pdata->mic_offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pdata->mic_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (pdata->mic_offset > PDMIC_OFFSET_MAX_VAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "mic-offset value %d is larger than the max value %d, the max value is specified\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) pdata->mic_offset, PDMIC_OFFSET_MAX_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) pdata->mic_offset = PDMIC_OFFSET_MAX_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) } else if (pdata->mic_offset < PDMIC_OFFSET_MIN_VAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "mic-offset value %d is less than the min value %d, the min value is specified\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pdata->mic_offset, PDMIC_OFFSET_MIN_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pdata->mic_offset = PDMIC_OFFSET_MIN_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* cpu dai component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int atmel_pdmic_cpu_dai_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct atmel_pdmic *dd = snd_soc_card_get_drvdata(rtd->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ret = clk_prepare_enable(dd->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = clk_prepare_enable(dd->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) clk_disable_unprepare(dd->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Clear all bits in the Control Register(PDMIC_CR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) regmap_write(dd->regmap, PDMIC_CR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dd->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Enable the overrun error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) regmap_write(dd->regmap, PDMIC_IER, PDMIC_IER_OVRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void atmel_pdmic_cpu_dai_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct atmel_pdmic *dd = snd_soc_card_get_drvdata(rtd->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Disable the overrun error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) regmap_write(dd->regmap, PDMIC_IDR, PDMIC_IDR_OVRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) clk_disable_unprepare(dd->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) clk_disable_unprepare(dd->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int atmel_pdmic_cpu_dai_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct atmel_pdmic *dd = snd_soc_card_get_drvdata(rtd->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct snd_soc_component *component = cpu_dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Clean the PDMIC Converted Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = regmap_read(dd->regmap, PDMIC_CDR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = snd_soc_component_update_bits(component, PDMIC_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PDMIC_CR_ENPDM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PDMIC_CR_ENPDM_DIS <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PDMIC_CR_ENPDM_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ATMEL_PDMIC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ATMEL_PDMIC_MAX_BUF_SIZE (64 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ATMEL_PDMIC_PREALLOC_BUF_SIZE ATMEL_PDMIC_MAX_BUF_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct snd_pcm_hardware atmel_pdmic_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .info = SNDRV_PCM_INFO_MMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) | SNDRV_PCM_INFO_MMAP_VALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) | SNDRV_PCM_INFO_INTERLEAVED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) | SNDRV_PCM_INFO_RESUME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) | SNDRV_PCM_INFO_PAUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .formats = ATMEL_PDMIC_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .buffer_bytes_max = ATMEL_PDMIC_MAX_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .period_bytes_min = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .period_bytes_max = 32 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .periods_max = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) atmel_pdmic_platform_configure_dma(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct dma_slave_config *slave_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct atmel_pdmic *dd = snd_soc_card_get_drvdata(rtd->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ret = snd_hwparams_to_dma_slave_config(substream, params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) slave_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_err(dd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "hw params to dma slave configure failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) slave_config->src_addr = dd->phy_base + PDMIC_CDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) slave_config->src_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) slave_config->dst_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const struct snd_dmaengine_pcm_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) atmel_pdmic_dmaengine_pcm_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .prepare_slave_config = atmel_pdmic_platform_configure_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .pcm_hardware = &atmel_pdmic_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .prealloc_buffer_size = ATMEL_PDMIC_PREALLOC_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Mic Gain = dgain * 2^(-scale) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct mic_gain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int dgain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned int scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* range from -90 dB to 90 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct mic_gain mic_gain_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { 1, 15}, { 1, 14}, /* -90, -84 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { 3, 15}, { 1, 13}, { 3, 14}, { 1, 12}, /* -81, -78, -75, -72 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { 5, 14}, { 13, 15}, /* -70, -68 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { 9, 14}, { 21, 15}, { 23, 15}, { 13, 14}, /* -65 ~ -62 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { 29, 15}, { 33, 15}, { 37, 15}, { 41, 15}, /* -61 ~ -58 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { 23, 14}, { 13, 13}, { 58, 15}, { 65, 15}, /* -57 ~ -54 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { 73, 15}, { 41, 14}, { 23, 13}, { 13, 12}, /* -53 ~ -50 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { 29, 13}, { 65, 14}, { 73, 14}, { 41, 13}, /* -49 ~ -46 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { 23, 12}, { 207, 15}, { 29, 12}, { 65, 13}, /* -45 ~ -42 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { 73, 13}, { 41, 12}, { 23, 11}, { 413, 15}, /* -41 ~ -38 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { 463, 15}, { 519, 15}, { 583, 15}, { 327, 14}, /* -37 ~ -34 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { 367, 14}, { 823, 15}, { 231, 13}, { 1036, 15}, /* -33 ~ -30 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { 1163, 15}, { 1305, 15}, { 183, 12}, { 1642, 15}, /* -29 ~ -26 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { 1843, 15}, { 2068, 15}, { 145, 11}, { 2603, 15}, /* -25 ~ -22 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { 365, 12}, { 3277, 15}, { 3677, 15}, { 4125, 15}, /* -21 ~ -18 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { 4629, 15}, { 5193, 15}, { 5827, 15}, { 3269, 14}, /* -17 ~ -14 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { 917, 12}, { 8231, 15}, { 9235, 15}, { 5181, 14}, /* -13 ~ -10 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {11627, 15}, {13045, 15}, {14637, 15}, {16423, 15}, /* -9 ~ -6 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {18427, 15}, {20675, 15}, { 5799, 13}, {26029, 15}, /* -5 ~ -2 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { 7301, 13}, { 1, 0}, {18383, 14}, {10313, 13}, /* -1 ~ 2 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {23143, 14}, {25967, 14}, {29135, 14}, {16345, 13}, /* 3 ~ 6 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { 4585, 11}, {20577, 13}, { 1443, 9}, {25905, 13}, /* 7 ~ 10 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {14533, 12}, { 8153, 11}, { 2287, 9}, {20529, 12}, /* 11 ~ 14 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {11517, 11}, { 6461, 10}, {28997, 12}, { 4067, 9}, /* 15 ~ 18 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {18253, 11}, { 10, 0}, {22979, 11}, {25783, 11}, /* 19 ~ 22 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {28929, 11}, {32459, 11}, { 9105, 9}, {20431, 10}, /* 23 ~ 26 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {22925, 10}, {12861, 9}, { 7215, 8}, {16191, 9}, /* 27 ~ 30 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { 9083, 8}, {20383, 9}, {11435, 8}, { 6145, 7}, /* 31 ~ 34 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { 3599, 6}, {32305, 9}, {18123, 8}, {20335, 8}, /* 35 ~ 38 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { 713, 3}, { 100, 0}, { 7181, 6}, { 8057, 6}, /* 39 ~ 42 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { 565, 2}, {20287, 7}, {11381, 6}, {25539, 7}, /* 43 ~ 46 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { 1791, 3}, { 4019, 4}, { 9019, 5}, {20239, 6}, /* 47 ~ 50 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { 5677, 4}, {25479, 6}, { 7147, 4}, { 8019, 4}, /* 51 ~ 54 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {17995, 5}, {20191, 5}, {11327, 4}, {12709, 4}, /* 55 ~ 58 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { 3565, 2}, { 1000, 0}, { 1122, 0}, { 1259, 0}, /* 59 ~ 62 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { 2825, 1}, {12679, 3}, { 7113, 2}, { 7981, 2}, /* 63 ~ 66 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { 8955, 2}, {20095, 3}, {22547, 3}, {12649, 2}, /* 67 ~ 70 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {28385, 3}, { 3981, 0}, {17867, 2}, {20047, 2}, /* 71 ~ 74 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {11247, 1}, {12619, 1}, {14159, 1}, {31773, 2}, /* 75 ~ 78 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {17825, 1}, {10000, 0}, {11220, 0}, {12589, 0}, /* 79 ~ 82 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {28251, 1}, {15849, 0}, {17783, 0}, {19953, 0}, /* 83 ~ 86 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {22387, 0}, {25119, 0}, {28184, 0}, {31623, 0}, /* 87 ~ 90 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const DECLARE_TLV_DB_RANGE(mic_gain_tlv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 0, 1, TLV_DB_SCALE_ITEM(-9000, 600, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 2, 5, TLV_DB_SCALE_ITEM(-8100, 300, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 6, 7, TLV_DB_SCALE_ITEM(-7000, 200, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 8, ARRAY_SIZE(mic_gain_table)-1, TLV_DB_SCALE_ITEM(-6500, 100, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int pdmic_get_mic_volsw(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned int dgain_val, scale_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dgain_val = (snd_soc_component_read(component, PDMIC_DSPR1) & PDMIC_DSPR1_DGAIN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) >> PDMIC_DSPR1_DGAIN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) scale_val = (snd_soc_component_read(component, PDMIC_DSPR0) & PDMIC_DSPR0_SCALE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) >> PDMIC_DSPR0_SCALE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) for (i = 0; i < ARRAY_SIZE(mic_gain_table); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if ((mic_gain_table[i].dgain == dgain_val) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) (mic_gain_table[i].scale == scale_val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ucontrol->value.integer.value[0] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int pdmic_put_mic_volsw(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct soc_mixer_control *mc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) (struct soc_mixer_control *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int max = mc->max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) val = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (val > max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ret = snd_soc_component_update_bits(component, PDMIC_DSPR1, PDMIC_DSPR1_DGAIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) mic_gain_table[val].dgain << PDMIC_DSPR1_DGAIN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = snd_soc_component_update_bits(component, PDMIC_DSPR0, PDMIC_DSPR0_SCALE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) mic_gain_table[val].scale << PDMIC_DSPR0_SCALE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const struct snd_kcontrol_new atmel_pdmic_snd_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) SOC_SINGLE_EXT_TLV("Mic Capture Volume", PDMIC_DSPR1, PDMIC_DSPR1_DGAIN_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ARRAY_SIZE(mic_gain_table)-1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pdmic_get_mic_volsw, pdmic_put_mic_volsw, mic_gain_tlv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) SOC_SINGLE("High Pass Filter Switch", PDMIC_DSPR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PDMIC_DSPR0_HPFBYP_SHIFT, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) SOC_SINGLE("SINCC Filter Switch", PDMIC_DSPR0, PDMIC_DSPR0_SINBYP_SHIFT, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int atmel_pdmic_component_probe(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct atmel_pdmic *dd = snd_soc_card_get_drvdata(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) snd_soc_component_update_bits(component, PDMIC_DSPR1, PDMIC_DSPR1_OFFSET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) (u32)(dd->pdata->mic_offset << PDMIC_DSPR1_OFFSET_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define PDMIC_MR_PRESCAL_MAX_VAL 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) atmel_pdmic_cpu_dai_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct atmel_pdmic *dd = snd_soc_card_get_drvdata(rtd->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct snd_soc_component *component = cpu_dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned int rate_min = substream->runtime->hw.rate_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned int rate_max = substream->runtime->hw.rate_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int fs = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int bits = params_width(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned long pclk_rate, gclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned int f_pdmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u32 mr_val, dspr0_val, pclk_prescal, gclk_prescal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (params_channels(params) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dev_err(component->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) "only supports one channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if ((fs < rate_min) || (fs > rate_max)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dev_err(component->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) "sample rate is %dHz, min rate is %dHz, max rate is %dHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) fs, rate_min, rate_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) switch (bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dspr0_val = (PDMIC_DSPR0_SIZE_16_BITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) << PDMIC_DSPR0_SIZE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dspr0_val = (PDMIC_DSPR0_SIZE_32_BITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) << PDMIC_DSPR0_SIZE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if ((fs << 7) > (rate_max << 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) f_pdmic = fs << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dspr0_val |= PDMIC_DSPR0_OSR_64 << PDMIC_DSPR0_OSR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) f_pdmic = fs << 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dspr0_val |= PDMIC_DSPR0_OSR_128 << PDMIC_DSPR0_OSR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) pclk_rate = clk_get_rate(dd->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) gclk_rate = clk_get_rate(dd->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* PRESCAL = SELCK/(2*f_pdmic) - 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) pclk_prescal = (u32)(pclk_rate/(f_pdmic << 1)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) gclk_prescal = (u32)(gclk_rate/(f_pdmic << 1)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if ((pclk_prescal > PDMIC_MR_PRESCAL_MAX_VAL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) (gclk_rate/((gclk_prescal + 1) << 1) <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) pclk_rate/((pclk_prescal + 1) << 1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) mr_val = gclk_prescal << PDMIC_MR_PRESCAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) mr_val |= PDMIC_MR_CLKS_GCK << PDMIC_MR_CLKS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) mr_val = pclk_prescal << PDMIC_MR_PRESCAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) mr_val |= PDMIC_MR_CLKS_PCK << PDMIC_MR_CLKS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) snd_soc_component_update_bits(component, PDMIC_MR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PDMIC_MR_PRESCAL_MASK | PDMIC_MR_CLKS_MASK, mr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) snd_soc_component_update_bits(component, PDMIC_DSPR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PDMIC_DSPR0_OSR_MASK | PDMIC_DSPR0_SIZE_MASK, dspr0_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int atmel_pdmic_cpu_dai_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int cmd, struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct snd_soc_component *component = cpu_dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) val = PDMIC_CR_ENPDM_EN << PDMIC_CR_ENPDM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) val = PDMIC_CR_ENPDM_DIS << PDMIC_CR_ENPDM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) snd_soc_component_update_bits(component, PDMIC_CR, PDMIC_CR_ENPDM_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static const struct snd_soc_dai_ops atmel_pdmic_cpu_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .startup = atmel_pdmic_cpu_dai_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .shutdown = atmel_pdmic_cpu_dai_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .prepare = atmel_pdmic_cpu_dai_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .hw_params = atmel_pdmic_cpu_dai_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .trigger = atmel_pdmic_cpu_dai_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static struct snd_soc_dai_driver atmel_pdmic_cpu_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .stream_name = "Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .channels_max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .rates = SNDRV_PCM_RATE_KNOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .formats = ATMEL_PDMIC_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .ops = &atmel_pdmic_cpu_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static const struct snd_soc_component_driver atmel_pdmic_cpu_dai_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .name = "atmel-pdmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .probe = atmel_pdmic_component_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .controls = atmel_pdmic_snd_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .num_controls = ARRAY_SIZE(atmel_pdmic_snd_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .idle_bias_on = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .use_pmdown_time = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .endianness = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* ASoC sound card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int atmel_pdmic_asoc_card_init(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct snd_soc_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct snd_soc_dai_link *dai_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct atmel_pdmic *dd = snd_soc_card_get_drvdata(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct snd_soc_dai_link_component *comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dai_link = devm_kzalloc(dev, sizeof(*dai_link), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (!dai_link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) comp = devm_kzalloc(dev, 3 * sizeof(*comp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (!comp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dai_link->cpus = &comp[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dai_link->codecs = &comp[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dai_link->platforms = &comp[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dai_link->num_cpus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dai_link->num_codecs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dai_link->num_platforms = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dai_link->name = "PDMIC";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dai_link->stream_name = "PDMIC PCM";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dai_link->codecs->dai_name = "snd-soc-dummy-dai";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dai_link->cpus->dai_name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dai_link->codecs->name = "snd-soc-dummy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dai_link->platforms->name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) card->dai_link = dai_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) card->num_links = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) card->name = dd->pdata->card_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) card->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static void atmel_pdmic_get_sample_rate(struct atmel_pdmic *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned int *rate_min, unsigned int *rate_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u32 mic_min_freq = dd->pdata->mic_min_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u32 mic_max_freq = dd->pdata->mic_max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u32 clk_max_rate = (u32)(clk_get_rate(dd->pclk) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u32 clk_min_rate = (u32)(clk_get_rate(dd->gclk) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (mic_max_freq > clk_max_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) mic_max_freq = clk_max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (mic_min_freq < clk_min_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) mic_min_freq = clk_min_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) *rate_min = DIV_ROUND_CLOSEST(mic_min_freq, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) *rate_max = mic_max_freq >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* PDMIC interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static irqreturn_t atmel_pdmic_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct atmel_pdmic *dd = (struct atmel_pdmic *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u32 pdmic_isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) regmap_read(dd->regmap, PDMIC_ISR, &pdmic_isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (pdmic_isr & PDMIC_ISR_OVRE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) regmap_update_bits(dd->regmap, PDMIC_CR, PDMIC_CR_ENPDM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) PDMIC_CR_ENPDM_DIS << PDMIC_CR_ENPDM_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) snd_pcm_stop_xrun(dd->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* regmap configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define ATMEL_PDMIC_REG_MAX 0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static const struct regmap_config atmel_pdmic_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .max_register = ATMEL_PDMIC_REG_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static int atmel_pdmic_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct atmel_pdmic *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) const struct atmel_pdmic_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct snd_soc_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) unsigned int rate_min, rate_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) pdata = atmel_pdmic_dt_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (IS_ERR(pdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return PTR_ERR(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dd = devm_kzalloc(dev, sizeof(*dd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (!dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dd->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dd->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dd->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (dd->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return dd->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dd->pclk = devm_clk_get(dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (IS_ERR(dd->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ret = PTR_ERR(dd->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dev_err(dev, "failed to get peripheral clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dd->gclk = devm_clk_get(dev, "gclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (IS_ERR(dd->gclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ret = PTR_ERR(dd->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dev_err(dev, "failed to get GCK: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* The gclk clock frequency must always be three times
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * lower than the pclk clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = clk_set_rate(dd->gclk, clk_get_rate(dd->pclk)/3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dev_err(dev, "failed to set GCK clock rate: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) io_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (IS_ERR(io_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return PTR_ERR(io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dd->phy_base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dd->regmap = devm_regmap_init_mmio(dev, io_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) &atmel_pdmic_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (IS_ERR(dd->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ret = PTR_ERR(dd->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dev_err(dev, "failed to init register map: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ret = devm_request_irq(dev, dd->irq, atmel_pdmic_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) "PDMIC", (void *)dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dd->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* Get the minimal and maximal sample rate that the microphone supports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) atmel_pdmic_get_sample_rate(dd, &rate_min, &rate_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* register cpu dai */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) atmel_pdmic_cpu_dai.capture.rate_min = rate_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) atmel_pdmic_cpu_dai.capture.rate_max = rate_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ret = devm_snd_soc_register_component(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) &atmel_pdmic_cpu_dai_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) &atmel_pdmic_cpu_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dev_err(dev, "could not register CPU DAI: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* register platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ret = devm_snd_dmaengine_pcm_register(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) &atmel_pdmic_dmaengine_pcm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dev_err(dev, "could not register platform: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* register sound card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (!card) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) goto unregister_codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) snd_soc_card_set_drvdata(card, dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ret = atmel_pdmic_asoc_card_init(dev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dev_err(dev, "failed to init sound card: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) goto unregister_codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ret = devm_snd_soc_register_card(dev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_err(dev, "failed to register sound card: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) goto unregister_codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) unregister_codec:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static int atmel_pdmic_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static struct platform_driver atmel_pdmic_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .name = "atmel-pdmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .of_match_table = of_match_ptr(atmel_pdmic_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .pm = &snd_soc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .probe = atmel_pdmic_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .remove = atmel_pdmic_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) module_platform_driver(atmel_pdmic_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) MODULE_DESCRIPTION("Atmel PDMIC driver under ALSA SoC architecture");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) MODULE_AUTHOR("Songjun Wu <songjun.wu@atmel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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