^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * at91-pcm.h - ALSA PCM interface for the Atmel AT91 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005 SAN People
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008 Atmel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Authors: Sedji Gaouaou <sedji.gaouaou@atmel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Based on at91-pcm. by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Frank Mandarino <fmandarino@endrelia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright 2006 Endrelia Technologies Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Based on pxa2xx-pcm.c by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Author: Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Created: Nov 30, 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Copyright: (C) 2004 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifndef _ATMEL_PCM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define _ATMEL_PCM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/atmel-ssc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ATMEL_SSC_DMABUF_SIZE (64 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Registers and status bits that are required by the PCM driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct atmel_pdc_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned int xpr; /* PDC recv/trans pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned int xcr; /* PDC recv/trans counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned int xnpr; /* PDC next recv/trans pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned int xncr; /* PDC next recv/trans counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned int ptcr; /* PDC transfer control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct atmel_ssc_mask {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 ssc_enable; /* SSC recv/trans enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 ssc_disable; /* SSC recv/trans disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 ssc_error; /* SSC error conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 ssc_endx; /* SSC ENDTX or ENDRX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 ssc_endbuf; /* SSC TXBUFE or RXBUFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 pdc_enable; /* PDC recv/trans enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 pdc_disable; /* PDC recv/trans disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * This structure, shared between the PCM driver and the interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * contains all information required by the PCM driver to perform the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * PDC DMA operation. All fields except dma_intr_handler() are initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * by the interface. The dma_intr_handler() pointer is set by the PCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * driver and called by the interface SSC interrupt handler if it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * non-NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct atmel_pcm_dma_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) char *name; /* stream identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int pdc_xfer_size; /* PDC counter increment in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct ssc_device *ssc; /* SSC device for stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct atmel_pdc_regs *pdc; /* PDC receive or transmit registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct atmel_ssc_mask *mask; /* SSC & PDC status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void (*dma_intr_handler)(u32, struct snd_pcm_substream *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * SSC register access (since ssc_writel() / ssc_readl() require literal name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ssc_readx(base, reg) (__raw_readl((base) + (reg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ssc_writex(base, reg, value) __raw_writel((value), (base) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #if IS_ENABLED(CONFIG_SND_ATMEL_SOC_PDC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int atmel_pcm_pdc_platform_register(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static inline int atmel_pcm_pdc_platform_register(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #if IS_ENABLED(CONFIG_SND_ATMEL_SOC_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int atmel_pcm_dma_platform_register(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static inline int atmel_pcm_dma_platform_register(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #endif /* _ATMEL_PCM_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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