^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Atmel I2S controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Atmel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ATMEL_I2SC_MAX_TDM_CHANNELS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * ---- I2S Controller Register map ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ATMEL_I2SC_CR 0x0000 /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ATMEL_I2SC_MR 0x0004 /* Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ATMEL_I2SC_SR 0x0008 /* Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ATMEL_I2SC_SCR 0x000c /* Status Clear Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ATMEL_I2SC_SSR 0x0010 /* Status Set Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ATMEL_I2SC_IER 0x0014 /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ATMEL_I2SC_IDR 0x0018 /* Interrupt Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ATMEL_I2SC_IMR 0x001c /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ATMEL_I2SC_RHR 0x0020 /* Receiver Holding Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ATMEL_I2SC_THR 0x0024 /* Transmitter Holding Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ATMEL_I2SC_VERSION 0x0028 /* Version Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * ---- Control Register (Write-only) ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ATMEL_I2SC_CR_RXEN BIT(0) /* Receiver Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ATMEL_I2SC_CR_RXDIS BIT(1) /* Receiver Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ATMEL_I2SC_CR_CKEN BIT(2) /* Clock Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ATMEL_I2SC_CR_CKDIS BIT(3) /* Clock Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ATMEL_I2SC_CR_TXEN BIT(4) /* Transmitter Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ATMEL_I2SC_CR_TXDIS BIT(5) /* Transmitter Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ATMEL_I2SC_CR_SWRST BIT(7) /* Software Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * ---- Mode Register (Read/Write) ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ATMEL_I2SC_MR_MODE_MASK GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ATMEL_I2SC_MR_MODE_SLAVE (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ATMEL_I2SC_MR_MODE_MASTER (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ATMEL_I2SC_MR_DATALENGTH_MASK GENMASK(4, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ATMEL_I2SC_MR_DATALENGTH_32_BITS (0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ATMEL_I2SC_MR_DATALENGTH_24_BITS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ATMEL_I2SC_MR_DATALENGTH_20_BITS (2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ATMEL_I2SC_MR_DATALENGTH_18_BITS (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ATMEL_I2SC_MR_DATALENGTH_16_BITS (4 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ATMEL_I2SC_MR_DATALENGTH_16_BITS_COMPACT (5 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ATMEL_I2SC_MR_DATALENGTH_8_BITS (6 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ATMEL_I2SC_MR_DATALENGTH_8_BITS_COMPACT (7 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ATMEL_I2SC_MR_FORMAT_MASK GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ATMEL_I2SC_MR_FORMAT_I2S (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ATMEL_I2SC_MR_FORMAT_LJ (1 << 6) /* Left Justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ATMEL_I2SC_MR_FORMAT_TDM (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ATMEL_I2SC_MR_FORMAT_TDMLJ (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Left audio samples duplicated to right audio channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ATMEL_I2SC_MR_RXMONO BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Receiver uses one DMA channel ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ATMEL_I2SC_MR_RXDMA_MASK GENMASK(9, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ATMEL_I2SC_MR_RXDMA_SINGLE (0 << 9) /* for all audio channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ATMEL_I2SC_MR_RXDMA_MULTIPLE (1 << 9) /* per audio channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* I2SDO output of I2SC is internally connected to I2SDI input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ATMEL_I2SC_MR_RXLOOP BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Left audio samples duplicated to right audio channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ATMEL_I2SC_MR_TXMONO BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Transmitter uses one DMA channel ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ATMEL_I2SC_MR_TXDMA_MASK GENMASK(13, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ATMEL_I2SC_MR_TXDMA_SINGLE (0 << 13) /* for all audio channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ATMEL_I2SC_MR_TXDME_MULTIPLE (1 << 13) /* per audio channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* x sample transmitted when underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ATMEL_I2SC_MR_TXSAME_MASK GENMASK(14, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ATMEL_I2SC_MR_TXSAME_ZERO (0 << 14) /* Zero sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ATMEL_I2SC_MR_TXSAME_PREVIOUS (1 << 14) /* Previous sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Audio Clock to I2SC Master Clock ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ATMEL_I2SC_MR_IMCKDIV_MASK GENMASK(21, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ATMEL_I2SC_MR_IMCKDIV(div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) (((div) << 16) & ATMEL_I2SC_MR_IMCKDIV_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Master Clock to fs ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ATMEL_I2SC_MR_IMCKFS_MASK GENMASK(29, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ATMEL_I2SC_MR_IMCKFS(fs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) (((fs) << 24) & ATMEL_I2SC_MR_IMCKFS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Master Clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ATMEL_I2SC_MR_IMCKMODE_MASK GENMASK(30, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* 0: No master clock generated (selected clock drives I2SCK pin) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ATMEL_I2SC_MR_IMCKMODE_I2SCK (0 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* 1: master clock generated (internally generated clock drives I2SMCK pin) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ATMEL_I2SC_MR_IMCKMODE_I2SMCK (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Slot Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* 0: slot is 32 bits wide for DATALENGTH = 18/20/24 bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* 1: slot is 24 bits wide for DATALENGTH = 18/20/24 bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ATMEL_I2SC_MR_IWS BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * ---- Status Registers ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ATMEL_I2SC_SR_RXEN BIT(0) /* Receiver Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ATMEL_I2SC_SR_RXRDY BIT(1) /* Receive Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ATMEL_I2SC_SR_RXOR BIT(2) /* Receive Overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ATMEL_I2SC_SR_TXEN BIT(4) /* Transmitter Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ATMEL_I2SC_SR_TXRDY BIT(5) /* Transmit Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ATMEL_I2SC_SR_TXUR BIT(6) /* Transmit Underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Receive Overrun Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ATMEL_I2SC_SR_RXORCH_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ATMEL_I2SC_SR_RXORCH(ch) (1 << (((ch) & 0x7) + 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Transmit Underrun Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ATMEL_I2SC_SR_TXURCH_MASK GENMASK(27, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ATMEL_I2SC_SR_TXURCH(ch) (1 << (((ch) & 0x7) + 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * ---- Interrupt Enable/Disable/Mask Registers ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ATMEL_I2SC_INT_RXRDY ATMEL_I2SC_SR_RXRDY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ATMEL_I2SC_INT_RXOR ATMEL_I2SC_SR_RXOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ATMEL_I2SC_INT_TXRDY ATMEL_I2SC_SR_TXRDY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ATMEL_I2SC_INT_TXUR ATMEL_I2SC_SR_TXUR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct regmap_config atmel_i2s_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .max_register = ATMEL_I2SC_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct atmel_i2s_gck_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned long mck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int imckdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int imckfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define I2S_MCK_12M288 12288000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define I2S_MCK_11M2896 11289600UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* mck = (32 * (imckfs+1) / (imckdiv+1)) * fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct atmel_i2s_gck_param gck_params[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* mck = 12.288MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { 8000, I2S_MCK_12M288, 0, 47}, /* mck = 1536 fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { 16000, I2S_MCK_12M288, 1, 47}, /* mck = 768 fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { 24000, I2S_MCK_12M288, 3, 63}, /* mck = 512 fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { 32000, I2S_MCK_12M288, 3, 47}, /* mck = 384 fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { 48000, I2S_MCK_12M288, 7, 63}, /* mck = 256 fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { 64000, I2S_MCK_12M288, 7, 47}, /* mck = 192 fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { 96000, I2S_MCK_12M288, 7, 31}, /* mck = 128 fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {192000, I2S_MCK_12M288, 7, 15}, /* mck = 64 fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* mck = 11.2896MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { 11025, I2S_MCK_11M2896, 1, 63}, /* mck = 1024 fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { 22050, I2S_MCK_11M2896, 3, 63}, /* mck = 512 fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { 44100, I2S_MCK_11M2896, 7, 63}, /* mck = 256 fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { 88200, I2S_MCK_11M2896, 7, 31}, /* mck = 128 fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {176400, I2S_MCK_11M2896, 7, 15}, /* mck = 64 fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct atmel_i2s_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct atmel_i2s_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int (*mck_init)(struct atmel_i2s_dev *, struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct atmel_i2s_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct clk *gclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct snd_dmaengine_dai_dma_data playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct snd_dmaengine_dai_dma_data capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) const struct atmel_i2s_gck_param *gck_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) const struct atmel_i2s_caps *caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int clk_use_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static irqreturn_t atmel_i2s_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct atmel_i2s_dev *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int sr, imr, pending, ch, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) regmap_read(dev->regmap, ATMEL_I2SC_IMR, &imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pending = sr & imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (!pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (pending & ATMEL_I2SC_INT_RXOR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mask = ATMEL_I2SC_SR_RXOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (sr & ATMEL_I2SC_SR_RXORCH(ch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) mask |= ATMEL_I2SC_SR_RXORCH(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_err(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "RX overrun on channel %d\n", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (pending & ATMEL_I2SC_INT_TXUR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mask = ATMEL_I2SC_SR_TXUR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (sr & ATMEL_I2SC_SR_TXURCH(ch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mask |= ATMEL_I2SC_SR_TXURCH(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_err(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "TX underrun on channel %d\n", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define ATMEL_I2S_RATES SNDRV_PCM_RATE_8000_192000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define ATMEL_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) SNDRV_PCM_FMTBIT_S16_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) SNDRV_PCM_FMTBIT_S18_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) SNDRV_PCM_FMTBIT_S20_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) SNDRV_PCM_FMTBIT_S24_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) SNDRV_PCM_FMTBIT_S24_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int atmel_i2s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dev->fmt = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int atmel_i2s_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned int rhr, sr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (is_playback) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (sr & ATMEL_I2SC_SR_RXRDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * The RX Ready flag should not be set. However if here,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * we flush (read) the Receive Holding Register to start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * from a clean state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_dbg(dev->dev, "RXRDY is set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) regmap_read(dev->regmap, ATMEL_I2SC_RHR, &rhr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int atmel_i2s_get_gck_param(struct atmel_i2s_dev *dev, int fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int i, best;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!dev->gclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_err(dev->dev, "cannot generate the I2S Master Clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * Find the best possible settings to generate the I2S Master Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * from the PLL Audio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dev->gck_param = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) best = INT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) for (i = 0; i < ARRAY_SIZE(gck_params); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) const struct atmel_i2s_gck_param *gck_param = &gck_params[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int val = abs(fs - gck_param->fs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (val < best) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) best = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev->gck_param = gck_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int atmel_i2s_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned int mr = 0, mr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) mr_mask = ATMEL_I2SC_MR_FORMAT_MASK | ATMEL_I2SC_MR_MODE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ATMEL_I2SC_MR_DATALENGTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (is_playback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) mr_mask |= ATMEL_I2SC_MR_TXMONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) mr_mask |= ATMEL_I2SC_MR_RXMONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) mr |= ATMEL_I2SC_MR_FORMAT_I2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev_err(dev->dev, "unsupported bus format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* codec is slave, so cpu is master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) mr |= ATMEL_I2SC_MR_MODE_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ret = atmel_i2s_get_gck_param(dev, params_rate(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* codec is master, so cpu is slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) mr |= ATMEL_I2SC_MR_MODE_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dev->gck_param = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev_err(dev->dev, "unsupported master/slave mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) switch (params_channels(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (is_playback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) mr |= ATMEL_I2SC_MR_TXMONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mr |= ATMEL_I2SC_MR_RXMONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev_err(dev->dev, "unsupported number of audio channels\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) case SNDRV_PCM_FORMAT_S8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) mr |= ATMEL_I2SC_MR_DATALENGTH_8_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) mr |= ATMEL_I2SC_MR_DATALENGTH_16_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case SNDRV_PCM_FORMAT_S18_3LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) mr |= ATMEL_I2SC_MR_DATALENGTH_18_BITS | ATMEL_I2SC_MR_IWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case SNDRV_PCM_FORMAT_S20_3LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) mr |= ATMEL_I2SC_MR_DATALENGTH_20_BITS | ATMEL_I2SC_MR_IWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case SNDRV_PCM_FORMAT_S24_3LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS | ATMEL_I2SC_MR_IWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case SNDRV_PCM_FORMAT_S24_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case SNDRV_PCM_FORMAT_S32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) mr |= ATMEL_I2SC_MR_DATALENGTH_32_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_err(dev->dev, "unsupported size/endianness for audio samples\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return regmap_update_bits(dev->regmap, ATMEL_I2SC_MR, mr_mask, mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int atmel_i2s_switch_mck_generator(struct atmel_i2s_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) bool enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) unsigned int mr, mr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned long gclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) mr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) mr_mask = (ATMEL_I2SC_MR_IMCKDIV_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ATMEL_I2SC_MR_IMCKFS_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ATMEL_I2SC_MR_IMCKMODE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (!enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Disable the I2S Master Clock generator. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ret = regmap_write(dev->regmap, ATMEL_I2SC_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ATMEL_I2SC_CR_CKDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Reset the I2S Master Clock generator settings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = regmap_update_bits(dev->regmap, ATMEL_I2SC_MR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mr_mask, mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* Disable/unprepare the PMC generated clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) clk_disable_unprepare(dev->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (!dev->gck_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) gclk_rate = dev->gck_param->mck * (dev->gck_param->imckdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ret = clk_set_rate(dev->gclk, gclk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = clk_prepare_enable(dev->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Update the Mode Register to generate the I2S Master Clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) mr |= ATMEL_I2SC_MR_IMCKDIV(dev->gck_param->imckdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) mr |= ATMEL_I2SC_MR_IMCKFS(dev->gck_param->imckfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) mr |= ATMEL_I2SC_MR_IMCKMODE_I2SMCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = regmap_update_bits(dev->regmap, ATMEL_I2SC_MR, mr_mask, mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Finally enable the I2S Master Clock generator. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return regmap_write(dev->regmap, ATMEL_I2SC_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ATMEL_I2SC_CR_CKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int atmel_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) bool is_master, mck_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) unsigned int cr, mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) cr = is_playback ? ATMEL_I2SC_CR_TXEN : ATMEL_I2SC_CR_RXEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) mck_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) cr = is_playback ? ATMEL_I2SC_CR_TXDIS : ATMEL_I2SC_CR_RXDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) mck_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Read the Mode Register to retrieve the master/slave state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) err = regmap_read(dev->regmap, ATMEL_I2SC_MR, &mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) is_master = (mr & ATMEL_I2SC_MR_MODE_MASK) == ATMEL_I2SC_MR_MODE_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* If master starts, enable the audio clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (is_master && mck_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (!dev->clk_use_no) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) err = atmel_i2s_switch_mck_generator(dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dev->clk_use_no++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) err = regmap_write(dev->regmap, ATMEL_I2SC_CR, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* If master stops, disable the audio clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (is_master && !mck_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (dev->clk_use_no == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) err = atmel_i2s_switch_mck_generator(dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) dev->clk_use_no--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const struct snd_soc_dai_ops atmel_i2s_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .prepare = atmel_i2s_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .trigger = atmel_i2s_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .hw_params = atmel_i2s_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .set_fmt = atmel_i2s_set_dai_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int atmel_i2s_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) snd_soc_dai_init_dma_data(dai, &dev->playback, &dev->capture);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static struct snd_soc_dai_driver atmel_i2s_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .probe = atmel_i2s_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .rates = ATMEL_I2S_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .formats = ATMEL_I2S_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .rates = ATMEL_I2S_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .formats = ATMEL_I2S_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .ops = &atmel_i2s_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .symmetric_rates = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static const struct snd_soc_component_driver atmel_i2s_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .name = "atmel-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int atmel_i2s_sama5d2_mck_init(struct atmel_i2s_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct clk *muxclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (!dev->gclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* muxclk is optional, so we return error for probe defer only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) muxclk = devm_clk_get(dev->dev, "muxclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (IS_ERR(muxclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) err = PTR_ERR(muxclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (err == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dev_warn(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) "failed to get the I2S clock control: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return clk_set_parent(muxclk, dev->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static const struct atmel_i2s_caps atmel_i2s_sama5d2_caps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .mck_init = atmel_i2s_sama5d2_mck_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static const struct of_device_id atmel_i2s_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .compatible = "atmel,sama5d2-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .data = (void *)&atmel_i2s_sama5d2_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MODULE_DEVICE_TABLE(of, atmel_i2s_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int atmel_i2s_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct atmel_i2s_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) unsigned int pcm_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) unsigned int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* Get memory for driver data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* Get hardware capabilities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) match = of_match_node(atmel_i2s_dt_ids, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev->caps = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* Map I/O registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) base = devm_ioremap_resource(&pdev->dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) regmap = devm_regmap_init_mmio(&pdev->dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) &atmel_i2s_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Request IRQ. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) err = devm_request_irq(&pdev->dev, irq, atmel_i2s_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dev_name(&pdev->dev), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* Get the peripheral clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dev->pclk = devm_clk_get(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (IS_ERR(dev->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) err = PTR_ERR(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) "failed to get the peripheral clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Get audio clock to generate the I2S Master Clock (I2S_MCK) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dev->gclk = devm_clk_get(&pdev->dev, "gclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (IS_ERR(dev->gclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (PTR_ERR(dev->gclk) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* Master Mode not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dev->gclk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dev->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Do hardware specific settings to initialize I2S_MCK generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (dev->caps && dev->caps->mck_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) err = dev->caps->mck_init(dev, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* Enable the peripheral clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) err = clk_prepare_enable(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* Get IP version. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) regmap_read(dev->regmap, ATMEL_I2SC_VERSION, &version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_info(&pdev->dev, "hw version: %#x\n", version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Enable error interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) regmap_write(dev->regmap, ATMEL_I2SC_IER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ATMEL_I2SC_INT_RXOR | ATMEL_I2SC_INT_TXUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) err = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) &atmel_i2s_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) &atmel_i2s_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev_err(&pdev->dev, "failed to register DAI: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) clk_disable_unprepare(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* Prepare DMA config. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dev->playback.addr = (dma_addr_t)mem->start + ATMEL_I2SC_THR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) dev->playback.maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dev->capture.addr = (dma_addr_t)mem->start + ATMEL_I2SC_RHR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dev->capture.maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (of_property_match_string(np, "dma-names", "rx-tx") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) pcm_flags |= SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, pcm_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dev_err(&pdev->dev, "failed to register PCM: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) clk_disable_unprepare(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static int atmel_i2s_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct atmel_i2s_dev *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) clk_disable_unprepare(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static struct platform_driver atmel_i2s_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .name = "atmel_i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .of_match_table = of_match_ptr(atmel_i2s_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .probe = atmel_i2s_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .remove = atmel_i2s_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) module_platform_driver(atmel_i2s_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) MODULE_DESCRIPTION("Atmel I2S Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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