^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __ATMEL_CLASSD_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __ATMEL_CLASSD_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define CLASSD_CR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define CLASSD_CR_RESET 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define CLASSD_MR 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CLASSD_MR_LEN_DIS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CLASSD_MR_LEN_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLASSD_MR_LEN_MASK (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLASSD_MR_LEN_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLASSD_MR_LMUTE_DIS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLASSD_MR_LMUTE_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLASSD_MR_LMUTE_SHIFT (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLASSD_MR_LMUTE_MASK (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLASSD_MR_REN_DIS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLASSD_MR_REN_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLASSD_MR_REN_MASK (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLASSD_MR_REN_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLASSD_MR_RMUTE_DIS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLASSD_MR_RMUTE_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLASSD_MR_RMUTE_SHIFT (0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLASSD_MR_RMUTE_MASK (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLASSD_MR_PWMTYP_SINGLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLASSD_MR_PWMTYP_DIFF 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLASSD_MR_PWMTYP_MASK (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLASSD_MR_PWMTYP_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLASSD_MR_NON_OVERLAP_DIS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLASSD_MR_NON_OVERLAP_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLASSD_MR_NON_OVERLAP_MASK (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLASSD_MR_NON_OVERLAP_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLASSD_MR_NOVR_VAL_5NS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLASSD_MR_NOVR_VAL_10NS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLASSD_MR_NOVR_VAL_15NS 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLASSD_MR_NOVR_VAL_20NS 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLASSD_MR_NOVR_VAL_MASK (0x3 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLASSD_MR_NOVR_VAL_SHIFT (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLASSD_INTPMR 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLASSD_INTPMR_ATTL_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLASSD_INTPMR_ATTL_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLASSD_INTPMR_ATTR_MASK (0x3f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLASSD_INTPMR_ATTR_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLASSD_INTPMR_DSP_CLK_FREQ_12M288 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLASSD_INTPMR_DSP_CLK_FREQ_11M2896 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLASSD_INTPMR_DSP_CLK_FREQ_MASK (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLASSD_INTPMR_DSP_CLK_FREQ_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLASSD_INTPMR_DEEMP_DIS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLASSD_INTPMR_DEEMP_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLASSD_INTPMR_DEEMP_MASK (0x1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLASSD_INTPMR_DEEMP_SHIFT (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLASSD_INTPMR_SWAP_LEFT_ON_LSB 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLASSD_INTPMR_SWAP_RIGHT_ON_LSB 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLASSD_INTPMR_SWAP_MASK (0x1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLASSD_INTPMR_SWAP_SHIFT (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLASSD_INTPMR_FRAME_8K 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLASSD_INTPMR_FRAME_16K 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLASSD_INTPMR_FRAME_32K 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLASSD_INTPMR_FRAME_48K 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLASSD_INTPMR_FRAME_96K 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLASSD_INTPMR_FRAME_22K 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLASSD_INTPMR_FRAME_44K 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CLASSD_INTPMR_FRAME_88K 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CLASSD_INTPMR_FRAME_MASK (0x7 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CLASSD_INTPMR_FRAME_SHIFT (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLASSD_INTPMR_EQCFG_FLAT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CLASSD_INTPMR_EQCFG_B_BOOST_12 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CLASSD_INTPMR_EQCFG_B_BOOST_6 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CLASSD_INTPMR_EQCFG_B_CUT_12 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CLASSD_INTPMR_EQCFG_B_CUT_6 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CLASSD_INTPMR_EQCFG_M_BOOST_3 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CLASSD_INTPMR_EQCFG_M_BOOST_8 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CLASSD_INTPMR_EQCFG_M_CUT_3 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CLASSD_INTPMR_EQCFG_M_CUT_8 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CLASSD_INTPMR_EQCFG_T_BOOST_12 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CLASSD_INTPMR_EQCFG_T_BOOST_6 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CLASSD_INTPMR_EQCFG_T_CUT_12 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CLASSD_INTPMR_EQCFG_T_CUT_6 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CLASSD_INTPMR_EQCFG_SHIFT (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CLASSD_INTPMR_MONO_DIS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CLASSD_INTPMR_MONO_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CLASSD_INTPMR_MONO_MASK (0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLASSD_INTPMR_MONO_SHIFT (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLASSD_INTPMR_MONO_MODE_MIX 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLASSD_INTPMR_MONO_MODE_SAT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLASSD_INTPMR_MONO_MODE_LEFT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLASSD_INTPMR_MONO_MODE_RIGHT 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLASSD_INTPMR_MONO_MODE_MASK (0x3 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLASSD_INTPMR_MONO_MODE_SHIFT (29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLASSD_INTSR 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLASSD_THR 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLASSD_IER 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLASSD_IDR 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLASSD_IMR 0x0000001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLASSD_ISR 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLASSD_WPMR 0x000000e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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