^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Atmel ALSA SoC Audio Class D Amplifier (CLASSD) driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2015 Atmel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Songjun Wu <songjun.wu@atmel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "atmel-classd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct atmel_classd_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) bool non_overlap_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int non_overlap_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) int pwm_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) const char *card_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct atmel_classd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) dma_addr_t phy_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct clk *gclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) const struct atmel_classd_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const struct of_device_id atmel_classd_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .compatible = "atmel,sama5d2-classd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MODULE_DEVICE_TABLE(of, atmel_classd_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static struct atmel_classd_pdata *atmel_classd_dt_init(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct atmel_classd_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) const char *pwm_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) dev_err(dev, "device node not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ret = of_property_read_string(np, "atmel,pwm-type", &pwm_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if ((ret == 0) && (strcmp(pwm_type, "diff") == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pdata->pwm_type = CLASSD_MR_PWMTYP_DIFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pdata->pwm_type = CLASSD_MR_PWMTYP_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ret = of_property_read_u32(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "atmel,non-overlap-time", &pdata->non_overlap_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pdata->non_overlap_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pdata->non_overlap_enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ret = of_property_read_string(np, "atmel,model", &pdata->card_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pdata->card_name = "CLASSD";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static inline struct atmel_classd_pdata *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) atmel_classd_dt_init(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ATMEL_CLASSD_RATES (SNDRV_PCM_RATE_8000 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) | SNDRV_PCM_RATE_96000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const struct snd_pcm_hardware atmel_classd_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .info = SNDRV_PCM_INFO_MMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) | SNDRV_PCM_INFO_MMAP_VALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) | SNDRV_PCM_INFO_INTERLEAVED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) | SNDRV_PCM_INFO_RESUME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) | SNDRV_PCM_INFO_PAUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .formats = (SNDRV_PCM_FMTBIT_S16_LE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .rates = ATMEL_CLASSD_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .buffer_bytes_max = 64 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .period_bytes_min = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .period_bytes_max = 32 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .periods_max = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ATMEL_CLASSD_PREALLOC_BUF_SIZE (64 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* cpu dai component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int atmel_classd_cpu_dai_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) regmap_write(dd->regmap, CLASSD_THR, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) err = clk_prepare_enable(dd->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) err = clk_prepare_enable(dd->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) clk_disable_unprepare(dd->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) atmel_classd_platform_configure_dma(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct dma_slave_config *slave_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (params_physical_width(params) != 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dev_err(dd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "only supports 16-bit audio data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (params_channels(params) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) slave_config->direction = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) slave_config->dst_addr = dd->phy_base + CLASSD_THR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) slave_config->dst_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) slave_config->src_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) slave_config->device_fc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct snd_dmaengine_pcm_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) atmel_classd_dmaengine_pcm_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .prepare_slave_config = atmel_classd_platform_configure_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .pcm_hardware = &atmel_classd_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .prealloc_buffer_size = ATMEL_CLASSD_PREALLOC_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const char * const mono_mode_text[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "mix", "sat", "left", "right"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static SOC_ENUM_SINGLE_DECL(classd_mono_mode_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) CLASSD_INTPMR, CLASSD_INTPMR_MONO_MODE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mono_mode_text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const char * const eqcfg_text[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "Treble-12dB", "Treble-6dB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "Medium-8dB", "Medium-3dB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "Bass-12dB", "Bass-6dB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "0 dB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "Bass+6dB", "Bass+12dB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "Medium+3dB", "Medium+8dB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "Treble+6dB", "Treble+12dB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const unsigned int eqcfg_value[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) CLASSD_INTPMR_EQCFG_T_CUT_12, CLASSD_INTPMR_EQCFG_T_CUT_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) CLASSD_INTPMR_EQCFG_M_CUT_8, CLASSD_INTPMR_EQCFG_M_CUT_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) CLASSD_INTPMR_EQCFG_B_CUT_12, CLASSD_INTPMR_EQCFG_B_CUT_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) CLASSD_INTPMR_EQCFG_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) CLASSD_INTPMR_EQCFG_B_BOOST_6, CLASSD_INTPMR_EQCFG_B_BOOST_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) CLASSD_INTPMR_EQCFG_M_BOOST_3, CLASSD_INTPMR_EQCFG_M_BOOST_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) CLASSD_INTPMR_EQCFG_T_BOOST_6, CLASSD_INTPMR_EQCFG_T_BOOST_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static SOC_VALUE_ENUM_SINGLE_DECL(classd_eqcfg_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) CLASSD_INTPMR, CLASSD_INTPMR_EQCFG_SHIFT, 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) eqcfg_text, eqcfg_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const DECLARE_TLV_DB_SCALE(classd_digital_tlv, -7800, 100, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct snd_kcontrol_new atmel_classd_snd_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) SOC_DOUBLE_TLV("Playback Volume", CLASSD_INTPMR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) CLASSD_INTPMR_ATTL_SHIFT, CLASSD_INTPMR_ATTR_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 78, 1, classd_digital_tlv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) SOC_SINGLE("Deemphasis Switch", CLASSD_INTPMR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) CLASSD_INTPMR_DEEMP_SHIFT, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) SOC_SINGLE("Mono Switch", CLASSD_INTPMR, CLASSD_INTPMR_MONO_SHIFT, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) SOC_SINGLE("Swap Switch", CLASSD_INTPMR, CLASSD_INTPMR_SWAP_SHIFT, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) SOC_ENUM("Mono Mode", classd_mono_mode_enum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) SOC_ENUM("EQ", classd_eqcfg_enum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const char * const pwm_type[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "Single ended", "Differential"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int atmel_classd_component_probe(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct atmel_classd *dd = snd_soc_card_get_drvdata(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) const struct atmel_classd_pdata *pdata = dd->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) mask = CLASSD_MR_PWMTYP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) val = pdata->pwm_type << CLASSD_MR_PWMTYP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) mask |= CLASSD_MR_NON_OVERLAP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (pdata->non_overlap_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) val |= (CLASSD_MR_NON_OVERLAP_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) << CLASSD_MR_NON_OVERLAP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) mask |= CLASSD_MR_NOVR_VAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) switch (pdata->non_overlap_time) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) val |= (CLASSD_MR_NOVR_VAL_5NS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) << CLASSD_MR_NOVR_VAL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) val |= (CLASSD_MR_NOVR_VAL_10NS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) << CLASSD_MR_NOVR_VAL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case 15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) val |= (CLASSD_MR_NOVR_VAL_15NS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) << CLASSD_MR_NOVR_VAL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case 20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) val |= (CLASSD_MR_NOVR_VAL_20NS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) << CLASSD_MR_NOVR_VAL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) val |= (CLASSD_MR_NOVR_VAL_10NS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) << CLASSD_MR_NOVR_VAL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev_warn(component->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "non-overlapping value %d is invalid, the default value 10 is specified\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) pdata->non_overlap_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) snd_soc_component_update_bits(component, CLASSD_MR, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_info(component->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "PWM modulation type is %s, non-overlapping is %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) pwm_type[pdata->pwm_type],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pdata->non_overlap_enable?"enabled":"disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int atmel_classd_component_resume(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct atmel_classd *dd = snd_soc_card_get_drvdata(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return regcache_sync(dd->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int atmel_classd_cpu_dai_mute_stream(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int mute, int direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct snd_soc_component *component = cpu_dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) mask = CLASSD_MR_LMUTE_MASK | CLASSD_MR_RMUTE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (mute)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) val = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) snd_soc_component_update_bits(component, CLASSD_MR, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CLASSD_GCLK_RATE_11M2896_MPY_8 (112896 * 100 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define CLASSD_GCLK_RATE_12M288_MPY_8 (12288 * 1000 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int dsp_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned long gclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) } const sample_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { 8000, CLASSD_INTPMR_FRAME_8K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_GCLK_RATE_12M288_MPY_8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { 16000, CLASSD_INTPMR_FRAME_16K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_GCLK_RATE_12M288_MPY_8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { 32000, CLASSD_INTPMR_FRAME_32K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_GCLK_RATE_12M288_MPY_8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { 48000, CLASSD_INTPMR_FRAME_48K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_GCLK_RATE_12M288_MPY_8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { 96000, CLASSD_INTPMR_FRAME_96K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_GCLK_RATE_12M288_MPY_8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { 22050, CLASSD_INTPMR_FRAME_22K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) CLASSD_INTPMR_DSP_CLK_FREQ_11M2896, CLASSD_GCLK_RATE_11M2896_MPY_8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { 44100, CLASSD_INTPMR_FRAME_44K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) CLASSD_INTPMR_DSP_CLK_FREQ_11M2896, CLASSD_GCLK_RATE_11M2896_MPY_8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { 88200, CLASSD_INTPMR_FRAME_88K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) CLASSD_INTPMR_DSP_CLK_FREQ_11M2896, CLASSD_GCLK_RATE_11M2896_MPY_8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) atmel_classd_cpu_dai_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct snd_soc_component *component = cpu_dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int i, best, best_val, cur_val, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) fs = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) best = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) best_val = abs(fs - sample_rates[0].rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Closest match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) cur_val = abs(fs - sample_rates[i].rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (cur_val < best_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) best = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) best_val = cur_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev_dbg(component->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) "Selected SAMPLE_RATE of %dHz, GCLK_RATE of %ldHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) sample_rates[best].rate, sample_rates[best].gclk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) clk_disable_unprepare(dd->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ret = clk_set_rate(dd->gclk, sample_rates[best].gclk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) mask = CLASSD_INTPMR_DSP_CLK_FREQ_MASK | CLASSD_INTPMR_FRAME_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) val = (sample_rates[best].dsp_clk << CLASSD_INTPMR_DSP_CLK_FREQ_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) | (sample_rates[best].sample_rate << CLASSD_INTPMR_FRAME_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) snd_soc_component_update_bits(component, CLASSD_INTPMR, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return clk_prepare_enable(dd->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) atmel_classd_cpu_dai_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) clk_disable_unprepare(dd->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int atmel_classd_cpu_dai_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct snd_soc_component *component = cpu_dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) snd_soc_component_update_bits(component, CLASSD_MR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) CLASSD_MR_LEN_MASK | CLASSD_MR_REN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) (CLASSD_MR_LEN_DIS << CLASSD_MR_LEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) |(CLASSD_MR_REN_DIS << CLASSD_MR_REN_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int atmel_classd_cpu_dai_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int cmd, struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct snd_soc_component *component = cpu_dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) mask = CLASSD_MR_LEN_MASK | CLASSD_MR_REN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) val = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) val = (CLASSD_MR_LEN_DIS << CLASSD_MR_LEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) | (CLASSD_MR_REN_DIS << CLASSD_MR_REN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) snd_soc_component_update_bits(component, CLASSD_MR, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const struct snd_soc_dai_ops atmel_classd_cpu_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .startup = atmel_classd_cpu_dai_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .shutdown = atmel_classd_cpu_dai_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .mute_stream = atmel_classd_cpu_dai_mute_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .hw_params = atmel_classd_cpu_dai_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .prepare = atmel_classd_cpu_dai_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .trigger = atmel_classd_cpu_dai_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .no_capture_mute = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static struct snd_soc_dai_driver atmel_classd_cpu_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .stream_name = "Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .rates = ATMEL_CLASSD_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .ops = &atmel_classd_cpu_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static const struct snd_soc_component_driver atmel_classd_cpu_dai_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .name = "atmel-classd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .probe = atmel_classd_component_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .resume = atmel_classd_component_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .controls = atmel_classd_snd_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .num_controls = ARRAY_SIZE(atmel_classd_snd_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .idle_bias_on = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .use_pmdown_time = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .endianness = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* ASoC sound card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static int atmel_classd_asoc_card_init(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct snd_soc_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct snd_soc_dai_link *dai_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct atmel_classd *dd = snd_soc_card_get_drvdata(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct snd_soc_dai_link_component *comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dai_link = devm_kzalloc(dev, sizeof(*dai_link), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (!dai_link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) comp = devm_kzalloc(dev, 3 * sizeof(*comp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (!comp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dai_link->cpus = &comp[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dai_link->codecs = &comp[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dai_link->platforms = &comp[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dai_link->num_cpus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dai_link->num_codecs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dai_link->num_platforms = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dai_link->name = "CLASSD";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dai_link->stream_name = "CLASSD PCM";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dai_link->codecs->dai_name = "snd-soc-dummy-dai";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dai_link->cpus->dai_name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dai_link->codecs->name = "snd-soc-dummy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dai_link->platforms->name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) card->dai_link = dai_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) card->num_links = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) card->name = dd->pdata->card_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) card->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* regmap configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const struct reg_default atmel_classd_reg_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) { CLASSD_INTPMR, 0x00301212 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define ATMEL_CLASSD_REG_MAX 0xE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static const struct regmap_config atmel_classd_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .max_register = ATMEL_CLASSD_REG_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .reg_defaults = atmel_classd_reg_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .num_reg_defaults = ARRAY_SIZE(atmel_classd_reg_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static int atmel_classd_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct atmel_classd *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) const struct atmel_classd_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct snd_soc_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) pdata = atmel_classd_dt_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (IS_ERR(pdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return PTR_ERR(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dd = devm_kzalloc(dev, sizeof(*dd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (!dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dd->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dd->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (dd->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return dd->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dd->pclk = devm_clk_get(dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (IS_ERR(dd->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ret = PTR_ERR(dd->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev_err(dev, "failed to get peripheral clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dd->gclk = devm_clk_get(dev, "gclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (IS_ERR(dd->gclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = PTR_ERR(dd->gclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev_err(dev, "failed to get GCK clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) io_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (IS_ERR(io_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return PTR_ERR(io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dd->phy_base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dd->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dd->regmap = devm_regmap_init_mmio(dev, io_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) &atmel_classd_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (IS_ERR(dd->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ret = PTR_ERR(dd->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_err(dev, "failed to init register map: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret = devm_snd_soc_register_component(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) &atmel_classd_cpu_dai_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) &atmel_classd_cpu_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dev_err(dev, "could not register CPU DAI: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ret = devm_snd_dmaengine_pcm_register(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) &atmel_classd_dmaengine_pcm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_err(dev, "could not register platform: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* register sound card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (!card) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) goto unregister_codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) snd_soc_card_set_drvdata(card, dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ret = atmel_classd_asoc_card_init(dev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) dev_err(dev, "failed to init sound card\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) goto unregister_codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ret = devm_snd_soc_register_card(dev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dev_err(dev, "failed to register sound card: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) goto unregister_codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) unregister_codec:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static int atmel_classd_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static struct platform_driver atmel_classd_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .name = "atmel-classd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .of_match_table = of_match_ptr(atmel_classd_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .pm = &snd_soc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .probe = atmel_classd_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .remove = atmel_classd_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) module_platform_driver(atmel_classd_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) MODULE_DESCRIPTION("Atmel ClassD driver under ALSA SoC architecture");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) MODULE_AUTHOR("Songjun Wu <songjun.wu@atmel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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