^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AMD ALSA SoC PCM Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2016 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "chip_offset_byte.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define I2S_SP_INSTANCE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define I2S_BT_INSTANCE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TDM_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TDM_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ACP3x_DEVS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ACP3x_PHY_BASE_ADDRESS 0x1240000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ACP3x_I2S_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ACP3x_REG_START 0x1240000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ACP3x_REG_END 0x1250200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ACP3x_I2STDM_REG_START 0x1242400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ACP3x_I2STDM_REG_END 0x1242410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ACP3x_BT_TDM_REG_START 0x1242800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ACP3x_BT_TDM_REG_END 0x1242810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define I2S_MODE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define I2S_RX_THRESHOLD 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define I2S_TX_THRESHOLD 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BT_TX_THRESHOLD 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BT_RX_THRESHOLD 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ACP_ERR_INTR_MASK 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ACP3x_POWER_ON 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ACP3x_POWER_ON_IN_PROGRESS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ACP3x_POWER_OFF 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ACP3x_POWER_OFF_IN_PROGRESS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ACP3x_SOFT_RESET__SoftResetAudDone_MASK 0x00010001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ACP_SRAM_PTE_OFFSET 0x02050000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ACP_SRAM_SP_PB_PTE_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ACP_SRAM_BT_PB_PTE_OFFSET 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ACP_SRAM_BT_CP_PTE_OFFSET 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PAGE_SIZE_4K_ENABLE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I2S_SP_TX_MEM_WINDOW_START 0x4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I2S_SP_RX_MEM_WINDOW_START 0x4020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define I2S_BT_TX_MEM_WINDOW_START 0x4040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define I2S_BT_RX_MEM_WINDOW_START 0x4060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SP_PB_FIFO_ADDR_OFFSET 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SP_CAPT_FIFO_ADDR_OFFSET 0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BT_PB_FIFO_ADDR_OFFSET 0x900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BT_CAPT_FIFO_ADDR_OFFSET 0xB00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PLAYBACK_MIN_NUM_PERIODS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PLAYBACK_MAX_NUM_PERIODS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PLAYBACK_MAX_PERIOD_SIZE 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PLAYBACK_MIN_PERIOD_SIZE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CAPTURE_MIN_NUM_PERIODS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CAPTURE_MAX_NUM_PERIODS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CAPTURE_MAX_PERIOD_SIZE 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CAPTURE_MIN_PERIOD_SIZE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MIN_BUFFER MAX_BUFFER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FIFO_SIZE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DMA_SIZE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define FRM_LEN 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SLOT_WIDTH_8 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SLOT_WIDTH_16 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SLOT_WIDTH_24 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SLOT_WIDTH_32 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ACP_PGFSM_STATUS_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ACP_POWERED_ON 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ACP_POWER_ON_IN_PROGRESS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ACP_POWERED_OFF 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ACP_POWER_OFF_IN_PROGRESS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ACP3x_ITER_IRER_SAMP_LEN_MASK 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct acp3x_platform_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u16 play_i2s_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u16 cap_i2s_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u16 capture_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct i2s_dev_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) bool tdm_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int i2s_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u16 i2s_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 tdm_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 substream_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) void __iomem *acp3x_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct snd_pcm_substream *play_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct snd_pcm_substream *capture_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct snd_pcm_substream *i2ssp_play_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct snd_pcm_substream *i2ssp_capture_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct i2s_stream_instance {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u16 num_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u16 i2s_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 capture_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u16 direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u16 channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 xfer_resolution;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u64 bytescount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void __iomem *acp3x_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline u32 rv_readl(void __iomem *base_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return readl(base_addr - ACP3x_PHY_BASE_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline void rv_writel(u32 val, void __iomem *base_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) writel(val, base_addr - ACP3x_PHY_BASE_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static inline u64 acp_get_byte_count(struct i2s_stream_instance *rtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u64 byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) switch (rtd->i2s_instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) case I2S_BT_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) byte_count = rv_readl(rtd->acp3x_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) mmACP_BT_TX_LINEARPOSITIONCNTR_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) byte_count |= rv_readl(rtd->acp3x_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) mmACP_BT_TX_LINEARPOSITIONCNTR_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case I2S_SP_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) byte_count = rv_readl(rtd->acp3x_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) mmACP_I2S_TX_LINEARPOSITIONCNTR_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) byte_count |= rv_readl(rtd->acp3x_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) mmACP_I2S_TX_LINEARPOSITIONCNTR_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) switch (rtd->i2s_instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case I2S_BT_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) byte_count = rv_readl(rtd->acp3x_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mmACP_BT_RX_LINEARPOSITIONCNTR_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) byte_count |= rv_readl(rtd->acp3x_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) mmACP_BT_RX_LINEARPOSITIONCNTR_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case I2S_SP_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) byte_count = rv_readl(rtd->acp3x_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) mmACP_I2S_RX_LINEARPOSITIONCNTR_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) byte_count |= rv_readl(rtd->acp3x_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) mmACP_I2S_RX_LINEARPOSITIONCNTR_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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