^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // AMD ALSA SoC PCM Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //Copyright 2016 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "acp3x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DRV_NAME "acp3x_rv_i2s_dma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const struct snd_pcm_hardware acp3x_pcm_hardware_playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .info = SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) SNDRV_PCM_INFO_BATCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .rates = SNDRV_PCM_RATE_8000_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .periods_min = PLAYBACK_MIN_NUM_PERIODS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .periods_max = PLAYBACK_MAX_NUM_PERIODS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const struct snd_pcm_hardware acp3x_pcm_hardware_capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .info = SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SNDRV_PCM_INFO_BATCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .rates = SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .periods_min = CAPTURE_MIN_NUM_PERIODS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .periods_max = CAPTURE_MAX_NUM_PERIODS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct i2s_dev_data *rv_i2s_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u16 play_flag, cap_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) rv_i2s_data = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (!rv_i2s_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) play_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) cap_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) val = rv_readl(rv_i2s_data->acp3x_base + mmACP_EXTERNAL_INTR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if ((val & BIT(BT_TX_THRESHOLD)) && rv_i2s_data->play_stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) rv_writel(BIT(BT_TX_THRESHOLD), rv_i2s_data->acp3x_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mmACP_EXTERNAL_INTR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) snd_pcm_period_elapsed(rv_i2s_data->play_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) play_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if ((val & BIT(I2S_TX_THRESHOLD)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) rv_i2s_data->i2ssp_play_stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) rv_writel(BIT(I2S_TX_THRESHOLD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) rv_i2s_data->acp3x_base + mmACP_EXTERNAL_INTR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) snd_pcm_period_elapsed(rv_i2s_data->i2ssp_play_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) play_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if ((val & BIT(BT_RX_THRESHOLD)) && rv_i2s_data->capture_stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) rv_writel(BIT(BT_RX_THRESHOLD), rv_i2s_data->acp3x_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mmACP_EXTERNAL_INTR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) snd_pcm_period_elapsed(rv_i2s_data->capture_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) cap_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if ((val & BIT(I2S_RX_THRESHOLD)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) rv_i2s_data->i2ssp_capture_stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) rv_writel(BIT(I2S_RX_THRESHOLD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) rv_i2s_data->acp3x_base + mmACP_EXTERNAL_INTR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) snd_pcm_period_elapsed(rv_i2s_data->i2ssp_capture_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) cap_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (play_flag | cap_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void config_acp3x_dma(struct i2s_stream_instance *rtd, int direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u16 page_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 low, high, val, acp_fifo_addr, reg_fifo_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 reg_dma_size, reg_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) addr = rtd->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) switch (rtd->i2s_instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case I2S_BT_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) val = ACP_SRAM_BT_PB_PTE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case I2S_SP_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) val = ACP_SRAM_SP_PB_PTE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) switch (rtd->i2s_instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case I2S_BT_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) val = ACP_SRAM_BT_CP_PTE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case I2S_SP_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) val = ACP_SRAM_SP_CP_PTE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Group Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) rv_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp3x_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mmACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) rv_writel(PAGE_SIZE_4K_ENABLE, rtd->acp3x_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Load the low address of page int ACP SRAM through SRBM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) low = lower_32_bits(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) high = upper_32_bits(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) rv_writel(low, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) high |= BIT(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) rv_writel(high, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Move to next physically contiguos page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) val += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) addr += PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) switch (rtd->i2s_instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) case I2S_BT_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) reg_dma_size = mmACP_BT_TX_DMA_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) BT_PB_FIFO_ADDR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) reg_fifo_addr = mmACP_BT_TX_FIFOADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) reg_fifo_size = mmACP_BT_TX_FIFOSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) rv_writel(I2S_BT_TX_MEM_WINDOW_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) rtd->acp3x_base + mmACP_BT_TX_RINGBUFADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case I2S_SP_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) reg_dma_size = mmACP_I2S_TX_DMA_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) SP_PB_FIFO_ADDR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) reg_fifo_addr = mmACP_I2S_TX_FIFOADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) reg_fifo_size = mmACP_I2S_TX_FIFOSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) rv_writel(I2S_SP_TX_MEM_WINDOW_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) rtd->acp3x_base + mmACP_I2S_TX_RINGBUFADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) switch (rtd->i2s_instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) case I2S_BT_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) reg_dma_size = mmACP_BT_RX_DMA_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) BT_CAPT_FIFO_ADDR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) reg_fifo_addr = mmACP_BT_RX_FIFOADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) reg_fifo_size = mmACP_BT_RX_FIFOSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) rv_writel(I2S_BT_RX_MEM_WINDOW_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) rtd->acp3x_base + mmACP_BT_RX_RINGBUFADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case I2S_SP_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) reg_dma_size = mmACP_I2S_RX_DMA_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) SP_CAPT_FIFO_ADDR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) reg_fifo_addr = mmACP_I2S_RX_FIFOADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) reg_fifo_size = mmACP_I2S_RX_FIFOSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) rv_writel(I2S_SP_RX_MEM_WINDOW_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) rtd->acp3x_base + mmACP_I2S_RX_RINGBUFADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) rv_writel(DMA_SIZE, rtd->acp3x_base + reg_dma_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) rv_writel(acp_fifo_addr, rtd->acp3x_base + reg_fifo_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) rv_writel(FIFO_SIZE, rtd->acp3x_base + reg_fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) rv_writel(BIT(I2S_RX_THRESHOLD) | BIT(BT_RX_THRESHOLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) | BIT(I2S_TX_THRESHOLD) | BIT(BT_TX_THRESHOLD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) rtd->acp3x_base + mmACP_EXTERNAL_INTR_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int acp3x_dma_open(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct snd_pcm_runtime *runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct snd_soc_pcm_runtime *prtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct i2s_dev_data *adata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct i2s_stream_instance *i2s_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) prtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) adata = dev_get_drvdata(component->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) i2s_data = kzalloc(sizeof(*i2s_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (!i2s_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) runtime->hw = acp3x_pcm_hardware_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) runtime->hw = acp3x_pcm_hardware_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret = snd_pcm_hw_constraint_integer(runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) SNDRV_PCM_HW_PARAM_PERIODS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_err(component->dev, "set integer constraint failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) kfree(i2s_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) i2s_data->acp3x_base = adata->acp3x_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) runtime->private_data = i2s_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int acp3x_dma_hw_params(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct i2s_stream_instance *rtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct snd_soc_pcm_runtime *prtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct snd_soc_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct acp3x_platform_info *pinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct i2s_dev_data *adata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) prtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) card = prtd->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pinfo = snd_soc_card_get_drvdata(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) adata = dev_get_drvdata(component->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) rtd = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (!rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (pinfo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) rtd->i2s_instance = pinfo->play_i2s_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) switch (rtd->i2s_instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case I2S_BT_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) adata->play_stream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case I2S_SP_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) adata->i2ssp_play_stream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) rtd->i2s_instance = pinfo->cap_i2s_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) switch (rtd->i2s_instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case I2S_BT_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) adata->capture_stream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case I2S_SP_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) adata->i2ssp_capture_stream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) pr_err("pinfo failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) size = params_buffer_bytes(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) rtd->dma_addr = substream->runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) config_acp3x_dma(rtd, substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static snd_pcm_uframes_t acp3x_dma_pointer(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct i2s_stream_instance *rtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 buffersize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u64 bytescount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) rtd = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) buffersize = frames_to_bytes(substream->runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) substream->runtime->buffer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) bytescount = acp_get_byte_count(rtd, substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (bytescount > rtd->bytescount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) bytescount -= rtd->bytescount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) pos = do_div(bytescount, buffersize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return bytes_to_frames(substream->runtime, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int acp3x_dma_new(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct snd_soc_pcm_runtime *rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct device *parent = component->dev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) parent, MIN_BUFFER, MAX_BUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int acp3x_dma_mmap(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct vm_area_struct *vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return snd_pcm_lib_default_mmap(substream, vma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int acp3x_dma_close(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct snd_soc_pcm_runtime *prtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct i2s_dev_data *adata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct i2s_stream_instance *ins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) prtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) adata = dev_get_drvdata(component->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ins = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!ins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) switch (ins->i2s_instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case I2S_BT_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) adata->play_stream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case I2S_SP_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) adata->i2ssp_play_stream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) switch (ins->i2s_instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case I2S_BT_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) adata->capture_stream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case I2S_SP_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) adata->i2ssp_capture_stream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const struct snd_soc_component_driver acp3x_i2s_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .open = acp3x_dma_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .close = acp3x_dma_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .hw_params = acp3x_dma_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .pointer = acp3x_dma_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .mmap = acp3x_dma_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .pcm_construct = acp3x_dma_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int acp3x_audio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct i2s_dev_data *adata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned int irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (!pdev->dev.platform_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dev_err(&pdev->dev, "platform_data not retrieved\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) irqflags = *((unsigned int *)(pdev->dev.platform_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) adata = devm_kzalloc(&pdev->dev, sizeof(*adata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (!adata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) adata->acp3x_base = devm_ioremap(&pdev->dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (!adata->acp3x_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) adata->i2s_irq = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dev_set_drvdata(&pdev->dev, adata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) status = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) &acp3x_i2s_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_err(&pdev->dev, "Fail to register acp i2s component\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) status = devm_request_irq(&pdev->dev, adata->i2s_irq, i2s_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) irqflags, "ACP3x_I2S_IRQ", adata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dev_err(&pdev->dev, "ACP3x I2S IRQ request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) pm_runtime_allow(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int acp3x_audio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int acp3x_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct i2s_dev_data *adata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u32 val, reg_val, frmt_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) reg_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) frmt_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) adata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (adata->play_stream && adata->play_stream->runtime) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct i2s_stream_instance *rtd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) adata->play_stream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) config_acp3x_dma(rtd, SNDRV_PCM_STREAM_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) switch (rtd->i2s_instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case I2S_BT_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) reg_val = mmACP_BTTDM_ITER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) frmt_val = mmACP_BTTDM_TXFRMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case I2S_SP_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) reg_val = mmACP_I2STDM_ITER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) frmt_val = mmACP_I2STDM_TXFRMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) rv_writel((rtd->xfer_resolution << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) rtd->acp3x_base + reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (adata->capture_stream && adata->capture_stream->runtime) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct i2s_stream_instance *rtd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) adata->capture_stream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) config_acp3x_dma(rtd, SNDRV_PCM_STREAM_CAPTURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) switch (rtd->i2s_instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) case I2S_BT_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) reg_val = mmACP_BTTDM_IRER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) frmt_val = mmACP_BTTDM_RXFRMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case I2S_SP_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) reg_val = mmACP_I2STDM_IRER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) frmt_val = mmACP_I2STDM_RXFRMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) rv_writel((rtd->xfer_resolution << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) rtd->acp3x_base + reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (adata->tdm_mode == TDM_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) rv_writel(adata->tdm_fmt, adata->acp3x_base + frmt_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) val = rv_readl(adata->acp3x_base + reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) rv_writel(val | 0x2, adata->acp3x_base + reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static int acp3x_pcm_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct i2s_dev_data *adata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) adata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) rv_writel(0, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int acp3x_pcm_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct i2s_dev_data *adata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) adata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static const struct dev_pm_ops acp3x_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .runtime_suspend = acp3x_pcm_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .runtime_resume = acp3x_pcm_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .resume = acp3x_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static struct platform_driver acp3x_dma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .probe = acp3x_audio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .remove = acp3x_audio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .name = "acp3x_rv_i2s_dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .pm = &acp3x_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) module_platform_driver(acp3x_dma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MODULE_AUTHOR("Vishnuvardhanrao.Ravulapati@amd.com");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MODULE_DESCRIPTION("AMD ACP 3.x PCM Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) MODULE_ALIAS("platform:"DRV_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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