^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __ACP_HW_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __ACP_HW_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include "include/acp_2_2_d.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include "include/acp_2_2_sh_mask.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define ACP_PAGE_SIZE_4K_ENABLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define ACP_PLAYBACK_PTE_OFFSET 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ACP_CAPTURE_PTE_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Playback and Capture Offset for Stoney */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ACP_ST_PLAYBACK_PTE_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ACP_ST_CAPTURE_PTE_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ACP_ST_BT_PLAYBACK_PTE_OFFSET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ACP_ST_BT_CAPTURE_PTE_OFFSET 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ACP_GARLIC_CNTL_DEFAULT 0x00000FB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ACP_ONION_CNTL_DEFAULT 0x00000FB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ACP_PHYSICAL_BASE 0x14000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * In case of I2S SP controller instance, Stoney uses SRAM bank 1 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * playback and SRAM Bank 2 for capture where as in case of BT I2S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Instance, Stoney uses SRAM Bank 3 for playback & SRAM Bank 4 will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * be used for capture. Carrizo uses I2S SP controller instance. SRAM Banks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 1, 2, 3, 4 will be used for playback & SRAM Banks 5, 6, 7, 8 will be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * for capture scenario.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ACP_SRAM_BANK_1_ADDRESS 0x4002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ACP_SRAM_BANK_2_ADDRESS 0x4004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ACP_SRAM_BANK_3_ADDRESS 0x4006000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ACP_SRAM_BANK_4_ADDRESS 0x4008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ACP_SRAM_BANK_5_ADDRESS 0x400A000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ACP_DMA_RESET_TIME 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ACP_DMA_COMPLETE_TIME_OUT_VALUE 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ACP_SRAM_BASE_ADDRESS 0x4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ACP_DAGB_GRP_SRAM_BASE_ADDRESS 0x4001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ACP_INTERNAL_APERTURE_WINDOW_4_ADDRESS 0x01800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TO_ACP_I2S_1 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TO_ACP_I2S_2 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TO_BLUETOOTH 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define FROM_ACP_I2S_1 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define FROM_ACP_I2S_2 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define FROM_BLUETOOTH 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define I2S_SP_INSTANCE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define I2S_BT_INSTANCE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CAP_CHANNEL0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CAP_CHANNEL1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ACP_TILE_ON_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ACP_TILE_OFF_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ACP_TILE_ON_RETAIN_REG_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ACP_TILE_OFF_RETAIN_REG_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ACP_TILE_P1_MASK 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ACP_TILE_P2_MASK 0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ACP_TILE_DSP0_MASK 0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ACP_TILE_DSP1_MASK 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ACP_TILE_DSP2_MASK 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Playback DMA channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SYSRAM_TO_ACP_CH_NUM 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ACP_TO_I2S_DMA_CH_NUM 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Capture DMA channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define I2S_TO_ACP_DMA_CH_NUM 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ACP_TO_SYSRAM_CH_NUM 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Playback DMA Channels for I2S BT instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Capture DMA Channels for I2S BT Instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define NUM_DSCRS_PER_CHANNEL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PLAYBACK_START_DMA_DESCR_CH12 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PLAYBACK_END_DMA_DESCR_CH12 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PLAYBACK_START_DMA_DESCR_CH13 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PLAYBACK_END_DMA_DESCR_CH13 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CAPTURE_START_DMA_DESCR_CH14 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CAPTURE_END_DMA_DESCR_CH14 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CAPTURE_START_DMA_DESCR_CH15 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CAPTURE_END_DMA_DESCR_CH15 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* I2S BT Instance DMA Descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PLAYBACK_START_DMA_DESCR_CH8 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PLAYBACK_END_DMA_DESCR_CH8 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PLAYBACK_START_DMA_DESCR_CH9 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PLAYBACK_END_DMA_DESCR_CH9 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CAPTURE_START_DMA_DESCR_CH10 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CAPTURE_END_DMA_DESCR_CH10 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CAPTURE_START_DMA_DESCR_CH11 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CAPTURE_END_DMA_DESCR_CH11 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define mmACP_I2S_16BIT_RESOLUTION_EN 0x5209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ACP_I2S_MIC_16BIT_RESOLUTION_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ACP_I2S_SP_16BIT_RESOLUTION_EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ACP_I2S_BT_16BIT_RESOLUTION_EN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ACP_BT_UART_PAD_SELECT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) enum acp_dma_priority_level {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* 0x0 Specifies the DMA channel is given normal priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ACP_DMA_PRIORITY_LEVEL_NORMAL = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* 0x1 Specifies the DMA channel is given high priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ACP_DMA_PRIORITY_LEVEL_HIGH = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ACP_DMA_PRIORITY_LEVEL_FORCESIZE = 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct audio_substream_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u16 num_of_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u16 i2s_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u16 capture_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u16 direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u16 ch1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u16 ch2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u16 destination;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u16 dma_dscr_idx_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u16 dma_dscr_idx_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 pte_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 sram_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 byte_cnt_high_reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 byte_cnt_low_reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 dma_curr_dscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) uint64_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u64 bytescount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) void __iomem *acp_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct audio_drv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct snd_pcm_substream *play_i2ssp_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct snd_pcm_substream *capture_i2ssp_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct snd_pcm_substream *play_i2sbt_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct snd_pcm_substream *capture_i2sbt_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) void __iomem *acp_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 asic_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * this structure used for platform data transfer between machine driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * and dma driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct acp_platform_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u16 play_i2s_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u16 cap_i2s_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u16 capture_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) union acp_dma_count {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) } bcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u64 bytescount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ACP_TILE_P1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ACP_TILE_P2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ACP_TILE_DSP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ACP_TILE_DSP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ACP_TILE_DSP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM = 0x9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ACP_DMA_ATTR_FORCE_SIZE = 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) typedef struct acp_dma_dscr_transfer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Specifies the source memory location for the DMA data transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * Specifies the destination memory location to where the data will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * be transferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Specifies the number of bytes need to be transferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * from source to destination memory.Transfer direction & IOC enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 xfer_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Reserved for future use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) } acp_dma_dscr_transfer_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #endif /*__ACP_HW_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags