^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AMD ALSA SoC PCM Driver for ACP 2.x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2014-2015 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <drm/amd_asic_type.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "acp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DRV_NAME "acp_audio_dma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PLAYBACK_MIN_NUM_PERIODS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PLAYBACK_MAX_NUM_PERIODS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PLAYBACK_MAX_PERIOD_SIZE 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PLAYBACK_MIN_PERIOD_SIZE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CAPTURE_MIN_NUM_PERIODS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CAPTURE_MAX_NUM_PERIODS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CAPTURE_MAX_PERIOD_SIZE 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CAPTURE_MIN_PERIOD_SIZE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MIN_BUFFER MAX_BUFFER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ST_PLAYBACK_MAX_PERIOD_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ST_CAPTURE_MAX_PERIOD_SIZE ST_PLAYBACK_MAX_PERIOD_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ST_MIN_BUFFER ST_MAX_BUFFER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRV_NAME "acp_audio_dma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) bool bt_uart_enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) EXPORT_SYMBOL(bt_uart_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const struct snd_pcm_hardware acp_pcm_hardware_playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .info = SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .rates = SNDRV_PCM_RATE_8000_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .periods_min = PLAYBACK_MIN_NUM_PERIODS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .periods_max = PLAYBACK_MAX_NUM_PERIODS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const struct snd_pcm_hardware acp_pcm_hardware_capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .info = SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .rates = SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .periods_min = CAPTURE_MIN_NUM_PERIODS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .periods_max = CAPTURE_MAX_NUM_PERIODS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .info = SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .rates = SNDRV_PCM_RATE_8000_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .buffer_bytes_max = ST_MAX_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .periods_min = PLAYBACK_MIN_NUM_PERIODS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .periods_max = PLAYBACK_MAX_NUM_PERIODS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .info = SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .rates = SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .buffer_bytes_max = ST_MAX_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .periods_min = CAPTURE_MIN_NUM_PERIODS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .periods_max = CAPTURE_MAX_NUM_PERIODS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return readl(acp_mmio + (reg * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) writel(val, acp_mmio + (reg * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * Configure a given dma channel parameters - enable/disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * number of descriptors, priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u16 dscr_strt_idx, u16 num_dscrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) enum acp_dma_priority_level priority_level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 dma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* disable the channel run field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* program a DMA channel with first descriptor to be processed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) & dscr_strt_idx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * program a DMA channel with the number of descriptors to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * processed in the transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* set DMA channel priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Initialize a dma descriptor in SRAM based on descritor information passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void config_dma_descriptor_in_sram(void __iomem *acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u16 descr_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) acp_dma_dscr_transfer_t *descr_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 sram_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* program the source base address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* program the destination base address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* program the number of bytes to be transferred for this descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void pre_config_reset(void __iomem *acp_mmio, u16 ch_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 dma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* clear the reset bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* check the reset bit before programming configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ret = readl_poll_timeout(acp_mmio + ((mmACP_DMA_CNTL_0 + ch_num) * 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dma_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) !(dma_ctrl & ACP_DMA_CNTL_0__DMAChRst_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 100, ACP_DMA_RESET_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pr_err("Failed to clear reset of channel : %d\n", ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Initialize the DMA descriptor information for transfer between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * system memory <-> ACP SRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 size, int direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 pte_offset, u16 ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 sram_bank, u16 dma_dscr_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 asic_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u16 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dmadscr[i].xfer_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dma_dscr_idx = dma_dscr_idx + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dmadscr[i].dest = sram_bank + (i * (size / 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) + (pte_offset * SZ_4K) + (i * (size / 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) switch (asic_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case CHIP_STONEY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dmadscr[i].xfer_val |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) (ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) (size / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dmadscr[i].xfer_val |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) (ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) (size / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dma_dscr_idx = dma_dscr_idx + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dmadscr[i].src = sram_bank + (i * (size / 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dmadscr[i].dest =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) (pte_offset * SZ_4K) + (i * (size / 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) switch (asic_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case CHIP_STONEY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dmadscr[i].xfer_val |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) (ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) (size / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dmadscr[i].xfer_val |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) (ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) (size / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) &dmadscr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pre_config_reset(acp_mmio, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) config_acp_dma_channel(acp_mmio, ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dma_dscr_idx - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) NUM_DSCRS_PER_CHANNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ACP_DMA_PRIORITY_LEVEL_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * Initialize the DMA descriptor information for transfer between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * ACP SRAM <-> I2S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int direction, u32 sram_bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u16 destination, u16 ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u16 dma_dscr_idx, u32 asic_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u16 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dmadscr[i].xfer_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dma_dscr_idx = dma_dscr_idx + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dmadscr[i].src = sram_bank + (i * (size / 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* dmadscr[i].dest is unused by hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dmadscr[i].dest = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dmadscr[i].xfer_val |= BIT(22) | (destination << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) (size / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dma_dscr_idx = dma_dscr_idx + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* dmadscr[i].src is unused by hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dmadscr[i].src = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dmadscr[i].dest =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) sram_bank + (i * (size / 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dmadscr[i].xfer_val |= BIT(22) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) (destination << 16) | (size / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) &dmadscr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) pre_config_reset(acp_mmio, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Configure the DMA channel with the above descriptore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) NUM_DSCRS_PER_CHANNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ACP_DMA_PRIORITY_LEVEL_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Create page table entries in ACP SRAM for the allocated memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void acp_pte_config(void __iomem *acp_mmio, dma_addr_t addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u16 num_of_pages, u32 pte_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u16 page_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) for (page_idx = 0; page_idx < (num_of_pages); page_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Load the low address of page int ACP SRAM through SRBM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) acp_reg_write((offset + (page_idx * 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) low = lower_32_bits(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) high = upper_32_bits(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Load the High address of page int ACP SRAM through SRBM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) acp_reg_write((offset + (page_idx * 8) + 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* page enable in ACP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) high |= BIT(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Move to next physically contiguos page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) addr += PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static void config_acp_dma(void __iomem *acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct audio_substream_data *rtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 asic_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u16 ch_acp_sysmem, ch_acp_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) acp_pte_config(acp_mmio, rtd->dma_addr, rtd->num_of_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) rtd->pte_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ch_acp_sysmem = rtd->ch1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ch_acp_i2s = rtd->ch2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ch_acp_i2s = rtd->ch1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ch_acp_sysmem = rtd->ch2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Configure System memory <-> ACP SRAM DMA descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) rtd->direction, rtd->pte_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ch_acp_sysmem, rtd->sram_bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) rtd->dma_dscr_idx_1, asic_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Configure ACP SRAM <-> I2S DMA descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) rtd->direction, rtd->sram_bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) rtd->destination, ch_acp_i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) rtd->dma_dscr_idx_2, asic_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void acp_dma_cap_channel_enable(void __iomem *acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u16 cap_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 val, ch_reg, imr_reg, res_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) switch (cap_channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case CAP_CHANNEL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ch_reg = mmACP_I2SMICSP_RER1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) res_reg = mmACP_I2SMICSP_RCR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) imr_reg = mmACP_I2SMICSP_IMR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) case CAP_CHANNEL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ch_reg = mmACP_I2SMICSP_RER0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) res_reg = mmACP_I2SMICSP_RCR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) imr_reg = mmACP_I2SMICSP_IMR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) val = acp_reg_read(acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) mmACP_I2S_16BIT_RESOLUTION_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (val & ACP_I2S_MIC_16BIT_RESOLUTION_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) acp_reg_write(0x0, acp_mmio, ch_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Set 16bit resolution on capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) acp_reg_write(0x2, acp_mmio, res_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) val = acp_reg_read(acp_mmio, imr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) acp_reg_write(val, acp_mmio, imr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) acp_reg_write(0x1, acp_mmio, ch_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static void acp_dma_cap_channel_disable(void __iomem *acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u16 cap_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 val, ch_reg, imr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) switch (cap_channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case CAP_CHANNEL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) imr_reg = mmACP_I2SMICSP_IMR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ch_reg = mmACP_I2SMICSP_RER1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case CAP_CHANNEL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) imr_reg = mmACP_I2SMICSP_IMR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ch_reg = mmACP_I2SMICSP_RER0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) val = acp_reg_read(acp_mmio, imr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) acp_reg_write(val, acp_mmio, imr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) acp_reg_write(0x0, acp_mmio, ch_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Start a given DMA channel transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num, bool is_circular)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u32 dma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* read the dma control register and disable the channel run field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Invalidating the DAGB cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * configure the DMA channel and start the DMA transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * set dmachrun bit to start the transfer and enable the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * interrupt on completion of the dma transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) switch (ch_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case ACP_TO_I2S_DMA_CH_NUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case I2S_TO_ACP_DMA_CH_NUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* enable for ACP to SRAM DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (is_circular == true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Stop a given DMA channel transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u32 dma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u32 dma_ch_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u32 count = ACP_DMA_RESET_TIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * clear the dma control register fields before writing zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * in reset bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (dma_ch_sts & BIT(ch_num)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * set the reset bit for this channel to stop the dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* check the channel status bit for some time and return the status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) while (true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (!(dma_ch_sts & BIT(ch_num))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * clear the reset flag after successfully stopping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * the dma transfer and break from the loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) + ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (--count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) pr_err("Failed to stop ACP DMA channel : %d\n", ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) bool power_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u32 val, req_reg, sts_reg, sts_reg_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u32 loops = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (bank < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) sts_reg_mask = 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) bank -= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) sts_reg_mask = 0x0000FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) val = acp_reg_read(acp_mmio, req_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (val & (1 << bank)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* bank is in off state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (power_on == true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* request to on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) val &= ~(1 << bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* request to off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* bank is in on state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (power_on == false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* request to off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) val |= 1 << bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* request to on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) acp_reg_write(val, acp_mmio, req_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (!loops--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) pr_err("ACP SRAM bank %d state change failed\n", bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Initialize and bring ACP hardware to default state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int acp_init(void __iomem *acp_mmio, u32 asic_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u16 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u32 val, count, sram_pte_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Assert Soft reset of ACP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) val |= ACP_SOFT_RESET__SoftResetAud_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) while (true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (--count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) pr_err("Failed to reset ACP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* Enable clock to ACP and wait until the clock is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) val = acp_reg_read(acp_mmio, mmACP_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) val = val | ACP_CONTROL__ClkEn_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) acp_reg_write(val, acp_mmio, mmACP_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) count = ACP_CLOCK_EN_TIME_OUT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) while (true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) val = acp_reg_read(acp_mmio, mmACP_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (val & (u32)0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (--count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) pr_err("Failed to reset ACP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* Deassert the SOFT RESET flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* For BT instance change pins from UART to BT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (!bt_uart_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) val |= ACP_BT_UART_PAD_SELECT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* initiailize Onion control DAGB register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) mmACP_AXI2DAGB_ONION_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* initiailize Garlic control DAGB registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) mmACP_AXI2DAGB_GARLIC_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) mmACP_DAGB_PAGE_SIZE_GRP_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) mmACP_DMA_DESC_BASE_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) acp_mmio, mmACP_EXTERNAL_INTR_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * When ACP_TILE_P1 is turned on, all SRAM banks get turned on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * Now, turn off all of them. This can't be done in 'poweron' of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * ACP pm domain, as this requires ACP to be initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * For Stoney, Memory gating is disabled,i.e SRAM Banks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * won't be turned off. The default state for SRAM banks is ON.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * Setting SRAM bank state code skipped for STONEY platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (asic_type != CHIP_STONEY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) for (bank = 1; bank < 48; bank++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) acp_set_sram_bank_state(acp_mmio, bank, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Deinitialize ACP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static int acp_deinit(void __iomem *acp_mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Assert Soft reset of ACP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) val |= ACP_SOFT_RESET__SoftResetAud_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) while (true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (--count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) pr_err("Failed to reset ACP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* Disable ACP clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) val = acp_reg_read(acp_mmio, mmACP_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) val &= ~ACP_CONTROL__ClkEn_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) acp_reg_write(val, acp_mmio, mmACP_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) count = ACP_CLOCK_EN_TIME_OUT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) while (true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) val = acp_reg_read(acp_mmio, mmACP_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (!(val & (u32)0x1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (--count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) pr_err("Failed to reset ACP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* ACP DMA irq handler routine for playback, capture usecases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static irqreturn_t dma_irq_handler(int irq, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) u16 dscr_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) u32 intr_flag, ext_intr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct audio_drv_data *irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) void __iomem *acp_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct device *dev = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) bool valid_irq = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) irq_data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) acp_mmio = irq_data->acp_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) intr_flag = (((ext_intr_status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) valid_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) snd_pcm_period_elapsed(irq_data->play_i2ssp_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) acp_mmio, mmACP_EXTERNAL_INTR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if ((intr_flag & BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) valid_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) snd_pcm_period_elapsed(irq_data->play_i2sbt_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) acp_reg_write((intr_flag &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) acp_mmio, mmACP_EXTERNAL_INTR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) valid_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_14) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) CAPTURE_START_DMA_DESCR_CH15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dscr_idx = CAPTURE_END_DMA_DESCR_CH14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dscr_idx = CAPTURE_START_DMA_DESCR_CH14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) acp_mmio, mmACP_EXTERNAL_INTR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) valid_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_10) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) CAPTURE_START_DMA_DESCR_CH11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dscr_idx = CAPTURE_END_DMA_DESCR_CH10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) dscr_idx = CAPTURE_START_DMA_DESCR_CH10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) config_acp_dma_channel(acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) dscr_idx, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) acp_dma_start(acp_mmio, ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) acp_reg_write((intr_flag &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) acp_mmio, mmACP_EXTERNAL_INTR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (valid_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static int acp_dma_open(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u16 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct audio_drv_data *intr_data = dev_get_drvdata(component->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct audio_substream_data *adata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (!adata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) switch (intr_data->asic_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) case CHIP_STONEY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) runtime->hw = acp_st_pcm_hardware_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) runtime->hw = acp_pcm_hardware_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) switch (intr_data->asic_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) case CHIP_STONEY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) runtime->hw = acp_st_pcm_hardware_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) runtime->hw = acp_pcm_hardware_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = snd_pcm_hw_constraint_integer(runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) SNDRV_PCM_HW_PARAM_PERIODS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) dev_err(component->dev, "set integer constraint failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) kfree(adata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) adata->acp_mmio = intr_data->acp_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) runtime->private_data = adata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * Enable ACP irq, when neither playback or capture streams are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * active by the time when a new stream is being opened.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * This enablement is not required for another stream, if current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * stream is not closed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) !intr_data->play_i2sbt_stream && !intr_data->capture_i2sbt_stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * For Stoney, Memory gating is disabled,i.e SRAM Banks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * won't be turned off. The default state for SRAM banks is ON.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * Setting SRAM bank state code skipped for STONEY platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (intr_data->asic_type != CHIP_STONEY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) for (bank = 1; bank <= 4; bank++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) acp_set_sram_bank_state(intr_data->acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) bank, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (intr_data->asic_type != CHIP_STONEY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) for (bank = 5; bank <= 8; bank++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) acp_set_sram_bank_state(intr_data->acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) bank, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static int acp_dma_hw_params(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) uint64_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct snd_pcm_runtime *runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct audio_substream_data *rtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct snd_soc_pcm_runtime *prtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct audio_drv_data *adata = dev_get_drvdata(component->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct snd_soc_card *card = prtd->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct acp_platform_info *pinfo = snd_soc_card_get_drvdata(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) rtd = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (WARN_ON(!rtd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (pinfo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) rtd->i2s_instance = pinfo->play_i2s_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) rtd->i2s_instance = pinfo->cap_i2s_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) rtd->capture_channel = pinfo->capture_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (adata->asic_type == CHIP_STONEY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) val = acp_reg_read(adata->acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) mmACP_I2S_16BIT_RESOLUTION_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) switch (rtd->i2s_instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) case I2S_BT_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) val |= ACP_I2S_BT_16BIT_RESOLUTION_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) case I2S_SP_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) val |= ACP_I2S_SP_16BIT_RESOLUTION_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) switch (rtd->i2s_instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) case I2S_BT_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) val |= ACP_I2S_BT_16BIT_RESOLUTION_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) case I2S_SP_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) acp_reg_write(val, adata->acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) mmACP_I2S_16BIT_RESOLUTION_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) switch (rtd->i2s_instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) case I2S_BT_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) rtd->pte_offset = ACP_ST_BT_PLAYBACK_PTE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) rtd->ch1 = SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) rtd->ch2 = ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) rtd->sram_bank = ACP_SRAM_BANK_3_ADDRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) rtd->destination = TO_BLUETOOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) rtd->byte_cnt_high_reg_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) rtd->byte_cnt_low_reg_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) adata->play_i2sbt_stream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) case I2S_SP_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) switch (adata->asic_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) case CHIP_STONEY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) rtd->ch1 = SYSRAM_TO_ACP_CH_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) rtd->destination = TO_ACP_I2S_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) rtd->byte_cnt_high_reg_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) rtd->byte_cnt_low_reg_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) mmACP_I2S_TRANSMIT_BYTE_CNT_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) adata->play_i2ssp_stream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) switch (rtd->i2s_instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) case I2S_BT_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) rtd->pte_offset = ACP_ST_BT_CAPTURE_PTE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) rtd->ch1 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) rtd->ch2 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) rtd->sram_bank = ACP_SRAM_BANK_4_ADDRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) rtd->destination = FROM_BLUETOOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) rtd->byte_cnt_high_reg_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) rtd->byte_cnt_low_reg_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) adata->capture_i2sbt_stream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) case I2S_SP_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) rtd->ch1 = I2S_TO_ACP_DMA_CH_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) rtd->ch2 = ACP_TO_SYSRAM_CH_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) switch (adata->asic_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) case CHIP_STONEY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) rtd->destination = FROM_ACP_I2S_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) rtd->byte_cnt_high_reg_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) mmACP_I2S_RECEIVED_BYTE_CNT_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) rtd->byte_cnt_low_reg_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) mmACP_I2S_RECEIVED_BYTE_CNT_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) adata->capture_i2ssp_stream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) size = params_buffer_bytes(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) acp_set_sram_bank_state(rtd->acp_mmio, 0, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* Save for runtime private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) rtd->dma_addr = runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) rtd->order = get_order(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* Fill the page table entries in ACP SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) rtd->size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) rtd->direction = substream->stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static u64 acp_get_byte_count(struct audio_substream_data *rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) union acp_dma_count byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) byte_count.bcount.high = acp_reg_read(rtd->acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) rtd->byte_cnt_high_reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) byte_count.bcount.low = acp_reg_read(rtd->acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) rtd->byte_cnt_low_reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return byte_count.bytescount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static snd_pcm_uframes_t acp_dma_pointer(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) u32 buffersize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) u32 pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) u64 bytescount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) u16 dscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) u32 period_bytes, delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct audio_substream_data *rtd = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (!rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) period_bytes = frames_to_bytes(runtime, runtime->period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) bytescount = acp_get_byte_count(rtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (bytescount >= rtd->bytescount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) bytescount -= rtd->bytescount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (bytescount < period_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) dscr = acp_reg_read(rtd->acp_mmio, rtd->dma_curr_dscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (dscr == rtd->dma_dscr_idx_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) pos = period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (bytescount > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) delay = do_div(bytescount, period_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) runtime->delay = bytes_to_frames(runtime, delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) buffersize = frames_to_bytes(runtime, runtime->buffer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) bytescount = acp_get_byte_count(rtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (bytescount > rtd->bytescount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) bytescount -= rtd->bytescount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) pos = do_div(bytescount, buffersize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return bytes_to_frames(runtime, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static int acp_dma_mmap(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) struct vm_area_struct *vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return snd_pcm_lib_default_mmap(substream, vma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static int acp_dma_prepare(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct audio_substream_data *rtd = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) u16 ch_acp_sysmem, ch_acp_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (!rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) ch_acp_sysmem = rtd->ch1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ch_acp_i2s = rtd->ch2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ch_acp_i2s = rtd->ch1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ch_acp_sysmem = rtd->ch2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) config_acp_dma_channel(rtd->acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ch_acp_sysmem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) rtd->dma_dscr_idx_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) NUM_DSCRS_PER_CHANNEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) config_acp_dma_channel(rtd->acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ch_acp_i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) rtd->dma_dscr_idx_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) NUM_DSCRS_PER_CHANNEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static int acp_dma_trigger(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) struct audio_substream_data *rtd = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (!rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) rtd->bytescount = acp_get_byte_count(rtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (rtd->capture_channel == CAP_CHANNEL0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) acp_dma_cap_channel_disable(rtd->acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) CAP_CHANNEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) acp_dma_cap_channel_enable(rtd->acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) CAP_CHANNEL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (rtd->capture_channel == CAP_CHANNEL1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) acp_dma_cap_channel_disable(rtd->acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) CAP_CHANNEL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) acp_dma_cap_channel_enable(rtd->acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) CAP_CHANNEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) acp_dma_start(rtd->acp_mmio, rtd->ch1, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) acp_dma_start(rtd->acp_mmio, rtd->ch1, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) acp_dma_start(rtd->acp_mmio, rtd->ch2, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) acp_dma_stop(rtd->acp_mmio, rtd->ch2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static int acp_dma_new(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct snd_soc_pcm_runtime *rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct audio_drv_data *adata = dev_get_drvdata(component->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct device *parent = component->dev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) switch (adata->asic_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) case CHIP_STONEY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) snd_pcm_set_managed_buffer_all(rtd->pcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ST_MIN_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) ST_MAX_BUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) snd_pcm_set_managed_buffer_all(rtd->pcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) MIN_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) MAX_BUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static int acp_dma_close(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) u16 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct audio_substream_data *rtd = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct audio_drv_data *adata = dev_get_drvdata(component->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) switch (rtd->i2s_instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) case I2S_BT_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) adata->play_i2sbt_stream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) case I2S_SP_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) adata->play_i2ssp_stream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) * For Stoney, Memory gating is disabled,i.e SRAM Banks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * won't be turned off. The default state for SRAM banks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) * is ON.Setting SRAM bank state code skipped for STONEY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * platform. Added condition checks for Carrizo platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (adata->asic_type != CHIP_STONEY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) for (bank = 1; bank <= 4; bank++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) acp_set_sram_bank_state(adata->acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) bank, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) switch (rtd->i2s_instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) case I2S_BT_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) adata->capture_i2sbt_stream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) case I2S_SP_INSTANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) adata->capture_i2ssp_stream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (adata->asic_type != CHIP_STONEY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) for (bank = 5; bank <= 8; bank++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) acp_set_sram_bank_state(adata->acp_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) bank, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * Disable ACP irq, when the current stream is being closed and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * another stream is also not active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) !adata->play_i2sbt_stream && !adata->capture_i2sbt_stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) kfree(rtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static const struct snd_soc_component_driver acp_asoc_platform = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .open = acp_dma_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .close = acp_dma_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .hw_params = acp_dma_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .trigger = acp_dma_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .pointer = acp_dma_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .mmap = acp_dma_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .prepare = acp_dma_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .pcm_construct = acp_dma_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) static int acp_audio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) struct audio_drv_data *audio_drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) const u32 *pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) dev_err(&pdev->dev, "Missing platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (!audio_drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) audio_drv_data->acp_mmio = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (IS_ERR(audio_drv_data->acp_mmio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) return PTR_ERR(audio_drv_data->acp_mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * The following members gets populated in device 'open'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * function. Till then interrupts are disabled in 'acp_init'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * and device doesn't generate any interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) audio_drv_data->play_i2ssp_stream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) audio_drv_data->capture_i2ssp_stream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) audio_drv_data->play_i2sbt_stream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) audio_drv_data->capture_i2sbt_stream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) audio_drv_data->asic_type = *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) 0, "ACP_IRQ", &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) dev_err(&pdev->dev, "ACP IRQ request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) dev_set_drvdata(&pdev->dev, audio_drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /* Initialize the ACP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) dev_err(&pdev->dev, "ACP Init failed status:%d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) status = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) &acp_asoc_platform, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) dev_err(&pdev->dev, "Fail to register ALSA platform device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) pm_runtime_set_autosuspend_delay(&pdev->dev, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static int acp_audio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) status = acp_deinit(adata->acp_mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static int acp_pcm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) u16 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct audio_substream_data *rtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct audio_drv_data *adata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) status = acp_init(adata->acp_mmio, adata->asic_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) dev_err(dev, "ACP Init failed status:%d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * For Stoney, Memory gating is disabled,i.e SRAM Banks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * won't be turned off. The default state for SRAM banks is ON.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * Setting SRAM bank state code skipped for STONEY platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (adata->asic_type != CHIP_STONEY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) for (bank = 1; bank <= 4; bank++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) acp_set_sram_bank_state(adata->acp_mmio, bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) rtd = adata->play_i2ssp_stream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (adata->capture_i2ssp_stream &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) adata->capture_i2ssp_stream->runtime) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (adata->asic_type != CHIP_STONEY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) for (bank = 5; bank <= 8; bank++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) acp_set_sram_bank_state(adata->acp_mmio, bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) rtd = adata->capture_i2ssp_stream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (adata->asic_type != CHIP_CARRIZO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (adata->play_i2sbt_stream &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) adata->play_i2sbt_stream->runtime) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) rtd = adata->play_i2sbt_stream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (adata->capture_i2sbt_stream &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) adata->capture_i2sbt_stream->runtime) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) rtd = adata->capture_i2sbt_stream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) static int acp_pcm_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) struct audio_drv_data *adata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) status = acp_deinit(adata->acp_mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) dev_err(dev, "ACP Deinit failed status:%d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) static int acp_pcm_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) struct audio_drv_data *adata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) status = acp_init(adata->acp_mmio, adata->asic_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) dev_err(dev, "ACP Init failed status:%d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) static const struct dev_pm_ops acp_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .resume = acp_pcm_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .runtime_suspend = acp_pcm_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .runtime_resume = acp_pcm_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static struct platform_driver acp_dma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .probe = acp_audio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .remove = acp_audio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .pm = &acp_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) module_platform_driver(acp_dma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) MODULE_DESCRIPTION("AMD ACP PCM Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) MODULE_ALIAS("platform:"DRV_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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