^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2012-2013, Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Lars-Peter Clausen <lars@metafoo.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AXI_SPDIF_REG_CTRL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AXI_SPDIF_REG_STAT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AXI_SPDIF_REG_TX_FIFO 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AXI_SPDIF_CTRL_TXDATA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AXI_SPDIF_CTRL_TXEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AXI_SPDIF_CTRL_CLKDIV_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AXI_SPDIF_CTRL_CLKDIV_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AXI_SPDIF_FREQ_44100 (0x0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AXI_SPDIF_FREQ_48000 (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AXI_SPDIF_FREQ_32000 (0x2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AXI_SPDIF_FREQ_NA (0x3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct axi_spdif {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct clk *clk_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct snd_dmaengine_dai_dma_data dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct snd_ratnum ratnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct snd_pcm_hw_constraint_ratnums rate_constraints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int axi_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct axi_spdif *spdif = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) val = AXI_SPDIF_CTRL_TXDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) AXI_SPDIF_CTRL_TXDATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int axi_spdif_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct axi_spdif *spdif = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int clkdiv, stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) switch (params_rate(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) stat = AXI_SPDIF_FREQ_32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) stat = AXI_SPDIF_FREQ_44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) stat = AXI_SPDIF_FREQ_48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) stat = AXI_SPDIF_FREQ_NA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(spdif->clk_ref),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) rate * 64 * 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) clkdiv <<= AXI_SPDIF_CTRL_CLKDIV_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) regmap_write(spdif->regmap, AXI_SPDIF_REG_STAT, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) AXI_SPDIF_CTRL_CLKDIV_MASK, clkdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int axi_spdif_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct axi_spdif *spdif = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) snd_soc_dai_init_dma_data(dai, &spdif->dma_data, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int axi_spdif_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct axi_spdif *spdif = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ret = snd_pcm_hw_constraint_ratnums(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) &spdif->rate_constraints);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ret = clk_prepare_enable(spdif->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) AXI_SPDIF_CTRL_TXEN, AXI_SPDIF_CTRL_TXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void axi_spdif_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct axi_spdif *spdif = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) AXI_SPDIF_CTRL_TXEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) clk_disable_unprepare(spdif->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct snd_soc_dai_ops axi_spdif_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .startup = axi_spdif_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .shutdown = axi_spdif_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .trigger = axi_spdif_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .hw_params = axi_spdif_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct snd_soc_dai_driver axi_spdif_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .probe = axi_spdif_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .rates = SNDRV_PCM_RATE_KNOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .ops = &axi_spdif_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct snd_soc_component_driver axi_spdif_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .name = "axi-spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct regmap_config axi_spdif_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .max_register = AXI_SPDIF_REG_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int axi_spdif_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct axi_spdif *spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (!spdif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) platform_set_drvdata(pdev, spdif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) spdif->regmap = devm_regmap_init_mmio(&pdev->dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) &axi_spdif_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (IS_ERR(spdif->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return PTR_ERR(spdif->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) spdif->clk = devm_clk_get(&pdev->dev, "axi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (IS_ERR(spdif->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return PTR_ERR(spdif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) spdif->clk_ref = devm_clk_get(&pdev->dev, "ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (IS_ERR(spdif->clk_ref))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return PTR_ERR(spdif->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = clk_prepare_enable(spdif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) spdif->dma_data.addr = res->start + AXI_SPDIF_REG_TX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) spdif->dma_data.addr_width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) spdif->dma_data.maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) spdif->ratnum.num = clk_get_rate(spdif->clk_ref) / 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) spdif->ratnum.den_step = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) spdif->ratnum.den_min = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) spdif->ratnum.den_max = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) spdif->rate_constraints.rats = &spdif->ratnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) spdif->rate_constraints.nrats = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = devm_snd_soc_register_component(&pdev->dev, &axi_spdif_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) &axi_spdif_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) err_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) clk_disable_unprepare(spdif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int axi_spdif_dev_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct axi_spdif *spdif = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) clk_disable_unprepare(spdif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const struct of_device_id axi_spdif_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { .compatible = "adi,axi-spdif-tx-1.00.a", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MODULE_DEVICE_TABLE(of, axi_spdif_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct platform_driver axi_spdif_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .name = "axi-spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .of_match_table = axi_spdif_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .probe = axi_spdif_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .remove = axi_spdif_dev_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) module_platform_driver(axi_spdif_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MODULE_DESCRIPTION("AXI SPDIF driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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