^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2012-2013, Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Lars-Peter Clausen <lars@metafoo.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AXI_I2S_REG_RESET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AXI_I2S_REG_CTRL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AXI_I2S_REG_CLK_CTRL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AXI_I2S_REG_STATUS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AXI_I2S_REG_RX_FIFO 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AXI_I2S_REG_TX_FIFO 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AXI_I2S_RESET_GLOBAL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AXI_I2S_RESET_TX_FIFO BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AXI_I2S_RESET_RX_FIFO BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AXI_I2S_CTRL_TX_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AXI_I2S_CTRL_RX_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* The frame size is configurable, but for now we always set it 64 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AXI_I2S_BITS_PER_FRAME 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct axi_i2s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct clk *clk_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) bool has_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) bool has_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct snd_soc_dai_driver dai_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct snd_dmaengine_dai_dma_data capture_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct snd_dmaengine_dai_dma_data playback_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct snd_ratnum ratnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct snd_pcm_hw_constraint_ratnums rate_constraints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int axi_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct axi_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) mask = AXI_I2S_CTRL_RX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) mask = AXI_I2S_CTRL_TX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) val = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) regmap_update_bits(i2s->regmap, AXI_I2S_REG_CTRL, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int axi_i2s_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct axi_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int bclk_div, word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int bclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) bclk_rate = params_rate(params) * AXI_I2S_BITS_PER_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) word_size = AXI_I2S_BITS_PER_FRAME / 2 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) bclk_div = DIV_ROUND_UP(clk_get_rate(i2s->clk_ref), bclk_rate) / 2 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) regmap_write(i2s->regmap, AXI_I2S_REG_CLK_CTRL, (word_size << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) bclk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int axi_i2s_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct axi_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) uint32_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mask = AXI_I2S_RESET_RX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mask = AXI_I2S_RESET_TX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) regmap_write(i2s->regmap, AXI_I2S_REG_RESET, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = snd_pcm_hw_constraint_ratnums(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) &i2s->rate_constraints);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return clk_prepare_enable(i2s->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void axi_i2s_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct axi_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) clk_disable_unprepare(i2s->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int axi_i2s_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct axi_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) snd_soc_dai_init_dma_data(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) i2s->has_playback ? &i2s->playback_dma_data : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) i2s->has_capture ? &i2s->capture_dma_data : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct snd_soc_dai_ops axi_i2s_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .startup = axi_i2s_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .shutdown = axi_i2s_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .trigger = axi_i2s_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .hw_params = axi_i2s_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct snd_soc_dai_driver axi_i2s_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .probe = axi_i2s_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .ops = &axi_i2s_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .symmetric_rates = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const struct snd_soc_component_driver axi_i2s_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .name = "axi-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct regmap_config axi_i2s_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .max_register = AXI_I2S_REG_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void axi_i2s_parse_of(struct axi_i2s *i2s, const struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct property *dma_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) const char *dma_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) of_property_for_each_string(np, "dma-names", dma_names, dma_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (strcmp(dma_name, "rx") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) i2s->has_capture = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (strcmp(dma_name, "tx") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) i2s->has_playback = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int axi_i2s_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct axi_i2s *i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (!i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) platform_set_drvdata(pdev, i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) axi_i2s_parse_of(i2s, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) i2s->regmap = devm_regmap_init_mmio(&pdev->dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) &axi_i2s_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (IS_ERR(i2s->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return PTR_ERR(i2s->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) i2s->clk = devm_clk_get(&pdev->dev, "axi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (IS_ERR(i2s->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return PTR_ERR(i2s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) i2s->clk_ref = devm_clk_get(&pdev->dev, "ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (IS_ERR(i2s->clk_ref))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return PTR_ERR(i2s->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret = clk_prepare_enable(i2s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (i2s->has_playback) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) axi_i2s_dai.playback.channels_min = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) axi_i2s_dai.playback.channels_max = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) axi_i2s_dai.playback.rates = SNDRV_PCM_RATE_KNOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) axi_i2s_dai.playback.formats =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) i2s->playback_dma_data.addr = res->start + AXI_I2S_REG_TX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) i2s->playback_dma_data.addr_width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) i2s->playback_dma_data.maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (i2s->has_capture) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) axi_i2s_dai.capture.channels_min = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) axi_i2s_dai.capture.channels_max = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) axi_i2s_dai.capture.rates = SNDRV_PCM_RATE_KNOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) axi_i2s_dai.capture.formats =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) i2s->capture_dma_data.addr = res->start + AXI_I2S_REG_RX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) i2s->capture_dma_data.addr_width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) i2s->capture_dma_data.maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) i2s->ratnum.num = clk_get_rate(i2s->clk_ref) / 2 / AXI_I2S_BITS_PER_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) i2s->ratnum.den_step = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) i2s->ratnum.den_min = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) i2s->ratnum.den_max = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) i2s->rate_constraints.rats = &i2s->ratnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) i2s->rate_constraints.nrats = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) regmap_write(i2s->regmap, AXI_I2S_REG_RESET, AXI_I2S_RESET_GLOBAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ret = devm_snd_soc_register_component(&pdev->dev, &axi_i2s_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) &axi_i2s_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev_info(&pdev->dev, "probed, capture %s, playback %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) i2s->has_capture ? "enabled" : "disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) i2s->has_playback ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) err_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) clk_disable_unprepare(i2s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int axi_i2s_dev_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct axi_i2s *i2s = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) clk_disable_unprepare(i2s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const struct of_device_id axi_i2s_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { .compatible = "adi,axi-i2s-1.00.a", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MODULE_DEVICE_TABLE(of, axi_i2s_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static struct platform_driver axi_i2s_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .name = "axi-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .of_match_table = axi_i2s_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .probe = axi_i2s_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .remove = axi_i2s_dev_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) module_platform_driver(axi_i2s_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MODULE_DESCRIPTION("AXI I2S driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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