Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* aica.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Header file for ALSA driver for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Sega Dreamcast Yamaha AICA sound
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright Adrian McMenamin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * <adrian@mcmen.demon.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * 2006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* SPU memory and register constants etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define G2_FIFO 0xa05f688c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SPU_MEMORY_BASE 0xA0800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ARM_RESET_REGISTER 0xA0702C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SPU_REGISTER_BASE 0xA0700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* AICA channels stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AICA_CONTROL_POINT 0xA0810000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AICA_CONTROL_CHANNEL_SAMPLE_NUMBER 0xA0810008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AICA_CHANNEL0_CONTROL_OFFSET 0x10004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Command values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AICA_CMD_KICK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AICA_CMD_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AICA_CMD_START 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AICA_CMD_STOP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AICA_CMD_VOL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Sound modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SM_8BIT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SM_16BIT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SM_ADPCM	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Buffer and period size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AICA_BUFFER_SIZE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AICA_PERIOD_SIZE 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AICA_PERIOD_NUMBER 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AICA_CHANNEL0_OFFSET 0x11000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AICA_CHANNEL1_OFFSET 0x21000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CHANNEL_OFFSET 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AICA_DMA_CHANNEL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AICA_DMA_MODE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SND_AICA_DRIVER "AICA"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct aica_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	uint32_t cmd;		/* Command ID           */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	uint32_t pos;		/* Sample position      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	uint32_t length;	/* Sample length        */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	uint32_t freq;		/* Frequency            */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	uint32_t vol;		/* Volume 0-255         */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	uint32_t pan;		/* Pan 0-255            */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	uint32_t sfmt;		/* Sound format         */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	uint32_t flags;		/* Bit flags            */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct snd_card_aica {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	struct work_struct spu_dma_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	struct aica_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	int clicks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	int current_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	int master_volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	int dma_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };