^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Audio support for PS3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007 Sony Computer Entertainment Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2006, 2007 Sony Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * interrupt / configure registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PS3_AUDIO_INTR_0 (0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PS3_AUDIO_INTR_EN_0 (0x00000140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PS3_AUDIO_CONFIG (0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * DMAC registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * n:0..9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PS3_AUDIO_DMAC_REGBASE(x) (0x0000210 + 0x20 * (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PS3_AUDIO_KICK(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PS3_AUDIO_SOURCE(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PS3_AUDIO_DEST(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PS3_AUDIO_DMASIZE(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * mute control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PS3_AUDIO_AX_MCTRL (0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PS3_AUDIO_AX_ISBP (0x00004004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PS3_AUDIO_AX_AOBP (0x00004008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PS3_AUDIO_AX_IC (0x00004010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PS3_AUDIO_AX_IE (0x00004014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PS3_AUDIO_AX_IS (0x00004018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * three wire serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * n:0..3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PS3_AUDIO_AO_MCTRL (0x00006000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PS3_AUDIO_AO_3WMCTRL (0x00006004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PS3_AUDIO_AO_3WCTRL(n) (0x00006200 + 0x200 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * S/PDIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * n:0..1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * x:0..11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * y:0..5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PS3_AUDIO_AO_SPD_REGBASE(n) (0x00007200 + 0x200 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PS3_AUDIO_AO_SPDCTRL(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) (PS3_AUDIO_AO_SPD_REGBASE(n) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PS3_AUDIO_AO_SPDUB(n, x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) (PS3_AUDIO_AO_SPD_REGBASE(n) + 0x04 + 0x04 * (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PS3_AUDIO_AO_SPDCS(n, y) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) (PS3_AUDIO_AO_SPD_REGBASE(n) + 0x34 + 0x04 * (y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PS3_AUDIO_INTR_0 register tells an interrupt handler which audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DMA channel triggered the interrupt. The interrupt status for a channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) can be cleared by writing a '1' to the corresponding bit. A new interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) cannot be generated until the previous interrupt has been cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) Note that the status reported by PS3_AUDIO_INTR_0 is independent of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) value of PS3_AUDIO_INTR_EN_0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 31 24 23 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) |0 0 0 0 0 0 0 0 0 0 0 0 0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C| INTR_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PS3_AUDIO_INTR_0_CHAN(n) (1 << ((n) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PS3_AUDIO_INTR_0_CHAN9 PS3_AUDIO_INTR_0_CHAN(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PS3_AUDIO_INTR_0_CHAN8 PS3_AUDIO_INTR_0_CHAN(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PS3_AUDIO_INTR_0_CHAN7 PS3_AUDIO_INTR_0_CHAN(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PS3_AUDIO_INTR_0_CHAN6 PS3_AUDIO_INTR_0_CHAN(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PS3_AUDIO_INTR_0_CHAN5 PS3_AUDIO_INTR_0_CHAN(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PS3_AUDIO_INTR_0_CHAN4 PS3_AUDIO_INTR_0_CHAN(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PS3_AUDIO_INTR_0_CHAN3 PS3_AUDIO_INTR_0_CHAN(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PS3_AUDIO_INTR_0_CHAN2 PS3_AUDIO_INTR_0_CHAN(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PS3_AUDIO_INTR_0_CHAN1 PS3_AUDIO_INTR_0_CHAN(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PS3_AUDIO_INTR_0_CHAN0 PS3_AUDIO_INTR_0_CHAN(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) The PS3_AUDIO_INTR_EN_0 register specifies which DMA channels can generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) an interrupt to the PU. Each bit of PS3_AUDIO_INTR_EN_0 is ANDed with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) corresponding bit in PS3_AUDIO_INTR_0. The resulting bits are OR'd together
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) to generate the Audio interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 31 24 23 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) |0 0 0 0 0 0 0 0 0 0 0 0 0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C| INTR_EN_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) Bit assignments are same as PS3_AUDIO_INTR_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PS3_AUDIO_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 31 24 23 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) |0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 C|0 0 0 0 0 0 0 0| CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* The CLEAR field cancels all pending transfers, and stops any running DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) transfers. Any interrupts associated with the canceled transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) will occur as if the transfer had finished.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) Since this bit is designed to recover from DMA related issues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) which are caused by unpredictable situations, it is preferred to wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) for normal DMA transfer end without using this bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PS3_AUDIO_CONFIG_CLEAR (1 << 8) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PS3_AUDIO_AX_MCTRL: Audio Port Mute Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 31 24 23 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|A|A|A|0 0 0 0 0 0 0|S|S|A|A|A|A| AX_MCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* 3 Wire Audio Serial Output Channel Mutes (0..3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PS3_AUDIO_AX_MCTRL_ASOMT(n) (1 << (3 - (n))) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PS3_AUDIO_AX_MCTRL_ASO3MT (1 << 0) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PS3_AUDIO_AX_MCTRL_ASO2MT (1 << 1) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PS3_AUDIO_AX_MCTRL_ASO1MT (1 << 2) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PS3_AUDIO_AX_MCTRL_ASO0MT (1 << 3) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* S/PDIF mutes (0,1)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PS3_AUDIO_AX_MCTRL_SPOMT(n) (1 << (5 - (n))) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PS3_AUDIO_AX_MCTRL_SPO1MT (1 << 4) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PS3_AUDIO_AX_MCTRL_SPO0MT (1 << 5) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* All 3 Wire Serial Outputs Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PS3_AUDIO_AX_MCTRL_AASOMT (1 << 13) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* All S/PDIF Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PS3_AUDIO_AX_MCTRL_ASPOMT (1 << 14) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* All Audio Outputs Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PS3_AUDIO_AX_MCTRL_AAOMT (1 << 15) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) S/PDIF Outputs Buffer Read/Write Pointer Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 31 24 23 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) |0 0 0 0 0 0 0 0|0|SPO0B|0|SPO1B|0 0 0 0 0 0 0 0|0|SPO0B|0|SPO1B| AX_ISBP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) S/PDIF Output Channel Read Buffer Numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) Buffer number is value of field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) Indicates current read access buffer ID from Audio Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) Transfer controller of S/PDIF Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PS3_AUDIO_AX_ISBP_SPOBRN_MASK(n) (0x7 << 4 * (1 - (n))) /* R-IUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PS3_AUDIO_AX_ISBP_SPO1BRN_MASK (0x7 << 0) /* R-IUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PS3_AUDIO_AX_ISBP_SPO0BRN_MASK (0x7 << 4) /* R-IUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) S/PDIF Output Channel Buffer Write Numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) Indicates current write access buffer ID from bus master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PS3_AUDIO_AX_ISBP_SPOBWN_MASK(n) (0x7 << 4 * (5 - (n))) /* R-IUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PS3_AUDIO_AX_ISBP_SPO1BWN_MASK (0x7 << 16) /* R-IUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PS3_AUDIO_AX_ISBP_SPO0BWN_MASK (0x7 << 20) /* R-IUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 3 Wire Audio Serial Outputs Buffer Read/Write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) Pointer Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) Buffer number is value of field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 31 24 23 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) |0|ASO0B|0|ASO1B|0|ASO2B|0|ASO3B|0|ASO0B|0|ASO1B|0|ASO2B|0|ASO3B| AX_AOBP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 3 Wire Audio Serial Output Channel Buffer Read Numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) Indicates current read access buffer Id from Audio Data Transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) Controller of 3 Wire Audio Serial Output Channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PS3_AUDIO_AX_AOBP_ASOBRN_MASK(n) (0x7 << 4 * (3 - (n))) /* R-IUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PS3_AUDIO_AX_AOBP_ASO3BRN_MASK (0x7 << 0) /* R-IUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PS3_AUDIO_AX_AOBP_ASO2BRN_MASK (0x7 << 4) /* R-IUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PS3_AUDIO_AX_AOBP_ASO1BRN_MASK (0x7 << 8) /* R-IUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define PS3_AUDIO_AX_AOBP_ASO0BRN_MASK (0x7 << 12) /* R-IUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 3 Wire Audio Serial Output Channel Buffer Write Numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) Indicates current write access buffer ID from bus master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define PS3_AUDIO_AX_AOBP_ASOBWN_MASK(n) (0x7 << 4 * (7 - (n))) /* R-IUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PS3_AUDIO_AX_AOBP_ASO3BWN_MASK (0x7 << 16) /* R-IUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PS3_AUDIO_AX_AOBP_ASO2BWN_MASK (0x7 << 20) /* R-IUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PS3_AUDIO_AX_AOBP_ASO1BWN_MASK (0x7 << 24) /* R-IUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PS3_AUDIO_AX_AOBP_ASO0BWN_MASK (0x7 << 28) /* R-IUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) Audio Port Interrupt Condition Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) For the fields in this register, the following values apply:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 0 = Interrupt is generated every interrupt event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 1 = Interrupt is generated every 2 interrupt events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 2 = Interrupt is generated every 4 interrupt events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 3 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 31 24 23 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) |0 0 0 0 0 0 0 0|0 0|SPO|0 0|SPO|0 0|AAS|0 0 0 0 0 0 0 0 0 0 0 0| AX_IC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) All 3-Wire Audio Serial Outputs Interrupt Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) Configures the Interrupt and Signal Notification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) condition of all 3-wire Audio Serial Outputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PS3_AUDIO_AX_IC_AASOIMD_MASK (0x3 << 12) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PS3_AUDIO_AX_IC_AASOIMD_EVERY1 (0x0 << 12) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PS3_AUDIO_AX_IC_AASOIMD_EVERY2 (0x1 << 12) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define PS3_AUDIO_AX_IC_AASOIMD_EVERY4 (0x2 << 12) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) S/PDIF Output Channel Interrupt Modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) Configures the Interrupt and signal Notification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) conditions of S/PDIF output channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PS3_AUDIO_AX_IC_SPO1IMD_MASK (0x3 << 16) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define PS3_AUDIO_AX_IC_SPO1IMD_EVERY1 (0x0 << 16) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PS3_AUDIO_AX_IC_SPO1IMD_EVERY2 (0x1 << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PS3_AUDIO_AX_IC_SPO1IMD_EVERY4 (0x2 << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define PS3_AUDIO_AX_IC_SPO0IMD_MASK (0x3 << 20) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define PS3_AUDIO_AX_IC_SPO0IMD_EVERY1 (0x0 << 20) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define PS3_AUDIO_AX_IC_SPO0IMD_EVERY2 (0x1 << 20) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define PS3_AUDIO_AX_IC_SPO0IMD_EVERY4 (0x2 << 20) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) Audio Port interrupt Enable Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) Configures whether to enable or disable each Interrupt Generation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 31 24 23 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) |0 0 0 0 0 0 0 0|S|S|0 0|A|A|A|A|0 0 0 0|S|S|0 0|S|S|0 0|A|A|A|A| AX_IE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 3 Wire Audio Serial Output Channel Buffer Underflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) Interrupt Enables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) Select enable/disable of Buffer Underflow Interrupts for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 3-Wire Audio Serial Output Channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) DISABLED=Interrupt generation disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define PS3_AUDIO_AX_IE_ASOBUIE(n) (1 << (3 - (n))) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define PS3_AUDIO_AX_IE_ASO3BUIE (1 << 0) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define PS3_AUDIO_AX_IE_ASO2BUIE (1 << 1) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define PS3_AUDIO_AX_IE_ASO1BUIE (1 << 2) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define PS3_AUDIO_AX_IE_ASO0BUIE (1 << 3) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* S/PDIF Output Channel Buffer Underflow Interrupt Enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define PS3_AUDIO_AX_IE_SPOBUIE(n) (1 << (7 - (n))) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define PS3_AUDIO_AX_IE_SPO1BUIE (1 << 6) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define PS3_AUDIO_AX_IE_SPO0BUIE (1 << 7) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* S/PDIF Output Channel One Block Transfer Completion Interrupt Enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define PS3_AUDIO_AX_IE_SPOBTCIE(n) (1 << (11 - (n))) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define PS3_AUDIO_AX_IE_SPO1BTCIE (1 << 10) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define PS3_AUDIO_AX_IE_SPO0BTCIE (1 << 11) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* 3-Wire Audio Serial Output Channel Buffer Empty Interrupt Enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define PS3_AUDIO_AX_IE_ASOBEIE(n) (1 << (19 - (n))) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define PS3_AUDIO_AX_IE_ASO3BEIE (1 << 16) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define PS3_AUDIO_AX_IE_ASO2BEIE (1 << 17) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define PS3_AUDIO_AX_IE_ASO1BEIE (1 << 18) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define PS3_AUDIO_AX_IE_ASO0BEIE (1 << 19) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* S/PDIF Output Channel Buffer Empty Interrupt Enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define PS3_AUDIO_AX_IE_SPOBEIE(n) (1 << (23 - (n))) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define PS3_AUDIO_AX_IE_SPO1BEIE (1 << 22) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define PS3_AUDIO_AX_IE_SPO0BEIE (1 << 23) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) Audio Port Interrupt Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) Indicates Interrupt status, which interrupt has occurred, and can clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) each interrupt in this register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) Writing 1b to a field containing 1b clears field and de-asserts interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) Writing 0b to a field has no effect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) Field vaules are the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 0 - Interrupt hasn't occurred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 1 - Interrupt has occurred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 31 24 23 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) |0 0 0 0 0 0 0 0|S|S|0 0|A|A|A|A|0 0 0 0|S|S|0 0|S|S|0 0|A|A|A|A| AX_IS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) Bit assignment are same as AX_IE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) Audio Output Master Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) Configures Master Clock and other master Audio Output Settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 31 24 23 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) |0|SCKSE|0|SCKSE| MR0 | MR1 |MCL|MCL|0 0 0 0|0 0 0 0 0 0 0 0| AO_MCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MCLK Output Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) Controls mclko[1] output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 0 - Disable output (fixed at High)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 1 - Output clock produced by clock selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) with scksel1 by mr1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 2 - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 3 - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define PS3_AUDIO_AO_MCTRL_MCLKC1_MASK (0x3 << 12) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define PS3_AUDIO_AO_MCTRL_MCLKC1_DISABLED (0x0 << 12) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define PS3_AUDIO_AO_MCTRL_MCLKC1_ENABLED (0x1 << 12) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define PS3_AUDIO_AO_MCTRL_MCLKC1_RESVD2 (0x2 << 12) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define PS3_AUDIO_AO_MCTRL_MCLKC1_RESVD3 (0x3 << 12) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MCLK Output Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) Controls mclko[0] output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 0 - Disable output (fixed at High)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 1 - Output clock produced by clock selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) with SCKSEL0 by MR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 2 - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 3 - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define PS3_AUDIO_AO_MCTRL_MCLKC0_MASK (0x3 << 14) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define PS3_AUDIO_AO_MCTRL_MCLKC0_DISABLED (0x0 << 14) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define PS3_AUDIO_AO_MCTRL_MCLKC0_ENABLED (0x1 << 14) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define PS3_AUDIO_AO_MCTRL_MCLKC0_RESVD2 (0x2 << 14) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define PS3_AUDIO_AO_MCTRL_MCLKC0_RESVD3 (0x3 << 14) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) Master Clock Rate 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) Sets the divide ration of Master Clock1 (clock output from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) mclko[1] for the input clock selected by scksel1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define PS3_AUDIO_AO_MCTRL_MR1_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define PS3_AUDIO_AO_MCTRL_MR1_DEFAULT (0x0 << 16) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) Master Clock Rate 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) Sets the divide ratio of Master Clock0 (clock output from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) mclko[0] for the input clock selected by scksel0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define PS3_AUDIO_AO_MCTRL_MR0_MASK (0xf << 20) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define PS3_AUDIO_AO_MCTRL_MR0_DEFAULT (0x0 << 20) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) System Clock Select 0/1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) Selects the system clock to be used as Master Clock 0/1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) Input the system clock that is appropriate for the sampling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define PS3_AUDIO_AO_MCTRL_SCKSEL1_MASK (0x7 << 24) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define PS3_AUDIO_AO_MCTRL_SCKSEL1_DEFAULT (0x2 << 24) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define PS3_AUDIO_AO_MCTRL_SCKSEL0_MASK (0x7 << 28) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define PS3_AUDIO_AO_MCTRL_SCKSEL0_DEFAULT (0x2 << 28) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 3-Wire Audio Output Master Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) Configures clock, 3-Wire Audio Serial Output Enable, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) other 3-Wire Audio Serial Output Master Settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 31 24 23 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) |A|A|A|A|0 0 0|A| ASOSR |0 0 0 0|A|A|A|A|A|A|0|1|0 0 0 0 0 0 0 0| AO_3WMCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) LRCKO Polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 0 - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 1 - default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define PS3_AUDIO_AO_3WMCTRL_ASOPLRCK (1 << 8) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define PS3_AUDIO_AO_3WMCTRL_ASOPLRCK_DEFAULT (1 << 8) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* LRCK Output Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD (1 << 10) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD_ENABLED (0 << 10) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD_DISABLED (1 << 10) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Bit Clock Output Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD (1 << 11) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD_ENABLED (0 << 11) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD_DISABLED (1 << 11) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 3-Wire Audio Serial Output Channel 0-3 Operational
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) Status. Each bit becomes 1 after each 3-Wire Audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) Serial Output Channel N is in action by setting 1 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) asoen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) Each bit becomes 0 after each 3-Wire Audio Serial Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) Channel N is out of action by setting 0 to asoen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define PS3_AUDIO_AO_3WMCTRL_ASORUN(n) (1 << (15 - (n))) /* R-IVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(n) (0 << (15 - (n))) /* R-I-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(n) (1 << (15 - (n))) /* R---V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define PS3_AUDIO_AO_3WMCTRL_ASORUN0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PS3_AUDIO_AO_3WMCTRL_ASORUN(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define PS3_AUDIO_AO_3WMCTRL_ASORUN0_STOPPED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define PS3_AUDIO_AO_3WMCTRL_ASORUN0_RUNNING \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define PS3_AUDIO_AO_3WMCTRL_ASORUN1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PS3_AUDIO_AO_3WMCTRL_ASORUN(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define PS3_AUDIO_AO_3WMCTRL_ASORUN1_STOPPED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define PS3_AUDIO_AO_3WMCTRL_ASORUN1_RUNNING \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define PS3_AUDIO_AO_3WMCTRL_ASORUN2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) PS3_AUDIO_AO_3WMCTRL_ASORUN(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define PS3_AUDIO_AO_3WMCTRL_ASORUN2_STOPPED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define PS3_AUDIO_AO_3WMCTRL_ASORUN2_RUNNING \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define PS3_AUDIO_AO_3WMCTRL_ASORUN3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) PS3_AUDIO_AO_3WMCTRL_ASORUN(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define PS3_AUDIO_AO_3WMCTRL_ASORUN3_STOPPED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define PS3_AUDIO_AO_3WMCTRL_ASORUN3_RUNNING \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) Sampling Rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) Specifies the divide ratio of the bit clock (clock output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) from bclko) used by the 3-wire Audio Output Clock, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) is applied to the master clock selected by mcksel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) Data output is synchronized with this clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define PS3_AUDIO_AO_3WMCTRL_ASOSR_MASK (0xf << 20) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV2 (0x1 << 20) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV4 (0x2 << 20) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV8 (0x4 << 20) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV12 (0x6 << 20) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) Master Clock Select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 0 - Master Clock 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 1 - Master Clock 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL (1 << 24) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL_CLK0 (0 << 24) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL_CLK1 (1 << 24) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) Enables and disables 4ch 3-Wire Audio Serial Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) operation. Each Bit from 0 to 3 corresponds to an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) output channel, which means that each output channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) can be enabled or disabled individually. When
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) multiple channels are enabled at the same time, output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) operations are performed in synchronization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) Bit 0 - Output Channel 0 (SDOUT[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) Bit 1 - Output Channel 1 (SDOUT[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) Bit 2 - Output Channel 2 (SDOUT[2])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) Bit 3 - Output Channel 3 (SDOUT[3])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define PS3_AUDIO_AO_3WMCTRL_ASOEN(n) (1 << (31 - (n))) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(n) (0 << (31 - (n))) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(n) (1 << (31 - (n))) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define PS3_AUDIO_AO_3WMCTRL_ASOEN0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PS3_AUDIO_AO_3WMCTRL_ASOEN(0) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define PS3_AUDIO_AO_3WMCTRL_ASOEN0_DISABLED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(0) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define PS3_AUDIO_AO_3WMCTRL_ASOEN0_ENABLED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(0) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define PS3_AUDIO_A1_3WMCTRL_ASOEN0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) PS3_AUDIO_AO_3WMCTRL_ASOEN(1) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define PS3_AUDIO_A1_3WMCTRL_ASOEN0_DISABLED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(1) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define PS3_AUDIO_A1_3WMCTRL_ASOEN0_ENABLED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(1) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define PS3_AUDIO_A2_3WMCTRL_ASOEN0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) PS3_AUDIO_AO_3WMCTRL_ASOEN(2) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define PS3_AUDIO_A2_3WMCTRL_ASOEN0_DISABLED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(2) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define PS3_AUDIO_A2_3WMCTRL_ASOEN0_ENABLED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(2) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define PS3_AUDIO_A3_3WMCTRL_ASOEN0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) PS3_AUDIO_AO_3WMCTRL_ASOEN(3) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define PS3_AUDIO_A3_3WMCTRL_ASOEN0_DISABLED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(3) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define PS3_AUDIO_A3_3WMCTRL_ASOEN0_ENABLED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(3) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 3-Wire Audio Serial output Channel 0-3 Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) Configures settings for 3-Wire Serial Audio Output Channel 0-3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 31 24 23 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|A|0 0 0 0|A|0|ASO|0 0 0|0|0|0|0|0| AO_3WCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) Data Bit Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) Specifies the number of data bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 0 - 16 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 1 - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 2 - 20 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 3 - 24 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define PS3_AUDIO_AO_3WCTRL_ASODB_MASK (0x3 << 8) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define PS3_AUDIO_AO_3WCTRL_ASODB_16BIT (0x0 << 8) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define PS3_AUDIO_AO_3WCTRL_ASODB_RESVD (0x1 << 8) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define PS3_AUDIO_AO_3WCTRL_ASODB_20BIT (0x2 << 8) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define PS3_AUDIO_AO_3WCTRL_ASODB_24BIT (0x3 << 8) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) Data Format Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) Specifies the data format where (LSB side or MSB) the data(in 20 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) or 24 bit resolution mode) is put in a 32 bit field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 0 - Data put on LSB side
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 1 - Data put on MSB side
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define PS3_AUDIO_AO_3WCTRL_ASODF (1 << 11) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define PS3_AUDIO_AO_3WCTRL_ASODF_LSB (0 << 11) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define PS3_AUDIO_AO_3WCTRL_ASODF_MSB (1 << 11) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) Buffer Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) Performs buffer reset. Writing 1 to this bit initializes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) corresponding 3-Wire Audio Output buffers(both L and R).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define PS3_AUDIO_AO_3WCTRL_ASOBRST (1 << 16) /* CWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define PS3_AUDIO_AO_3WCTRL_ASOBRST_IDLE (0 << 16) /* -WI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define PS3_AUDIO_AO_3WCTRL_ASOBRST_RESET (1 << 16) /* -W--T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) S/PDIF Audio Output Channel 0/1 Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) Configures settings for S/PDIF Audio Output Channel 0/1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 31 24 23 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) |S|0 0 0|S|0 0|S| SPOSR |0 0|SPO|0 0 0 0|S|0|SPO|0 0 0 0 0 0 0|S| AO_SPDCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) Buffer reset. Writing 1 to this bit initializes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) corresponding S/PDIF output buffer pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define PS3_AUDIO_AO_SPDCTRL_SPOBRST (1 << 0) /* CWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define PS3_AUDIO_AO_SPDCTRL_SPOBRST_IDLE (0 << 0) /* -WI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define PS3_AUDIO_AO_SPDCTRL_SPOBRST_RESET (1 << 0) /* -W--T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) Data Bit Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) Specifies number of data bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 0 - 16 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 1 - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 2 - 20 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 3 - 24 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define PS3_AUDIO_AO_SPDCTRL_SPODB_MASK (0x3 << 8) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define PS3_AUDIO_AO_SPDCTRL_SPODB_16BIT (0x0 << 8) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define PS3_AUDIO_AO_SPDCTRL_SPODB_RESVD (0x1 << 8) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define PS3_AUDIO_AO_SPDCTRL_SPODB_20BIT (0x2 << 8) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define PS3_AUDIO_AO_SPDCTRL_SPODB_24BIT (0x3 << 8) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) Data format Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) Specifies the data format, where (LSB side or MSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) the data(in 20 or 24 bit resolution) is put in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 32 bit field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 0 - LSB Side
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 1 - MSB Side
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define PS3_AUDIO_AO_SPDCTRL_SPODF (1 << 11) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define PS3_AUDIO_AO_SPDCTRL_SPODF_LSB (0 << 11) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define PS3_AUDIO_AO_SPDCTRL_SPODF_MSB (1 << 11) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) Source Select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) Specifies the source of the S/PDIF output. When 0, output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) operation is controlled by 3wen[0] of AO_3WMCTRL register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) The SR must have the same setting as the a0_3wmctrl reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 0 - 3-Wire Audio OUT Ch0 Buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 1 - S/PDIF buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define PS3_AUDIO_AO_SPDCTRL_SPOSS_MASK (0x3 << 16) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define PS3_AUDIO_AO_SPDCTRL_SPOSS_3WEN (0x0 << 16) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define PS3_AUDIO_AO_SPDCTRL_SPOSS_SPDIF (0x1 << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) Sampling Rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) Specifies the divide ratio of the bit clock (clock output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) from bclko) used by the S/PDIF Output Clock, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) is applied to the master clock selected by mcksel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define PS3_AUDIO_AO_SPDCTRL_SPOSR (0xf << 20) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV2 (0x1 << 20) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV4 (0x2 << 20) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV8 (0x4 << 20) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV12 (0x6 << 20) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) Master Clock Select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 0 - Master Clock 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 1 - Master Clock 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL (1 << 24) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL_CLK0 (0 << 24) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL_CLK1 (1 << 24) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) S/PDIF Output Channel Operational Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) This bit becomes 1 after S/PDIF Output Channel is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) action by setting 1 to spoen. This bit becomes 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) after S/PDIF Output Channel is out of action by setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 0 to spoen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define PS3_AUDIO_AO_SPDCTRL_SPORUN (1 << 27) /* R-IVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define PS3_AUDIO_AO_SPDCTRL_SPORUN_STOPPED (0 << 27) /* R-I-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define PS3_AUDIO_AO_SPDCTRL_SPORUN_RUNNING (1 << 27) /* R---V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) S/PDIF Audio Output Channel Output Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) Enables and disables output operation. This bit is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) only when sposs = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define PS3_AUDIO_AO_SPDCTRL_SPOEN (1 << 31) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define PS3_AUDIO_AO_SPDCTRL_SPOEN_DISABLED (0 << 31) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define PS3_AUDIO_AO_SPDCTRL_SPOEN_ENABLED (1 << 31) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) S/PDIF Audio Output Channel Channel Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) Setting Registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) Configures channel status bit settings for each block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) (192 bits).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) Output is performed from the MSB(AO_SPDCS0 register bit 31).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) The same value is added for subframes within the same frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 31 24 23 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) | SPOCS | AO_SPDCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) S/PDIF Audio Output Channel User Bit Setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) Configures user bit settings for each block (384 bits).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) Output is performed from the MSB(ao_spdub0 register bit 31).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 31 24 23 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) | SPOUB | AO_SPDUB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * DMAC register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) The PS3_AUDIO_KICK register is used to initiate a DMA transfer and monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) its status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 31 24 23 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) |0 0 0 0 0|STATU|0 0 0| EVENT |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|R| KICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) The REQUEST field is written to ACTIVE to initiate a DMA request when EVENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) occurs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) It will return to the DONE state when the request is completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) The registers for a DMA channel should only be written if REQUEST is IDLE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define PS3_AUDIO_KICK_REQUEST (1 << 0) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define PS3_AUDIO_KICK_REQUEST_IDLE (0 << 0) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define PS3_AUDIO_KICK_REQUEST_ACTIVE (1 << 0) /* -W--T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) *The EVENT field is used to set the event in which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) *the DMA request becomes active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define PS3_AUDIO_KICK_EVENT_MASK (0x1f << 16) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define PS3_AUDIO_KICK_EVENT_ALWAYS (0x00 << 16) /* RWI-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define PS3_AUDIO_KICK_EVENT_SERIALOUT0_EMPTY (0x01 << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define PS3_AUDIO_KICK_EVENT_SERIALOUT0_UNDERFLOW (0x02 << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define PS3_AUDIO_KICK_EVENT_SERIALOUT1_EMPTY (0x03 << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define PS3_AUDIO_KICK_EVENT_SERIALOUT1_UNDERFLOW (0x04 << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define PS3_AUDIO_KICK_EVENT_SERIALOUT2_EMPTY (0x05 << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define PS3_AUDIO_KICK_EVENT_SERIALOUT2_UNDERFLOW (0x06 << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define PS3_AUDIO_KICK_EVENT_SERIALOUT3_EMPTY (0x07 << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define PS3_AUDIO_KICK_EVENT_SERIALOUT3_UNDERFLOW (0x08 << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define PS3_AUDIO_KICK_EVENT_SPDIF0_BLOCKTRANSFERCOMPLETE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) (0x09 << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define PS3_AUDIO_KICK_EVENT_SPDIF0_UNDERFLOW (0x0A << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define PS3_AUDIO_KICK_EVENT_SPDIF0_EMPTY (0x0B << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define PS3_AUDIO_KICK_EVENT_SPDIF1_BLOCKTRANSFERCOMPLETE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) (0x0C << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define PS3_AUDIO_KICK_EVENT_SPDIF1_UNDERFLOW (0x0D << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define PS3_AUDIO_KICK_EVENT_SPDIF1_EMPTY (0x0E << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ((0x13 + (n)) << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA0 (0x13 << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA1 (0x14 << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA2 (0x15 << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA3 (0x16 << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA4 (0x17 << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA5 (0x18 << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA6 (0x19 << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA7 (0x1A << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA8 (0x1B << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA9 (0x1C << 16) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) The STATUS field can be used to monitor the progress of a DMA request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) DONE indicates the previous request has completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) EVENT indicates that the DMA engine is waiting for the EVENT to occur.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) PENDING indicates that the DMA engine has not started processing this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) request, but the EVENT has occurred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) DMA indicates that the data transfer is in progress.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) NOTIFY indicates that the notifier signalling end of transfer is being written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) CLEAR indicated that the previous transfer was cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ERROR indicates the previous transfer requested an unsupported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) source/destination combination.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define PS3_AUDIO_KICK_STATUS_MASK (0x7 << 24) /* R-IVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define PS3_AUDIO_KICK_STATUS_DONE (0x0 << 24) /* R-I-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define PS3_AUDIO_KICK_STATUS_EVENT (0x1 << 24) /* R---V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define PS3_AUDIO_KICK_STATUS_PENDING (0x2 << 24) /* R---V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define PS3_AUDIO_KICK_STATUS_DMA (0x3 << 24) /* R---V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define PS3_AUDIO_KICK_STATUS_NOTIFY (0x4 << 24) /* R---V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define PS3_AUDIO_KICK_STATUS_CLEAR (0x5 << 24) /* R---V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define PS3_AUDIO_KICK_STATUS_ERROR (0x6 << 24) /* R---V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) The PS3_AUDIO_SOURCE register specifies the source address for transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 31 24 23 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) | START |0 0 0 0 0|TAR| SOURCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) The Audio DMA engine uses 128-byte transfers, thus the address must be aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) to a 128 byte boundary. The low seven bits are assumed to be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define PS3_AUDIO_SOURCE_START_MASK (0x01FFFFFF << 7) /* RWIUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) The TARGET field specifies the memory space containing the source address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define PS3_AUDIO_SOURCE_TARGET_MASK (3 << 0) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define PS3_AUDIO_SOURCE_TARGET_SYSTEM_MEMORY (2 << 0) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) The PS3_AUDIO_DEST register specifies the destination address for transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 31 24 23 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) | START |0 0 0 0 0|TAR| DEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) The Audio DMA engine uses 128-byte transfers, thus the address must be aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) to a 128 byte boundary. The low seven bits are assumed to be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define PS3_AUDIO_DEST_START_MASK (0x01FFFFFF << 7) /* RWIUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) The TARGET field specifies the memory space containing the destination address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) AUDIOFIFO = Audio WriteData FIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define PS3_AUDIO_DEST_TARGET_MASK (3 << 0) /* RWIVF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define PS3_AUDIO_DEST_TARGET_AUDIOFIFO (1 << 0) /* RW--V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) PS3_AUDIO_DMASIZE specifies the number of 128-byte blocks + 1 to transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) So a value of 0 means 128-bytes will get transferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) 31 24 23 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| BLOCKS | DMASIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define PS3_AUDIO_DMASIZE_BLOCKS_MASK (0x7f << 0) /* RWIUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * source/destination address for internal fifos
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define PS3_AUDIO_AO_3W_LDATA(n) (0x1000 + (0x100 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define PS3_AUDIO_AO_3W_RDATA(n) (0x1080 + (0x100 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define PS3_AUDIO_AO_SPD_DATA(n) (0x2000 + (0x400 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * field attiribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * Read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * ' ' = Other Information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * '-' = Field is part of a write-only register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * 'C' = Value read is always the same, constant value line follows (C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * 'R' = Value is read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * Write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * ' ' = Other Information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * '-' = Must not be written (D), value ignored when written (R,A,F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * 'W' = Can be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * Internal State
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * ' ' = Other Information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * '-' = No internal state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * 'X' = Internal state, initial value is unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * 'I' = Internal state, initial value is known and follows (I)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * Declaration/Size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * ' ' = Other Information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * '-' = Does Not Apply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * 'V' = Type is void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * 'U' = Type is unsigned integer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * 'S' = Type is signed integer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * 'F' = Type is IEEE floating point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * '1' = Byte size (008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * '2' = Short size (016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * '3' = Three byte size (024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * '4' = Word size (032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * '8' = Double size (064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * Define Indicator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * ' ' = Other Information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * 'D' = Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * 'M' = Memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * 'R' = Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * 'A' = Array of Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * 'F' = Field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * 'V' = Value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * 'T' = Task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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