Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Driver for PowerMac AWACS onboard soundchips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2001 by Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *   based on dmasound.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #ifndef __AWACS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define __AWACS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /*******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /* AWACs Audio Register Layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /*******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) struct awacs_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)     unsigned	control;	/* Audio control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)     unsigned	pad0[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)     unsigned	codec_ctrl;	/* Codec control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)     unsigned	pad1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)     unsigned	codec_stat;	/* Codec status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)     unsigned	pad2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)     unsigned	clip_count;	/* Clipping count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)     unsigned	pad3[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)     unsigned	byteswap;	/* Data is little-endian if 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /*******************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* Audio Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /*******************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* Audio Control Reg Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* ----- ------- --- --- ----- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MASK_ISFSEL	(0xf)		/* Input SubFrame Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MASK_OSFSEL	(0xf << 4)	/* Output SubFrame Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MASK_RATE	(0x7 << 8)	/* Sound Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MASK_CNTLERR	(0x1 << 11)	/* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MASK_PORTCHG	(0x1 << 12)	/* Port Change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MASK_IEE	(0x1 << 13)	/* Enable Interrupt on Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MASK_IEPC	(0x1 << 14)	/* Enable Interrupt on Port Change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MASK_SSFSEL	(0x3 << 15)	/* Status SubFrame Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* Audio Codec Control Reg Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* ----- ----- ------- --- --- ----- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MASK_NEWECMD	(0x1 << 24)	/* Lock: don't write to reg when 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MASK_EMODESEL	(0x3 << 22)	/* Send info out on which frame? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MASK_EXMODEADDR	(0x3ff << 12)	/* Extended Mode Address -- 10 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MASK_EXMODEDATA	(0xfff)		/* Extended Mode Data -- 12 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* Audio Codec Control Address Values / Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /* ----- ----- ------- ------- ------ - ----- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MASK_ADDR0	(0x0 << 12)	/* Expanded Data Mode Address 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MASK_ADDR_MUX	MASK_ADDR0	/* Mux Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define MASK_ADDR_GAIN	MASK_ADDR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MASK_ADDR1	(0x1 << 12)	/* Expanded Data Mode Address 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define MASK_ADDR_MUTE	MASK_ADDR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define MASK_ADDR_RATE	MASK_ADDR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MASK_ADDR2	(0x2 << 12)	/* Expanded Data Mode Address 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MASK_ADDR_VOLA	MASK_ADDR2	/* Volume Control A -- Headphones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MASK_ADDR_VOLHD MASK_ADDR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define MASK_ADDR4	(0x4 << 12)	/* Expanded Data Mode Address 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define MASK_ADDR_VOLC	MASK_ADDR4	/* Volume Control C -- Speaker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define MASK_ADDR_VOLSPK MASK_ADDR4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* additional registers of screamer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define MASK_ADDR5	(0x5 << 12)	/* Expanded Data Mode Address 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define MASK_ADDR6	(0x6 << 12)	/* Expanded Data Mode Address 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define MASK_ADDR7	(0x7 << 12)	/* Expanded Data Mode Address 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* Address 0 Bit Masks & Macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* ------- - --- ----- - ------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define MASK_GAINRIGHT	(0xf)		/* Gain Right Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define MASK_GAINLEFT	(0xf << 4)	/* Gain Left Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define MASK_GAINLINE	(0x1 << 8)	/* Disable Mic preamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define MASK_GAINMIC	(0x0 << 8)	/* Enable Mic preamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define MASK_MUX_CD	(0x1 << 9)	/* Select CD in MUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define MASK_MUX_MIC	(0x1 << 10)	/* Select Mic in MUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define MASK_MUX_AUDIN	(0x1 << 11)	/* Select Audio In in MUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define MASK_MUX_LINE	MASK_MUX_AUDIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define SHIFT_GAINLINE	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define SHIFT_MUX_CD	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define SHIFT_MUX_MIC	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define SHIFT_MUX_LINE	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define GAINRIGHT(x)	((x) & MASK_GAINRIGHT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define GAINLEFT(x)	(((x) << 4) & MASK_GAINLEFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /* Address 1 Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* ------- - --- ----- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define MASK_ADDR1RES1	(0x3)		/* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define MASK_RECALIBRATE (0x1 << 2)	/* Recalibrate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define MASK_SAMPLERATE	(0x7 << 3)	/* Sample Rate: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define MASK_LOOPTHRU	(0x1 << 6)	/* Loopthrough Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define SHIFT_LOOPTHRU	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define MASK_CMUTE	(0x1 << 7)	/* Output C (Speaker) Mute when 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define MASK_SPKMUTE	MASK_CMUTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SHIFT_SPKMUTE	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MASK_ADDR1RES2	(0x1 << 8)	/* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MASK_AMUTE	(0x1 << 9)	/* Output A (Headphone) Mute when 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MASK_HDMUTE	MASK_AMUTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SHIFT_HDMUTE	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MASK_PAROUT	(0x3 << 10)	/* Parallel Out (???) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MASK_PAROUT0	(0x1 << 10)	/* Parallel Out (???) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MASK_PAROUT1	(0x1 << 11)	/* Parallel Out (enable speaker) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SHIFT_PAROUT	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SHIFT_PAROUT0	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SHIFT_PAROUT1	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SAMPLERATE_48000	(0x0 << 3)	/* 48 or 44.1 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SAMPLERATE_32000	(0x1 << 3)	/* 32 or 29.4 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SAMPLERATE_24000	(0x2 << 3)	/* 24 or 22.05 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SAMPLERATE_19200	(0x3 << 3)	/* 19.2 or 17.64 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SAMPLERATE_16000	(0x4 << 3)	/* 16 or 14.7 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SAMPLERATE_12000	(0x5 << 3)	/* 12 or 11.025 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SAMPLERATE_9600		(0x6 << 3)	/* 9.6 or 8.82 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SAMPLERATE_8000		(0x7 << 3)	/* 8 or 7.35 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Address 2 & 4 Bit Masks & Macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* ------- - - - --- ----- - ------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MASK_OUTVOLRIGHT (0xf)		/* Output Right Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MASK_ADDR2RES1	(0x2 << 4)	/* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MASK_ADDR4RES1	MASK_ADDR2RES1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MASK_OUTVOLLEFT	(0xf << 6)	/* Output Left Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MASK_ADDR2RES2	(0x2 << 10)	/* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MASK_ADDR4RES2	MASK_ADDR2RES2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define VOLRIGHT(x)	(((~(x)) & MASK_OUTVOLRIGHT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define VOLLEFT(x)	(((~(x)) << 6) & MASK_OUTVOLLEFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* address 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MASK_MIC_BOOST  (0x4)		/* screamer mic boost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SHIFT_MIC_BOOST	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Audio Codec Status Reg Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* ----- ----- ------ --- --- ----- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MASK_EXTEND	(0x1 << 23)	/* Extend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MASK_VALID	(0x1 << 22)	/* Valid Data? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MASK_OFLEFT	(0x1 << 21)	/* Overflow Left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MASK_OFRIGHT	(0x1 << 20)	/* Overflow Right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MASK_ERRCODE	(0xf << 16)	/* Error Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MASK_REVISION	(0xf << 12)	/* Revision Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MASK_MFGID	(0xf << 8)	/* Mfg. ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MASK_CODSTATRES	(0xf << 4)	/* bits 4 - 7 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MASK_INSENSE	(0xf)		/* port sense bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MASK_HDPCONN		8	/* headphone plugged in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MASK_LOCONN		4	/* line-out plugged in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MASK_LICONN		2	/* line-in plugged in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MASK_MICCONN		1	/* microphone plugged in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MASK_LICONN_IMAC	8	/* line-in plugged in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MASK_HDPRCONN_IMAC	4	/* headphone right plugged in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MASK_HDPLCONN_IMAC	2	/* headphone left plugged in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MASK_LOCONN_IMAC	1	/* line-out plugged in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Clipping Count Reg Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* -------- ----- --- --- ----- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MASK_CLIPLEFT	(0xff << 7)	/* Clipping Count, Left Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MASK_CLIPRIGHT	(0xff)		/* Clipping Count, Right Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* DBDMA ChannelStatus Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* ----- ------------- --- ----- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MASK_CSERR	(0x1 << 7)	/* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MASK_EOI	(0x1 << 6)	/* End of Input --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 					   only for Input Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MASK_CSUNUSED	(0x1f << 1)	/* bits 1-5 not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MASK_WAIT	(0x1)		/* Wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Various Rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* ------- ----- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define RATE_48000	(0x0 << 8)	/* 48 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define RATE_44100	(0x0 << 8)	/* 44.1 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define RATE_32000	(0x1 << 8)	/* 32 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define RATE_29400	(0x1 << 8)	/* 29.4 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define RATE_24000	(0x2 << 8)	/* 24 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define RATE_22050	(0x2 << 8)	/* 22.05 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define RATE_19200	(0x3 << 8)	/* 19.2 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define RATE_17640	(0x3 << 8)	/* 17.64 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define RATE_16000	(0x4 << 8)	/* 16 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RATE_14700	(0x4 << 8)	/* 14.7 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define RATE_12000	(0x5 << 8)	/* 12 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define RATE_11025	(0x5 << 8)	/* 11.025 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define RATE_9600	(0x6 << 8)	/* 9.6 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define RATE_8820	(0x6 << 8)	/* 8.82 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define RATE_8000	(0x7 << 8)	/* 8 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define RATE_7350	(0x7 << 8)	/* 7.35 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define RATE_LOW	1	/* HIGH = 48kHz, etc;  LOW = 44.1kHz, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #endif /* __AWACS_H */