^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Digigram VXpocket soundcards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __VXPOCKET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __VXPOCKET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <sound/vx_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <pcmcia/cistpl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <pcmcia/ds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct snd_vxpocket {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct vx_core core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) unsigned long port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int mic_level; /* analog mic level (or boost) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned int regCDSP; /* current CDSP register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned int regDIALOG; /* current DIALOG register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) int index; /* card index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* pcmcia stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct pcmcia_device *p_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define to_vxpocket(x) container_of(x, struct snd_vxpocket, core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) extern const struct snd_vx_ops snd_vxpocket_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void vx_set_mic_boost(struct vx_core *chip, int boost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void vx_set_mic_level(struct vx_core *chip, int level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int vxp_add_mic_controls(struct vx_core *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Constants used to access the CDSP register (0x08). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CDSP_MAGIC 0xA7 /* magic value (for read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* for write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define VXP_CDSP_CLOCKIN_SEL_MASK 0x80 /* 0 (internal), 1 (AES/EBU) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define VXP_CDSP_DATAIN_SEL_MASK 0x40 /* 0 (analog), 1 (UER) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define VXP_CDSP_SMPTE_SEL_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VXP_CDSP_RESERVED_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VXP_CDSP_MIC_SEL_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VXP_CDSP_VALID_IRQ_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VXP_CDSP_CODEC_RESET_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VXP_CDSP_DSP_RESET_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* VXPOCKET 240/440 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define P24_CDSP_MICS_SEL_MASK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define P24_CDSP_MIC20_SEL_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define P24_CDSP_MIC38_SEL_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Constants used to access the MEMIRQ register (0x0C). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define P44_MEMIRQ_MASTER_SLAVE_SEL_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define P44_MEMIRQ_SYNCED_ALONE_SEL_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define P44_MEMIRQ_WCLK_OUT_IN_SEL_MASK 0x02 /* Not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define P44_MEMIRQ_WCLK_UER_SEL_MASK 0x01 /* Not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Micro levels (0x0C) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Constants used to access the DIALOG register (0x0D). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VXP_DLG_XILINX_REPROG_MASK 0x80 /* W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define VXP_DLG_DATA_XICOR_MASK 0x80 /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define VXP_DLG_RESERVED4_0_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VXP_DLG_RESERVED2_0_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define VXP_DLG_RESERVED1_0_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define VXP_DLG_DMAWRITE_SEL_MASK 0x08 /* W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define VXP_DLG_DMAREAD_SEL_MASK 0x04 /* W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define VXP_DLG_MEMIRQ_MASK 0x02 /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define VXP_DLG_DMA16_SEL_MASK 0x02 /* W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define VXP_DLG_ACK_MEMIRQ_MASK 0x01 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #endif /* __VXPOCKET_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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