^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Digigram VXpocket soundcards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * lowlevel routines for VXpocket soundcards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "vxpocket.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static const int vxp_reg_offset[VX_REG_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) [VX_ICR] = 0x00, // ICR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) [VX_CVR] = 0x01, // CVR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) [VX_ISR] = 0x02, // ISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) [VX_IVR] = 0x03, // IVR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) [VX_RXH] = 0x05, // RXH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) [VX_RXM] = 0x06, // RXM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) [VX_RXL] = 0x07, // RXL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) [VX_DMA] = 0x04, // DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) [VX_CDSP] = 0x08, // CDSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) [VX_LOFREQ] = 0x09, // LFREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) [VX_HIFREQ] = 0x0a, // HFREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) [VX_DATA] = 0x0b, // DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) [VX_MICRO] = 0x0c, // MICRO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) [VX_DIALOG] = 0x0d, // DIALOG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) [VX_CSUER] = 0x0e, // CSUER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) [VX_RUER] = 0x0f, // RUER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static inline unsigned long vxp_reg_addr(struct vx_core *_chip, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct snd_vxpocket *chip = to_vxpocket(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return chip->port + vxp_reg_offset[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * snd_vx_inb - read a byte from the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @offset: register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static unsigned char vxp_inb(struct vx_core *chip, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return inb(vxp_reg_addr(chip, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * snd_vx_outb - write a byte on the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @offset: the register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @val: the value to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void vxp_outb(struct vx_core *chip, int offset, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) outb(val, vxp_reg_addr(chip, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * redefine macros to call directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #undef vx_inb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define vx_inb(chip,reg) vxp_inb((struct vx_core *)(chip), VX_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #undef vx_outb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define vx_outb(chip,reg,val) vxp_outb((struct vx_core *)(chip), VX_##reg,val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * vx_check_magic - check the magic word on xilinx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * returns zero if a magic word is detected, or a negative error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int vx_check_magic(struct vx_core *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long end_time = jiffies + HZ / 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) c = vx_inb(chip, CDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (c == CDSP_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) } while (time_after_eq(end_time, jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) snd_printk(KERN_ERR "cannot find xilinx magic word (%x)\n", c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * vx_reset_dsp - reset the DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define XX_DSP_RESET_WAIT_TIME 2 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void vxp_reset_dsp(struct vx_core *_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct snd_vxpocket *chip = to_vxpocket(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* set the reset dsp bit to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) vx_outb(chip, CDSP, chip->regCDSP | VXP_CDSP_DSP_RESET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) vx_inb(chip, CDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mdelay(XX_DSP_RESET_WAIT_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* reset the bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) chip->regCDSP &= ~VXP_CDSP_DSP_RESET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) vx_outb(chip, CDSP, chip->regCDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) vx_inb(chip, CDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mdelay(XX_DSP_RESET_WAIT_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * reset codec bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void vxp_reset_codec(struct vx_core *_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct snd_vxpocket *chip = to_vxpocket(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Set the reset CODEC bit to 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) vx_outb(chip, CDSP, chip->regCDSP | VXP_CDSP_CODEC_RESET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) vx_inb(chip, CDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Set the reset CODEC bit to 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) chip->regCDSP &= ~VXP_CDSP_CODEC_RESET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) vx_outb(chip, CDSP, chip->regCDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) vx_inb(chip, CDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * vx_load_xilinx_binary - load the xilinx binary image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * the binary image is the binary array converted from the bitstream file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int vxp_load_xilinx_binary(struct vx_core *_chip, const struct firmware *fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct snd_vxpocket *chip = to_vxpocket(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int regCSUER, regRUER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const unsigned char *image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned char data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Switch to programmation mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) chip->regDIALOG |= VXP_DLG_XILINX_REPROG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) vx_outb(chip, DIALOG, chip->regDIALOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Save register CSUER and RUER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) regCSUER = vx_inb(chip, CSUER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) regRUER = vx_inb(chip, RUER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* reset HF0 and HF1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) vx_outb(chip, ICR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Wait for answer HF2 equal to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) snd_printdd(KERN_DEBUG "check ISR_HF2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (vx_check_isr(_chip, ISR_HF2, ISR_HF2, 20) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) goto _error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* set HF1 for loading xilinx binary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) vx_outb(chip, ICR, ICR_HF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) image = fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) for (i = 0; i < fw->size; i++, image++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) data = *image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (vx_wait_isr_bit(_chip, ISR_TX_EMPTY) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) goto _error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) vx_outb(chip, TXL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* wait for reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (vx_wait_for_rx_full(_chip) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) goto _error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) c = vx_inb(chip, RXL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (c != (int)data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) snd_printk(KERN_ERR "vxpocket: load xilinx mismatch at %d: 0x%x != 0x%x\n", i, c, (int)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* reset HF1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) vx_outb(chip, ICR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* wait for HF3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (vx_check_isr(_chip, ISR_HF3, ISR_HF3, 20) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) goto _error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* read the number of bytes received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (vx_wait_for_rx_full(_chip) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) goto _error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) c = (int)vx_inb(chip, RXH) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) c |= (int)vx_inb(chip, RXM) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) c |= vx_inb(chip, RXL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) snd_printdd(KERN_DEBUG "xilinx: dsp size received 0x%x, orig 0x%zx\n", c, fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) vx_outb(chip, ICR, ICR_HF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* TEMPO 250ms : wait until Xilinx is downloaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) msleep(300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* test magical word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (vx_check_magic(_chip) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) goto _error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Restore register 0x0E and 0x0F (thus replacing COR and FCSR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) vx_outb(chip, CSUER, regCSUER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) vx_outb(chip, RUER, regRUER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Reset the Xilinx's signal enabling IO access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) chip->regDIALOG |= VXP_DLG_XILINX_REPROG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) vx_outb(chip, DIALOG, chip->regDIALOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) vx_inb(chip, DIALOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) chip->regDIALOG &= ~VXP_DLG_XILINX_REPROG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) vx_outb(chip, DIALOG, chip->regDIALOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) vx_inb(chip, DIALOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Reset of the Codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) vxp_reset_codec(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) vx_reset_dsp(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) _error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) vx_outb(chip, CSUER, regCSUER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) vx_outb(chip, RUER, regRUER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) chip->regDIALOG &= ~VXP_DLG_XILINX_REPROG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) vx_outb(chip, DIALOG, chip->regDIALOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * vxp_load_dsp - load_dsp callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int vxp_load_dsp(struct vx_core *vx, int index, const struct firmware *fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* xilinx boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if ((err = vx_check_magic(vx)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if ((err = snd_vx_load_boot_image(vx, fw)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* xilinx image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return vxp_load_xilinx_binary(vx, fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* DSP boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return snd_vx_dsp_boot(vx, fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* DSP image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return snd_vx_dsp_load(vx, fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * vx_test_and_ack - test and acknowledge interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * called from irq hander, too
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * spinlock held!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int vxp_test_and_ack(struct vx_core *_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct snd_vxpocket *chip = to_vxpocket(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* not booted yet? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (! (_chip->chip_status & VX_STAT_XILINX_LOADED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (! (vx_inb(chip, DIALOG) & VXP_DLG_MEMIRQ_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* ok, interrupts generated, now ack it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* set ACQUIT bit up and down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) vx_outb(chip, DIALOG, chip->regDIALOG | VXP_DLG_ACK_MEMIRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* useless read just to spend some time and maintain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * the ACQUIT signal up for a while ( a bus cycle )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) vx_inb(chip, DIALOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) vx_outb(chip, DIALOG, chip->regDIALOG & ~VXP_DLG_ACK_MEMIRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * vx_validate_irq - enable/disable IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static void vxp_validate_irq(struct vx_core *_chip, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct snd_vxpocket *chip = to_vxpocket(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Set the interrupt enable bit to 1 in CDSP register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) chip->regCDSP |= VXP_CDSP_VALID_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) chip->regCDSP &= ~VXP_CDSP_VALID_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) vx_outb(chip, CDSP, chip->regCDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * vx_setup_pseudo_dma - set up the pseudo dma read/write mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * @do_write: 0 = read, 1 = set up for DMA write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static void vx_setup_pseudo_dma(struct vx_core *_chip, int do_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct snd_vxpocket *chip = to_vxpocket(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Interrupt mode and HREQ pin enabled for host transmit / receive data transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) vx_outb(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Reset the pseudo-dma register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) vx_inb(chip, ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) vx_outb(chip, ISR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Select DMA in read/write transfer mode and in 16-bit accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) chip->regDIALOG |= VXP_DLG_DMA16_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) chip->regDIALOG |= do_write ? VXP_DLG_DMAWRITE_SEL_MASK : VXP_DLG_DMAREAD_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) vx_outb(chip, DIALOG, chip->regDIALOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * vx_release_pseudo_dma - disable the pseudo-DMA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static void vx_release_pseudo_dma(struct vx_core *_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct snd_vxpocket *chip = to_vxpocket(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Disable DMA and 16-bit accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) chip->regDIALOG &= ~(VXP_DLG_DMAWRITE_SEL_MASK|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) VXP_DLG_DMAREAD_SEL_MASK|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) VXP_DLG_DMA16_SEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) vx_outb(chip, DIALOG, chip->regDIALOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* HREQ pin disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) vx_outb(chip, ICR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * vx_pseudo_dma_write - write bulk data on pseudo-DMA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * @count: data length to transfer in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * data size must be aligned to 6 bytes to ensure the 24bit alignment on DSP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * NB: call with a certain lock!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void vxp_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct vx_pipe *pipe, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) long port = vxp_reg_addr(chip, VX_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int offset = pipe->hw_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned short *addr = (unsigned short *)(runtime->dma_area + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) vx_setup_pseudo_dma(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (offset + count >= pipe->buffer_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int length = pipe->buffer_bytes - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) count -= length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) length >>= 1; /* in 16bit words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Transfer using pseudo-dma. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) for (; length > 0; length--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) outw(*addr, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) addr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) addr = (unsigned short *)runtime->dma_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pipe->hw_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pipe->hw_ptr += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) count >>= 1; /* in 16bit words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Transfer using pseudo-dma. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) for (; count > 0; count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) outw(*addr, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) addr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) vx_release_pseudo_dma(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * vx_pseudo_dma_read - read bulk data on pseudo DMA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * @offset: buffer offset in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * @count: data length to transfer in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * the read length must be aligned to 6 bytes, as well as write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * NB: call with a certain lock!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static void vxp_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct vx_pipe *pipe, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct snd_vxpocket *pchip = to_vxpocket(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) long port = vxp_reg_addr(chip, VX_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int offset = pipe->hw_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned short *addr = (unsigned short *)(runtime->dma_area + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (snd_BUG_ON(count % 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) vx_setup_pseudo_dma(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (offset + count >= pipe->buffer_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int length = pipe->buffer_bytes - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) count -= length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) length >>= 1; /* in 16bit words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Transfer using pseudo-dma. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) for (; length > 0; length--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) *addr++ = inw(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) addr = (unsigned short *)runtime->dma_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) pipe->hw_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) pipe->hw_ptr += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) count >>= 1; /* in 16bit words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Transfer using pseudo-dma. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) for (; count > 1; count--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) *addr++ = inw(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Disable DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) pchip->regDIALOG &= ~VXP_DLG_DMAREAD_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) vx_outb(chip, DIALOG, pchip->regDIALOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Read the last word (16 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) *addr = inw(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Disable 16-bit accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) pchip->regDIALOG &= ~VXP_DLG_DMA16_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) vx_outb(chip, DIALOG, pchip->regDIALOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* HREQ pin disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) vx_outb(chip, ICR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * write a codec data (24bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static void vxp_write_codec_reg(struct vx_core *chip, int codec, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* Activate access to the corresponding codec register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (! codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) vx_inb(chip, LOFREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) vx_inb(chip, CODEC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* We have to send 24 bits (3 x 8 bits). Start with most signif. Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) for (i = 0; i < 24; i++, data <<= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) vx_outb(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Terminate access to codec registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) vx_inb(chip, HIFREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * vx_set_mic_boost - set mic boost level (on vxp440 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * @boost: 0 = 20dB, 1 = +38dB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) void vx_set_mic_boost(struct vx_core *chip, int boost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct snd_vxpocket *pchip = to_vxpocket(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (chip->chip_status & VX_STAT_IS_STALE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) mutex_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (pchip->regCDSP & P24_CDSP_MICS_SEL_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (boost) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* boost: 38 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pchip->regCDSP &= ~P24_CDSP_MIC20_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) pchip->regCDSP |= P24_CDSP_MIC38_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* minimum value: 20 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pchip->regCDSP |= P24_CDSP_MIC20_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pchip->regCDSP &= ~P24_CDSP_MIC38_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) vx_outb(chip, CDSP, pchip->regCDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mutex_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * remap the linear value (0-8) to the actual value (0-15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int vx_compute_mic_level(int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) switch (level) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case 5: level = 6 ; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) case 6: level = 8 ; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case 7: level = 11; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) case 8: level = 15; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) default: break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * vx_set_mic_level - set mic level (on vxpocket only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * @level: the mic level = 0 - 8 (max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) void vx_set_mic_level(struct vx_core *chip, int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct snd_vxpocket *pchip = to_vxpocket(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (chip->chip_status & VX_STAT_IS_STALE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) mutex_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (pchip->regCDSP & VXP_CDSP_MIC_SEL_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) level = vx_compute_mic_level(level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) vx_outb(chip, MICRO, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) mutex_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * change the input audio source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static void vxp_change_audio_source(struct vx_core *_chip, int src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct snd_vxpocket *chip = to_vxpocket(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) switch (src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) case VX_AUDIO_SRC_DIGITAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) chip->regCDSP |= VXP_CDSP_DATAIN_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) vx_outb(chip, CDSP, chip->regCDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case VX_AUDIO_SRC_LINE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) chip->regCDSP &= ~VXP_CDSP_DATAIN_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (_chip->type == VX_TYPE_VXP440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) chip->regCDSP &= ~P24_CDSP_MICS_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) chip->regCDSP &= ~VXP_CDSP_MIC_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) vx_outb(chip, CDSP, chip->regCDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) case VX_AUDIO_SRC_MIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) chip->regCDSP &= ~VXP_CDSP_DATAIN_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* reset mic levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (_chip->type == VX_TYPE_VXP440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) chip->regCDSP &= ~P24_CDSP_MICS_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (chip->mic_level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) chip->regCDSP |= P24_CDSP_MIC38_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) chip->regCDSP |= P24_CDSP_MIC20_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) vx_outb(chip, CDSP, chip->regCDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) chip->regCDSP |= VXP_CDSP_MIC_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) vx_outb(chip, CDSP, chip->regCDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) vx_outb(chip, MICRO, vx_compute_mic_level(chip->mic_level));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * change the clock source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * source = INTERNAL_QUARTZ or UER_SYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static void vxp_set_clock_source(struct vx_core *_chip, int source)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct snd_vxpocket *chip = to_vxpocket(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (source == INTERNAL_QUARTZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) chip->regCDSP &= ~VXP_CDSP_CLOCKIN_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) chip->regCDSP |= VXP_CDSP_CLOCKIN_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) vx_outb(chip, CDSP, chip->regCDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * reset the board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static void vxp_reset_board(struct vx_core *_chip, int cold_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct snd_vxpocket *chip = to_vxpocket(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) chip->regCDSP = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) chip->regDIALOG = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) const struct snd_vx_ops snd_vxpocket_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .in8 = vxp_inb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .out8 = vxp_outb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .test_and_ack = vxp_test_and_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .validate_irq = vxp_validate_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .write_codec = vxp_write_codec_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .reset_codec = vxp_reset_codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .change_audio_source = vxp_change_audio_source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .set_clock_source = vxp_set_clock_source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .load_dsp = vxp_load_dsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .add_controls = vxp_add_mic_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .reset_dsp = vxp_reset_dsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .reset_board = vxp_reset_board,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .dma_write = vxp_dma_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .dma_read = vxp_dma_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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