^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Sound Cors PDAudioCF soundcard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2003 by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __PDAUDIOCF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __PDAUDIOCF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <pcmcia/cistpl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <pcmcia/ds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/ak4117.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* PDAUDIOCF registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PDAUDIOCF_REG_MD 0x00 /* music data, R/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PDAUDIOCF_REG_WDP 0x02 /* write data pointer / 2, R/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PDAUDIOCF_REG_RDP 0x04 /* read data pointer / 2, R/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PDAUDIOCF_REG_TCR 0x06 /* test control register W/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PDAUDIOCF_REG_SCR 0x08 /* status and control, R/W (see bit description) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PDAUDIOCF_REG_ISR 0x0a /* interrupt status, R/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PDAUDIOCF_REG_IER 0x0c /* interrupt enable, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PDAUDIOCF_REG_AK_IFR 0x0e /* AK interface register, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* PDAUDIOCF_REG_TCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PDAUDIOCF_ELIMAKMBIT (1<<0) /* simulate AKM music data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PDAUDIOCF_TESTDATASEL (1<<1) /* test data selection, 0 = 0x55, 1 = pseudo-random */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* PDAUDIOCF_REG_SCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PDAUDIOCF_AK_SBP (1<<0) /* serial port busy flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PDAUDIOCF_RST (1<<2) /* FPGA, AKM + SRAM buffer reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PDAUDIOCF_PDN (1<<3) /* power down bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PDAUDIOCF_CLKDIV0 (1<<4) /* choose 24.576Mhz clock divided by 1,2,3 or 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PDAUDIOCF_CLKDIV1 (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PDAUDIOCF_RECORD (1<<6) /* start capturing to SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PDAUDIOCF_AK_SDD (1<<7) /* music data detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PDAUDIOCF_RED_LED_OFF (1<<8) /* red LED off override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PDAUDIOCF_BLUE_LED_OFF (1<<9) /* blue LED off override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PDAUDIOCF_DATAFMT0 (1<<10) /* data format bits: 00 = 16-bit, 01 = 18-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PDAUDIOCF_DATAFMT1 (1<<11) /* 10 = 20-bit, 11 = 24-bit, all right justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PDAUDIOCF_FPGAREV(x) ((x>>12)&0x0f) /* FPGA revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* PDAUDIOCF_REG_ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PDAUDIOCF_IRQLVL (1<<0) /* Buffer level IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PDAUDIOCF_IRQOVR (1<<1) /* Overrun IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PDAUDIOCF_IRQAKM (1<<2) /* AKM IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* PDAUDIOCF_REG_IER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PDAUDIOCF_IRQLVLEN0 (1<<0) /* fill threshold levels; 00 = none, 01 = 1/8th of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PDAUDIOCF_IRQLVLEN1 (1<<1) /* 10 = 1/4th of buffer, 11 = 1/2th of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PDAUDIOCF_IRQOVREN (1<<2) /* enable overrun IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PDAUDIOCF_IRQAKMEN (1<<3) /* enable AKM IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PDAUDIOCF_BLUEDUTY0 (1<<8) /* blue LED duty cycle; 00 = 100%, 01 = 50% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PDAUDIOCF_BLUEDUTY1 (1<<9) /* 02 = 25%, 11 = 12% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PDAUDIOCF_REDDUTY0 (1<<10) /* red LED duty cycle; 00 = 100%, 01 = 50% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PDAUDIOCF_REDDUTY1 (1<<11) /* 02 = 25%, 11 = 12% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PDAUDIOCF_BLUESDD (1<<12) /* blue LED against SDD bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PDAUDIOCF_BLUEMODULATE (1<<13) /* save power when 100% duty cycle selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PDAUDIOCF_REDMODULATE (1<<14) /* save power when 100% duty cycle selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PDAUDIOCF_HALFRATE (1<<15) /* slow both LED blinks by half (also spdif detect rate) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* chip status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PDAUDIOCF_STAT_IS_STALE (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PDAUDIOCF_STAT_IS_CONFIGURED (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PDAUDIOCF_STAT_IS_SUSPENDED (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct snd_pdacf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned long port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct mutex reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned short regmap[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned short suspend_reg_scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) spinlock_t ak4117_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct ak4117 *ak4117;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int chip_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct snd_pcm_substream *pcm_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int pcm_running: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int pcm_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int pcm_swab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int pcm_little;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int pcm_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int pcm_sample;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int pcm_xor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int pcm_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int pcm_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int pcm_tdone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int pcm_hwptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void *pcm_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* pcmcia stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct pcmcia_device *p_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static inline void pdacf_reg_write(struct snd_pdacf *chip, unsigned char reg, unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) outw(chip->regmap[reg>>1] = val, chip->port + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static inline unsigned short pdacf_reg_read(struct snd_pdacf *chip, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return inw(chip->port + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct snd_pdacf *snd_pdacf_create(struct snd_card *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int snd_pdacf_ak4117_create(struct snd_pdacf *pdacf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void snd_pdacf_powerdown(struct snd_pdacf *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int snd_pdacf_suspend(struct snd_pdacf *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int snd_pdacf_resume(struct snd_pdacf *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int snd_pdacf_pcm_new(struct snd_pdacf *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) irqreturn_t pdacf_interrupt(int irq, void *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) irqreturn_t pdacf_threaded_irq(int irq, void *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void pdacf_reinit(struct snd_pdacf *chip, int resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif /* __PDAUDIOCF_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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