^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Routines for control of YMF724/740/744/754 chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "ymfpci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/asoundef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/mpu401.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * common I/O routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static inline u8 snd_ymfpci_readb(struct snd_ymfpci *chip, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return readb(chip->reg_area_virt + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static inline void snd_ymfpci_writeb(struct snd_ymfpci *chip, u32 offset, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) writeb(val, chip->reg_area_virt + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static inline u16 snd_ymfpci_readw(struct snd_ymfpci *chip, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return readw(chip->reg_area_virt + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static inline void snd_ymfpci_writew(struct snd_ymfpci *chip, u32 offset, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) writew(val, chip->reg_area_virt + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static inline u32 snd_ymfpci_readl(struct snd_ymfpci *chip, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return readl(chip->reg_area_virt + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline void snd_ymfpci_writel(struct snd_ymfpci *chip, u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) writel(val, chip->reg_area_virt + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int snd_ymfpci_codec_ready(struct snd_ymfpci *chip, int secondary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned long end_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 reg = secondary ? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) end_time = jiffies + msecs_to_jiffies(750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if ((snd_ymfpci_readw(chip, reg) & 0x8000) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) } while (time_before(jiffies, end_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "codec_ready: codec %i is not ready [0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) secondary, snd_ymfpci_readw(chip, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void snd_ymfpci_codec_write(struct snd_ac97 *ac97, u16 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct snd_ymfpci *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) snd_ymfpci_codec_ready(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) cmd = ((YDSXG_AC97WRITECMD | reg) << 16) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) snd_ymfpci_writel(chip, YDSXGR_AC97CMDDATA, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static u16 snd_ymfpci_codec_read(struct snd_ac97 *ac97, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct snd_ymfpci *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (snd_ymfpci_codec_ready(chip, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) snd_ymfpci_writew(chip, YDSXGR_AC97CMDADR, YDSXG_AC97READCMD | reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (snd_ymfpci_codec_ready(chip, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (chip->device_id == PCI_DEVICE_ID_YAMAHA_744 && chip->rev < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) for (i = 0; i < 600; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Misc routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static u32 snd_ymfpci_calc_delta(u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) case 8000: return 0x02aaab00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case 11025: return 0x03accd00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case 16000: return 0x05555500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case 22050: return 0x07599a00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case 32000: return 0x0aaaab00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case 44100: return 0x0eb33300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) default: return ((rate << 16) / 375) << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const u32 def_rate[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 100, 2000, 8000, 11025, 16000, 22050, 32000, 48000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static u32 snd_ymfpci_calc_lpfK(u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const u32 val[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 0x00570000, 0x06AA0000, 0x18B20000, 0x20930000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 0x2B9A0000, 0x35A10000, 0x3EAA0000, 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (rate == 44100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0x40000000; /* FIXME: What's the right value? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (rate <= def_rate[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return val[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return val[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static u32 snd_ymfpci_calc_lpfQ(u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const u32 val[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 0x35280000, 0x34A70000, 0x32020000, 0x31770000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 0x31390000, 0x31C90000, 0x33D00000, 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (rate == 44100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0x370A0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (rate <= def_rate[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return val[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return val[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Hardware start management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void snd_ymfpci_hw_start(struct snd_ymfpci *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (chip->start_count++ > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) goto __end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) snd_ymfpci_writel(chip, YDSXGR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) snd_ymfpci_readl(chip, YDSXGR_MODE) | 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void snd_ymfpci_hw_stop(struct snd_ymfpci *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) long timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (--chip->start_count > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) goto __end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) snd_ymfpci_writel(chip, YDSXGR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) snd_ymfpci_readl(chip, YDSXGR_MODE) & ~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) while (timeout-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if ((snd_ymfpci_readl(chip, YDSXGR_STATUS) & 2) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (atomic_read(&chip->interrupt_sleep_count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) atomic_set(&chip->interrupt_sleep_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) wake_up(&chip->interrupt_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * Playback voice management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int voice_alloc(struct snd_ymfpci *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) enum snd_ymfpci_voice_type type, int pair,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct snd_ymfpci_voice **rvoice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct snd_ymfpci_voice *voice, *voice2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) *rvoice = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) for (idx = 0; idx < YDSXG_PLAYBACK_VOICES; idx += pair ? 2 : 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) voice = &chip->voices[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) voice2 = pair ? &chip->voices[idx+1] : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (voice->use || (voice2 && voice2->use))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) voice->use = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (voice2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) voice2->use = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case YMFPCI_PCM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) voice->pcm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (voice2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) voice2->pcm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case YMFPCI_SYNTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) voice->synth = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case YMFPCI_MIDI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) voice->midi = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) snd_ymfpci_hw_start(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (voice2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) snd_ymfpci_hw_start(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *rvoice = voice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int snd_ymfpci_voice_alloc(struct snd_ymfpci *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) enum snd_ymfpci_voice_type type, int pair,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct snd_ymfpci_voice **rvoice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (snd_BUG_ON(!rvoice))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (snd_BUG_ON(pair && type != YMFPCI_PCM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) spin_lock_irqsave(&chip->voice_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) result = voice_alloc(chip, type, pair, rvoice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (result == 0 || type != YMFPCI_PCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* TODO: synth/midi voice deallocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) spin_unlock_irqrestore(&chip->voice_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int snd_ymfpci_voice_free(struct snd_ymfpci *chip, struct snd_ymfpci_voice *pvoice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (snd_BUG_ON(!pvoice))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) snd_ymfpci_hw_stop(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) spin_lock_irqsave(&chip->voice_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (pvoice->number == chip->src441_used) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) chip->src441_used = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) pvoice->ypcm->use_441_slot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pvoice->use = pvoice->pcm = pvoice->synth = pvoice->midi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pvoice->ypcm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pvoice->interrupt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) spin_unlock_irqrestore(&chip->voice_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * PCM part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void snd_ymfpci_pcm_interrupt(struct snd_ymfpci *chip, struct snd_ymfpci_voice *voice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct snd_ymfpci_pcm *ypcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 pos, delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if ((ypcm = voice->ypcm) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (ypcm->substream == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (ypcm->running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) pos = le32_to_cpu(voice->bank[chip->active_bank].start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (pos < ypcm->last_pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) delta = pos + (ypcm->buffer_size - ypcm->last_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) delta = pos - ypcm->last_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ypcm->period_pos += delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ypcm->last_pos = pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (ypcm->period_pos >= ypcm->period_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "done - active_bank = 0x%x, start = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) chip->active_bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) voice->bank[chip->active_bank].start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ypcm->period_pos %= ypcm->period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) snd_pcm_period_elapsed(ypcm->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (unlikely(ypcm->update_pcm_vol)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned int subs = ypcm->substream->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned int next_bank = 1 - chip->active_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct snd_ymfpci_playback_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) __le32 volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) bank = &voice->bank[next_bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) volume = cpu_to_le32(chip->pcm_mixer[subs].left << 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) bank->left_gain_end = volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (ypcm->output_rear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) bank->eff2_gain_end = volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (ypcm->voices[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) bank = &ypcm->voices[1]->bank[next_bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) volume = cpu_to_le32(chip->pcm_mixer[subs].right << 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) bank->right_gain_end = volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ypcm->output_rear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) bank->eff3_gain_end = volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ypcm->update_pcm_vol--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void snd_ymfpci_pcm_capture_interrupt(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct snd_ymfpci_pcm *ypcm = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct snd_ymfpci *chip = ypcm->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u32 pos, delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (ypcm->running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pos = le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (pos < ypcm->last_pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) delta = pos + (ypcm->buffer_size - ypcm->last_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) delta = pos - ypcm->last_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ypcm->period_pos += delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ypcm->last_pos = pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (ypcm->period_pos >= ypcm->period_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ypcm->period_pos %= ypcm->period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) "done - active_bank = 0x%x, start = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) chip->active_bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) voice->bank[chip->active_bank].start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) snd_pcm_period_elapsed(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int snd_ymfpci_playback_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct snd_kcontrol *kctl = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (ypcm->voices[0] == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) goto __unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) chip->ctrl_playback[ypcm->voices[0]->number + 1] = cpu_to_le32(ypcm->voices[0]->bank_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (ypcm->voices[1] != NULL && !ypcm->use_441_slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) chip->ctrl_playback[ypcm->voices[1]->number + 1] = cpu_to_le32(ypcm->voices[1]->bank_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ypcm->running = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (substream->pcm == chip->pcm && !ypcm->use_441_slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) kctl = chip->pcm_mixer[substream->number].ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) chip->ctrl_playback[ypcm->voices[0]->number + 1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (ypcm->voices[1] != NULL && !ypcm->use_441_slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) chip->ctrl_playback[ypcm->voices[1]->number + 1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ypcm->running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) __unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (kctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int snd_ymfpci_capture_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) | (1 << ypcm->capture_bank_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ypcm->running = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) & ~(1 << ypcm->capture_bank_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ypcm->running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int snd_ymfpci_pcm_voice_alloc(struct snd_ymfpci_pcm *ypcm, int voices)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (ypcm->voices[1] != NULL && voices < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ypcm->voices[1] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (voices == 1 && ypcm->voices[0] != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return 0; /* already allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (voices == 2 && ypcm->voices[0] != NULL && ypcm->voices[1] != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return 0; /* already allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (voices > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (ypcm->voices[0] != NULL && ypcm->voices[1] == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ypcm->voices[0] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) err = snd_ymfpci_voice_alloc(ypcm->chip, YMFPCI_PCM, voices > 1, &ypcm->voices[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ypcm->voices[0]->ypcm = ypcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ypcm->voices[0]->interrupt = snd_ymfpci_pcm_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (voices > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ypcm->voices[1] = &ypcm->chip->voices[ypcm->voices[0]->number + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ypcm->voices[1]->ypcm = ypcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static void snd_ymfpci_pcm_init_voice(struct snd_ymfpci_pcm *ypcm, unsigned int voiceidx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct snd_pcm_runtime *runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int has_pcm_volume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct snd_ymfpci_voice *voice = ypcm->voices[voiceidx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u32 delta = snd_ymfpci_calc_delta(runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u32 lpfQ = snd_ymfpci_calc_lpfQ(runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 lpfK = snd_ymfpci_calc_lpfK(runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct snd_ymfpci_playback_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) unsigned int nbank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) __le32 vol_left, vol_right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u8 use_left, use_right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (snd_BUG_ON(!voice))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (runtime->channels == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) use_left = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) use_right = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) use_left = (voiceidx & 1) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) use_right = !use_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (has_pcm_volume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) vol_left = cpu_to_le32(ypcm->chip->pcm_mixer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) [ypcm->substream->number].left << 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) vol_right = cpu_to_le32(ypcm->chip->pcm_mixer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) [ypcm->substream->number].right << 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) vol_left = cpu_to_le32(0x40000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) vol_right = cpu_to_le32(0x40000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) spin_lock_irqsave(&ypcm->chip->voice_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) format = runtime->channels == 2 ? 0x00010000 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (snd_pcm_format_width(runtime->format) == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) format |= 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) else if (ypcm->chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) runtime->rate == 44100 && runtime->channels == 2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) voiceidx == 0 && (ypcm->chip->src441_used == -1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ypcm->chip->src441_used == voice->number)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ypcm->chip->src441_used = voice->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ypcm->use_441_slot = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) format |= 0x10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (ypcm->chip->src441_used == voice->number &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) (format & 0x10000000) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ypcm->chip->src441_used = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ypcm->use_441_slot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (runtime->channels == 2 && (voiceidx & 1) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) format |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) spin_unlock_irqrestore(&ypcm->chip->voice_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) for (nbank = 0; nbank < 2; nbank++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) bank = &voice->bank[nbank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) memset(bank, 0, sizeof(*bank));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) bank->format = cpu_to_le32(format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) bank->base = cpu_to_le32(runtime->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) bank->loop_end = cpu_to_le32(ypcm->buffer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) bank->lpfQ = cpu_to_le32(lpfQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) bank->delta =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) bank->delta_end = cpu_to_le32(delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) bank->lpfK =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) bank->lpfK_end = cpu_to_le32(lpfK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) bank->eg_gain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) bank->eg_gain_end = cpu_to_le32(0x40000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (ypcm->output_front) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (use_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) bank->left_gain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) bank->left_gain_end = vol_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (use_right) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) bank->right_gain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) bank->right_gain_end = vol_right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (ypcm->output_rear) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!ypcm->swap_rear) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (use_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) bank->eff2_gain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) bank->eff2_gain_end = vol_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (use_right) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) bank->eff3_gain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) bank->eff3_gain_end = vol_right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* The SPDIF out channels seem to be swapped, so we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * to swap them here, too. The rear analog out channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * will be wrong, but otherwise AC3 would not work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (use_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) bank->eff3_gain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) bank->eff3_gain_end = vol_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (use_right) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) bank->eff2_gain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) bank->eff2_gain_end = vol_right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static int snd_ymfpci_ac3_init(struct snd_ymfpci *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 4096, &chip->ac3_tmp_base) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) chip->bank_effect[3][0]->base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) chip->bank_effect[3][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) chip->bank_effect[3][0]->loop_end =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) chip->bank_effect[3][1]->loop_end = cpu_to_le32(1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) chip->bank_effect[4][0]->base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) chip->bank_effect[4][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr + 2048);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) chip->bank_effect[4][0]->loop_end =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) chip->bank_effect[4][1]->loop_end = cpu_to_le32(1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) | 3 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static int snd_ymfpci_ac3_done(struct snd_ymfpci *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) & ~(3 << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) // snd_ymfpci_irq_wait(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (chip->ac3_tmp_base.area) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) snd_dma_free_pages(&chip->ac3_tmp_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) chip->ac3_tmp_base.area = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static int snd_ymfpci_playback_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct snd_ymfpci_pcm *ypcm = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if ((err = snd_ymfpci_pcm_voice_alloc(ypcm, params_channels(hw_params))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static int snd_ymfpci_playback_hw_free(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct snd_ymfpci_pcm *ypcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (runtime->private_data == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ypcm = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* wait, until the PCI operations are not finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) snd_ymfpci_irq_wait(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (ypcm->voices[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) snd_ymfpci_voice_free(chip, ypcm->voices[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ypcm->voices[1] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (ypcm->voices[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) snd_ymfpci_voice_free(chip, ypcm->voices[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ypcm->voices[0] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static int snd_ymfpci_playback_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct snd_ymfpci_pcm *ypcm = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) unsigned int nvoice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ypcm->period_size = runtime->period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ypcm->buffer_size = runtime->buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ypcm->period_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ypcm->last_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) for (nvoice = 0; nvoice < runtime->channels; nvoice++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) snd_ymfpci_pcm_init_voice(ypcm, nvoice, runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) substream->pcm == chip->pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (substream->pcm == chip->pcm && !ypcm->use_441_slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) kctl = chip->pcm_mixer[substream->number].ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static int snd_ymfpci_capture_hw_free(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* wait, until the PCI operations are not finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) snd_ymfpci_irq_wait(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static int snd_ymfpci_capture_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct snd_ymfpci_pcm *ypcm = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct snd_ymfpci_capture_bank * bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int nbank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) u32 rate, format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ypcm->period_size = runtime->period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ypcm->buffer_size = runtime->buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ypcm->period_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ypcm->last_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ypcm->shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) rate = ((48000 * 4096) / runtime->rate) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) format = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (runtime->channels == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) format |= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ypcm->shift++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (snd_pcm_format_width(runtime->format) == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) format |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ypcm->shift++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) switch (ypcm->capture_bank_number) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) snd_ymfpci_writel(chip, YDSXGR_RECFORMAT, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) snd_ymfpci_writel(chip, YDSXGR_RECSLOTSR, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) snd_ymfpci_writel(chip, YDSXGR_ADCFORMAT, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) snd_ymfpci_writel(chip, YDSXGR_ADCSLOTSR, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) for (nbank = 0; nbank < 2; nbank++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) bank = chip->bank_capture[ypcm->capture_bank_number][nbank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) bank->base = cpu_to_le32(runtime->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) bank->loop_end = cpu_to_le32(ypcm->buffer_size << ypcm->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) bank->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) bank->num_of_loops = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static snd_pcm_uframes_t snd_ymfpci_playback_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct snd_ymfpci_pcm *ypcm = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct snd_ymfpci_voice *voice = ypcm->voices[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (!(ypcm->running && voice))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return le32_to_cpu(voice->bank[chip->active_bank].start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static snd_pcm_uframes_t snd_ymfpci_capture_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct snd_ymfpci_pcm *ypcm = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (!ypcm->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) wait_queue_entry_t wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) int loops = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) while (loops-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if ((snd_ymfpci_readl(chip, YDSXGR_MODE) & 3) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) init_waitqueue_entry(&wait, current);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) add_wait_queue(&chip->interrupt_sleep, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) atomic_inc(&chip->interrupt_sleep_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) schedule_timeout_uninterruptible(msecs_to_jiffies(50));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) remove_wait_queue(&chip->interrupt_sleep, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static irqreturn_t snd_ymfpci_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct snd_ymfpci *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) u32 status, nvoice, mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct snd_ymfpci_voice *voice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) status = snd_ymfpci_readl(chip, YDSXGR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (status & 0x80000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) spin_lock(&chip->voice_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) for (nvoice = 0; nvoice < YDSXG_PLAYBACK_VOICES; nvoice++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) voice = &chip->voices[nvoice];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (voice->interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) voice->interrupt(chip, voice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) for (nvoice = 0; nvoice < YDSXG_CAPTURE_VOICES; nvoice++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (chip->capture_substream[nvoice])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) snd_ymfpci_pcm_capture_interrupt(chip->capture_substream[nvoice]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) for (nvoice = 0; nvoice < YDSXG_EFFECT_VOICES; nvoice++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (chip->effect_substream[nvoice])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) snd_ymfpci_pcm_effect_interrupt(chip->effect_substream[nvoice]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) spin_unlock(&chip->voice_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) snd_ymfpci_writel(chip, YDSXGR_STATUS, 0x80000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) mode = snd_ymfpci_readl(chip, YDSXGR_MODE) | 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) snd_ymfpci_writel(chip, YDSXGR_MODE, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (atomic_read(&chip->interrupt_sleep_count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) atomic_set(&chip->interrupt_sleep_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) wake_up(&chip->interrupt_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) status = snd_ymfpci_readw(chip, YDSXGR_INTFLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (status & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (chip->timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) snd_timer_interrupt(chip->timer, chip->timer_ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) snd_ymfpci_writew(chip, YDSXGR_INTFLAG, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (chip->rawmidi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) snd_mpu401_uart_interrupt(irq, chip->rawmidi->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static const struct snd_pcm_hardware snd_ymfpci_playback =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .info = (SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) SNDRV_PCM_INFO_RESUME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .period_bytes_max = 256 * 1024, /* FIXME: enough? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .periods_min = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static const struct snd_pcm_hardware snd_ymfpci_capture =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .info = (SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) SNDRV_PCM_INFO_RESUME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .period_bytes_max = 256 * 1024, /* FIXME: enough? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .periods_min = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static void snd_ymfpci_pcm_free_substream(struct snd_pcm_runtime *runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) kfree(runtime->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static int snd_ymfpci_playback_open_1(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct snd_ymfpci_pcm *ypcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) runtime->hw = snd_ymfpci_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* FIXME? True value is 256/48 = 5.33333 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) err = snd_pcm_hw_constraint_minmax(runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) SNDRV_PCM_HW_PARAM_PERIOD_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) 5334, UINT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) err = snd_pcm_hw_rule_noresample(runtime, 48000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (ypcm == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ypcm->chip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ypcm->type = PLAYBACK_VOICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ypcm->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) runtime->private_data = ypcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) runtime->private_free = snd_ymfpci_pcm_free_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /* call with spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static void ymfpci_open_extension(struct snd_ymfpci *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (! chip->rear_opened) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (! chip->spdif_opened) /* set AC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) snd_ymfpci_writel(chip, YDSXGR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) snd_ymfpci_readl(chip, YDSXGR_MODE) | (1 << 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* enable second codec (4CHEN) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) | 0x0010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* call with spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static void ymfpci_close_extension(struct snd_ymfpci *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (! chip->rear_opened) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (! chip->spdif_opened)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) snd_ymfpci_writel(chip, YDSXGR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) snd_ymfpci_readl(chip, YDSXGR_MODE) & ~(1 << 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) & ~0x0010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static int snd_ymfpci_playback_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct snd_ymfpci_pcm *ypcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ypcm = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) ypcm->output_front = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ypcm->output_rear = chip->mode_dup4ch ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ypcm->swap_rear = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (ypcm->output_rear) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ymfpci_open_extension(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) chip->rear_opened++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static int snd_ymfpci_playback_spdif_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct snd_ymfpci_pcm *ypcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ypcm = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ypcm->output_front = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) ypcm->output_rear = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ypcm->swap_rear = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) | 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ymfpci_open_extension(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) chip->spdif_pcm_bits = chip->spdif_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) chip->spdif_opened++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) chip->spdif_pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static int snd_ymfpci_playback_4ch_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct snd_ymfpci_pcm *ypcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ypcm = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ypcm->output_front = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ypcm->output_rear = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ypcm->swap_rear = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ymfpci_open_extension(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) chip->rear_opened++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static int snd_ymfpci_capture_open(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) u32 capture_bank_number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct snd_ymfpci_pcm *ypcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) runtime->hw = snd_ymfpci_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* FIXME? True value is 256/48 = 5.33333 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) err = snd_pcm_hw_constraint_minmax(runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) SNDRV_PCM_HW_PARAM_PERIOD_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) 5334, UINT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) err = snd_pcm_hw_rule_noresample(runtime, 48000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (ypcm == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ypcm->chip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ypcm->type = capture_bank_number + CAPTURE_REC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) ypcm->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ypcm->capture_bank_number = capture_bank_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) chip->capture_substream[capture_bank_number] = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) runtime->private_data = ypcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) runtime->private_free = snd_ymfpci_pcm_free_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) snd_ymfpci_hw_start(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static int snd_ymfpci_capture_rec_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return snd_ymfpci_capture_open(substream, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static int snd_ymfpci_capture_ac97_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return snd_ymfpci_capture_open(substream, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static int snd_ymfpci_playback_close_1(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static int snd_ymfpci_playback_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (ypcm->output_rear && chip->rear_opened > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) chip->rear_opened--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ymfpci_close_extension(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return snd_ymfpci_playback_close_1(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static int snd_ymfpci_playback_spdif_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) chip->spdif_opened = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ymfpci_close_extension(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & ~2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) chip->spdif_pcm_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return snd_ymfpci_playback_close_1(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static int snd_ymfpci_playback_4ch_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (chip->rear_opened > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) chip->rear_opened--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ymfpci_close_extension(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return snd_ymfpci_playback_close_1(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static int snd_ymfpci_capture_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) struct snd_ymfpci_pcm *ypcm = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (ypcm != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) chip->capture_substream[ypcm->capture_bank_number] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) snd_ymfpci_hw_stop(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) static const struct snd_pcm_ops snd_ymfpci_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .open = snd_ymfpci_playback_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .close = snd_ymfpci_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .hw_params = snd_ymfpci_playback_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .hw_free = snd_ymfpci_playback_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .prepare = snd_ymfpci_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .trigger = snd_ymfpci_playback_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .pointer = snd_ymfpci_playback_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static const struct snd_pcm_ops snd_ymfpci_capture_rec_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .open = snd_ymfpci_capture_rec_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .close = snd_ymfpci_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .hw_free = snd_ymfpci_capture_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .prepare = snd_ymfpci_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .trigger = snd_ymfpci_capture_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .pointer = snd_ymfpci_capture_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) int snd_ymfpci_pcm(struct snd_ymfpci *chip, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if ((err = snd_pcm_new(chip->card, "YMFPCI", device, 32, 1, &pcm)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_rec_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* global setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) strcpy(pcm->name, "YMFPCI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) chip->pcm = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) &chip->pci->dev, 64*1024, 256*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) snd_pcm_std_chmaps, 2, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static const struct snd_pcm_ops snd_ymfpci_capture_ac97_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .open = snd_ymfpci_capture_ac97_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .close = snd_ymfpci_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .hw_free = snd_ymfpci_capture_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .prepare = snd_ymfpci_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .trigger = snd_ymfpci_capture_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .pointer = snd_ymfpci_capture_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) int snd_ymfpci_pcm2(struct snd_ymfpci *chip, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if ((err = snd_pcm_new(chip->card, "YMFPCI - PCM2", device, 0, 1, &pcm)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_ac97_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* global setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) sprintf(pcm->name, "YMFPCI - %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) chip->device_id == PCI_DEVICE_ID_YAMAHA_754 ? "Direct Recording" : "AC'97");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) chip->pcm2 = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) &chip->pci->dev, 64*1024, 256*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) static const struct snd_pcm_ops snd_ymfpci_playback_spdif_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .open = snd_ymfpci_playback_spdif_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .close = snd_ymfpci_playback_spdif_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .hw_params = snd_ymfpci_playback_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .hw_free = snd_ymfpci_playback_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .prepare = snd_ymfpci_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .trigger = snd_ymfpci_playback_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .pointer = snd_ymfpci_playback_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) int snd_ymfpci_pcm_spdif(struct snd_ymfpci *chip, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if ((err = snd_pcm_new(chip->card, "YMFPCI - IEC958", device, 1, 0, &pcm)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_spdif_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* global setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) strcpy(pcm->name, "YMFPCI - IEC958");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) chip->pcm_spdif = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) &chip->pci->dev, 64*1024, 256*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static const struct snd_pcm_ops snd_ymfpci_playback_4ch_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .open = snd_ymfpci_playback_4ch_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .close = snd_ymfpci_playback_4ch_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .hw_params = snd_ymfpci_playback_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .hw_free = snd_ymfpci_playback_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .prepare = snd_ymfpci_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .trigger = snd_ymfpci_playback_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .pointer = snd_ymfpci_playback_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static const struct snd_pcm_chmap_elem surround_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) { .channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .map = { SNDRV_CHMAP_MONO } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) { .channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) int snd_ymfpci_pcm_4ch(struct snd_ymfpci *chip, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if ((err = snd_pcm_new(chip->card, "YMFPCI - Rear", device, 1, 0, &pcm)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_4ch_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /* global setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) strcpy(pcm->name, "YMFPCI - Rear PCM");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) chip->pcm_4ch = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) &chip->pci->dev, 64*1024, 256*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) return snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) surround_map, 2, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static int snd_ymfpci_spdif_default_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static int snd_ymfpci_spdif_default_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) ucontrol->value.iec958.status[0] = (chip->spdif_bits >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) ucontrol->value.iec958.status[1] = (chip->spdif_bits >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static int snd_ymfpci_spdif_default_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) (ucontrol->value.iec958.status[1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) change = chip->spdif_bits != val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) chip->spdif_bits = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 1) && chip->pcm_spdif == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) static const struct snd_kcontrol_new snd_ymfpci_spdif_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .info = snd_ymfpci_spdif_default_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .get = snd_ymfpci_spdif_default_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .put = snd_ymfpci_spdif_default_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static int snd_ymfpci_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static int snd_ymfpci_spdif_mask_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) ucontrol->value.iec958.status[0] = 0x3e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ucontrol->value.iec958.status[1] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static const struct snd_kcontrol_new snd_ymfpci_spdif_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .info = snd_ymfpci_spdif_mask_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .get = snd_ymfpci_spdif_mask_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) static int snd_ymfpci_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static int snd_ymfpci_spdif_stream_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ucontrol->value.iec958.status[0] = (chip->spdif_pcm_bits >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ucontrol->value.iec958.status[1] = (chip->spdif_pcm_bits >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static int snd_ymfpci_spdif_stream_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) (ucontrol->value.iec958.status[1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) change = chip->spdif_pcm_bits != val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) chip->spdif_pcm_bits = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) static const struct snd_kcontrol_new snd_ymfpci_spdif_stream =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .info = snd_ymfpci_spdif_stream_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .get = snd_ymfpci_spdif_stream_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .put = snd_ymfpci_spdif_stream_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static int snd_ymfpci_drec_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) static const char *const texts[3] = {"AC'97", "IEC958", "ZV Port"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return snd_ctl_enum_info(info, 1, 3, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static int snd_ymfpci_drec_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (!(reg & 0x100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) value->value.enumerated.item[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) value->value.enumerated.item[0] = 1 + ((reg & 0x200) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static int snd_ymfpci_drec_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) u16 reg, old_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) old_reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (value->value.enumerated.item[0] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) reg = old_reg & ~0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) reg = (old_reg & ~0x300) | 0x100 | ((value->value.enumerated.item[0] == 2) << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) return reg != old_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) static const struct snd_kcontrol_new snd_ymfpci_drec_source = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .name = "Direct Recording Source",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .info = snd_ymfpci_drec_source_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .get = snd_ymfpci_drec_source_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .put = snd_ymfpci_drec_source_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) * Mixer controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #define YMFPCI_SINGLE(xname, xindex, reg, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .info = snd_ymfpci_info_single, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .get = snd_ymfpci_get_single, .put = snd_ymfpci_put_single, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .private_value = ((reg) | ((shift) << 16)) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #define snd_ymfpci_info_single snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static int snd_ymfpci_get_single(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) int reg = kcontrol->private_value & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) unsigned int mask = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) case YDSXGR_SPDIFOUTCTRL: break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) case YDSXGR_SPDIFINCTRL: break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) default: return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) ucontrol->value.integer.value[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) (snd_ymfpci_readl(chip, reg) >> shift) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) static int snd_ymfpci_put_single(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) int reg = kcontrol->private_value & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) unsigned int mask = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) unsigned int val, oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) case YDSXGR_SPDIFOUTCTRL: break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) case YDSXGR_SPDIFINCTRL: break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) default: return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) val = (ucontrol->value.integer.value[0] & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) val <<= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) oval = snd_ymfpci_readl(chip, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) val = (oval & ~(mask << shift)) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) change = val != oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) snd_ymfpci_writel(chip, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static const DECLARE_TLV_DB_LINEAR(db_scale_native, TLV_DB_GAIN_MUTE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #define YMFPCI_DOUBLE(xname, xindex, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .info = snd_ymfpci_info_double, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .get = snd_ymfpci_get_double, .put = snd_ymfpci_put_double, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .private_value = reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .tlv = { .p = db_scale_native } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static int snd_ymfpci_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) unsigned int reg = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (reg < 0x80 || reg >= 0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) uinfo->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) uinfo->value.integer.max = 16383;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) static int snd_ymfpci_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) unsigned int reg = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) unsigned int shift_left = 0, shift_right = 16, mask = 16383;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) if (reg < 0x80 || reg >= 0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) val = snd_ymfpci_readl(chip, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) ucontrol->value.integer.value[0] = (val >> shift_left) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) ucontrol->value.integer.value[1] = (val >> shift_right) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) static int snd_ymfpci_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) unsigned int reg = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) unsigned int shift_left = 0, shift_right = 16, mask = 16383;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) unsigned int val1, val2, oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) if (reg < 0x80 || reg >= 0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) val1 = ucontrol->value.integer.value[0] & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) val2 = ucontrol->value.integer.value[1] & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) val1 <<= shift_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) val2 <<= shift_right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) oval = snd_ymfpci_readl(chip, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) val1 = (oval & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) change = val1 != oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) snd_ymfpci_writel(chip, reg, val1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static int snd_ymfpci_put_nativedacvol(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) unsigned int reg = YDSXGR_NATIVEDACOUTVOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) unsigned int reg2 = YDSXGR_BUF441OUTVOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) unsigned int value, oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) value = ucontrol->value.integer.value[0] & 0x3fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) value |= (ucontrol->value.integer.value[1] & 0x3fff) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) oval = snd_ymfpci_readl(chip, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) change = value != oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) snd_ymfpci_writel(chip, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) snd_ymfpci_writel(chip, reg2, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) * 4ch duplication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) #define snd_ymfpci_info_dup4ch snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static int snd_ymfpci_get_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) ucontrol->value.integer.value[0] = chip->mode_dup4ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) static int snd_ymfpci_put_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) change = (ucontrol->value.integer.value[0] != chip->mode_dup4ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) chip->mode_dup4ch = !!ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) static const struct snd_kcontrol_new snd_ymfpci_dup4ch = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .name = "4ch Duplication",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .info = snd_ymfpci_info_dup4ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .get = snd_ymfpci_get_dup4ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .put = snd_ymfpci_put_dup4ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static const struct snd_kcontrol_new snd_ymfpci_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .name = "Wave Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) SNDRV_CTL_ELEM_ACCESS_TLV_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .info = snd_ymfpci_info_double,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .get = snd_ymfpci_get_double,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .put = snd_ymfpci_put_nativedacvol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .private_value = YDSXGR_NATIVEDACOUTVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .tlv = { .p = db_scale_native },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) YMFPCI_DOUBLE("Wave Capture Volume", 0, YDSXGR_NATIVEDACLOOPVOL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) YMFPCI_DOUBLE("Digital Capture Volume", 0, YDSXGR_NATIVEDACINVOL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) YMFPCI_DOUBLE("Digital Capture Volume", 1, YDSXGR_NATIVEADCINVOL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) YMFPCI_DOUBLE("ADC Playback Volume", 0, YDSXGR_PRIADCOUTVOL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) YMFPCI_DOUBLE("ADC Capture Volume", 0, YDSXGR_PRIADCLOOPVOL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) YMFPCI_DOUBLE("ADC Playback Volume", 1, YDSXGR_SECADCOUTVOL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) YMFPCI_DOUBLE("ADC Capture Volume", 1, YDSXGR_SECADCLOOPVOL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) YMFPCI_DOUBLE("FM Legacy Playback Volume", 0, YDSXGR_LEGACYOUTVOL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ", PLAYBACK,VOLUME), 0, YDSXGR_ZVOUTVOL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("", CAPTURE,VOLUME), 0, YDSXGR_ZVLOOPVOL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ",PLAYBACK,VOLUME), 1, YDSXGR_SPDIFOUTVOL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,VOLUME), 1, YDSXGR_SPDIFLOOPVOL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), 0, YDSXGR_SPDIFOUTCTRL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), 0, YDSXGR_SPDIFINCTRL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("Loop",NONE,NONE), 0, YDSXGR_SPDIFINCTRL, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) * GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) static int snd_ymfpci_get_gpio_out(struct snd_ymfpci *chip, int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) u16 reg, mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) reg &= ~(1 << (pin + 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) reg |= (1 << pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) /* set the level mode for input line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) mode = snd_ymfpci_readw(chip, YDSXGR_GPIOTYPECONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) mode &= ~(3 << (pin * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) snd_ymfpci_writew(chip, YDSXGR_GPIOTYPECONFIG, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) mode = snd_ymfpci_readw(chip, YDSXGR_GPIOINSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) return (mode >> pin) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) static int snd_ymfpci_set_gpio_out(struct snd_ymfpci *chip, int pin, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) reg &= ~(1 << pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) reg &= ~(1 << (pin + 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) snd_ymfpci_writew(chip, YDSXGR_GPIOOUTCTRL, enable << pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) #define snd_ymfpci_gpio_sw_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) static int snd_ymfpci_gpio_sw_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) int pin = (int)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) static int snd_ymfpci_gpio_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) int pin = (int)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (snd_ymfpci_get_gpio_out(chip, pin) != ucontrol->value.integer.value[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) snd_ymfpci_set_gpio_out(chip, pin, !!ucontrol->value.integer.value[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) static const struct snd_kcontrol_new snd_ymfpci_rear_shared = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .name = "Shared Rear/Line-In Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .info = snd_ymfpci_gpio_sw_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .get = snd_ymfpci_gpio_sw_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .put = snd_ymfpci_gpio_sw_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .private_value = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) * PCM voice volume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) static int snd_ymfpci_pcm_vol_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) uinfo->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) uinfo->value.integer.max = 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) static int snd_ymfpci_pcm_vol_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) unsigned int subs = kcontrol->id.subdevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) ucontrol->value.integer.value[0] = chip->pcm_mixer[subs].left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) ucontrol->value.integer.value[1] = chip->pcm_mixer[subs].right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) static int snd_ymfpci_pcm_vol_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) unsigned int subs = kcontrol->id.subdevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (ucontrol->value.integer.value[0] != chip->pcm_mixer[subs].left ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) ucontrol->value.integer.value[1] != chip->pcm_mixer[subs].right) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) chip->pcm_mixer[subs].left = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) chip->pcm_mixer[subs].right = ucontrol->value.integer.value[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (chip->pcm_mixer[subs].left > 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) chip->pcm_mixer[subs].left = 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if (chip->pcm_mixer[subs].right > 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) chip->pcm_mixer[subs].right = 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) substream = (struct snd_pcm_substream *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) spin_lock_irqsave(&chip->voice_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) if (substream->runtime && substream->runtime->private_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (!ypcm->use_441_slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) ypcm->update_pcm_vol = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) spin_unlock_irqrestore(&chip->voice_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) static const struct snd_kcontrol_new snd_ymfpci_pcm_volume = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .name = "PCM Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) SNDRV_CTL_ELEM_ACCESS_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .info = snd_ymfpci_pcm_vol_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .get = snd_ymfpci_pcm_vol_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .put = snd_ymfpci_pcm_vol_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) * Mixer routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) static void snd_ymfpci_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) struct snd_ymfpci *chip = bus->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) chip->ac97_bus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) static void snd_ymfpci_mixer_free_ac97(struct snd_ac97 *ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) struct snd_ymfpci *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) chip->ac97 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) int snd_ymfpci_mixer(struct snd_ymfpci *chip, int rear_switch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) struct snd_ac97_template ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static const struct snd_ac97_bus_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .write = snd_ymfpci_codec_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .read = snd_ymfpci_codec_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) chip->ac97_bus->private_free = snd_ymfpci_mixer_free_ac97_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) chip->ac97_bus->no_vra = 1; /* YMFPCI doesn't need VRA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) memset(&ac97, 0, sizeof(ac97));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) ac97.private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) ac97.private_free = snd_ymfpci_mixer_free_ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) /* to be sure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) snd_ac97_update_bits(chip->ac97, AC97_EXTENDED_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) AC97_EA_VRA|AC97_EA_VRM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) for (idx = 0; idx < ARRAY_SIZE(snd_ymfpci_controls); idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_controls[idx], chip))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) if (chip->ac97->ext_id & AC97_EI_SDAC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) kctl = snd_ctl_new1(&snd_ymfpci_dup4ch, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) err = snd_ctl_add(chip->card, kctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /* add S/PDIF control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (snd_BUG_ON(!chip->pcm_spdif))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_default, chip))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) kctl->id.device = chip->pcm_spdif->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_mask, chip))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) kctl->id.device = chip->pcm_spdif->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_stream, chip))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) kctl->id.device = chip->pcm_spdif->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) chip->spdif_pcm_ctl = kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) /* direct recording source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) if (chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) (err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_drec_source, chip))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) * shared rear/line-in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) if (rear_switch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_rear_shared, chip))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /* per-voice volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) substream = chip->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) for (idx = 0; idx < 32; ++idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) kctl = snd_ctl_new1(&snd_ymfpci_pcm_volume, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) if (!kctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) kctl->id.device = chip->pcm->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) kctl->id.subdevice = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) kctl->private_value = (unsigned long)substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) if ((err = snd_ctl_add(chip->card, kctl)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) chip->pcm_mixer[idx].left = 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) chip->pcm_mixer[idx].right = 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) chip->pcm_mixer[idx].ctl = kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) substream = substream->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) * timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) static int snd_ymfpci_timer_start(struct snd_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) struct snd_ymfpci *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) chip = snd_timer_chip(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) if (timer->sticks > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) chip->timer_ticks = timer->sticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) count = timer->sticks - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) * Divisor 1 is not allowed; fake it by using divisor 2 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) * counting two ticks for each interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) chip->timer_ticks = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) count = 2 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) snd_ymfpci_writew(chip, YDSXGR_TIMERCOUNT, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) static int snd_ymfpci_timer_stop(struct snd_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) struct snd_ymfpci *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) chip = snd_timer_chip(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) static int snd_ymfpci_timer_precise_resolution(struct snd_timer *timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) unsigned long *num, unsigned long *den)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) *num = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) *den = 96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) static const struct snd_timer_hardware snd_ymfpci_timer_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .flags = SNDRV_TIMER_HW_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .resolution = 10417, /* 1 / 96 kHz = 10.41666...us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .ticks = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .start = snd_ymfpci_timer_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .stop = snd_ymfpci_timer_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .precise_resolution = snd_ymfpci_timer_precise_resolution,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) int snd_ymfpci_timer(struct snd_ymfpci *chip, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) struct snd_timer *timer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) struct snd_timer_id tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) tid.dev_class = SNDRV_TIMER_CLASS_CARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) tid.card = chip->card->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) tid.device = device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) tid.subdevice = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) if ((err = snd_timer_new(chip->card, "YMFPCI", &tid, &timer)) >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) strcpy(timer->name, "YMFPCI timer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) timer->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) timer->hw = snd_ymfpci_timer_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) chip->timer = timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) * proc interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) static void snd_ymfpci_proc_read(struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) struct snd_ymfpci *chip = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) snd_iprintf(buffer, "YMFPCI\n\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) for (i = 0; i <= YDSXGR_WORKBASE; i += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) snd_iprintf(buffer, "%04x: %04x\n", i, snd_ymfpci_readl(chip, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) static int snd_ymfpci_proc_init(struct snd_card *card, struct snd_ymfpci *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) return snd_card_ro_proc_new(card, "ymfpci", chip, snd_ymfpci_proc_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) * initialization routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) static void snd_ymfpci_aclink_reset(struct pci_dev * pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) pci_read_config_byte(pci, PCIR_DSXG_CTRL, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) #if 0 // force to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) if (cmd & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd | 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) pci_write_config_word(pci, PCIR_DSXG_PWRCTRL1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) pci_write_config_word(pci, PCIR_DSXG_PWRCTRL2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) static void snd_ymfpci_enable_dsp(struct snd_ymfpci *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) static void snd_ymfpci_disable_dsp(struct snd_ymfpci *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) int timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) val = snd_ymfpci_readl(chip, YDSXGR_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) while (timeout-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) val = snd_ymfpci_readl(chip, YDSXGR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) if ((val & 0x00000002) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) static int snd_ymfpci_request_firmware(struct snd_ymfpci *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) int err, is_1e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) err = request_firmware(&chip->dsp_microcode, "yamaha/ds1_dsp.fw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) &chip->pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) if (err >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) if (chip->dsp_microcode->size != YDSXG_DSPLENGTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) "DSP microcode has wrong size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) is_1e = chip->device_id == PCI_DEVICE_ID_YAMAHA_724F ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) chip->device_id == PCI_DEVICE_ID_YAMAHA_740C ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) chip->device_id == PCI_DEVICE_ID_YAMAHA_744 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) chip->device_id == PCI_DEVICE_ID_YAMAHA_754;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) name = is_1e ? "yamaha/ds1e_ctrl.fw" : "yamaha/ds1_ctrl.fw";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) err = request_firmware(&chip->controller_microcode, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) &chip->pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) if (err >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) if (chip->controller_microcode->size != YDSXG_CTRLLENGTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) "controller microcode has wrong size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) MODULE_FIRMWARE("yamaha/ds1_dsp.fw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) MODULE_FIRMWARE("yamaha/ds1_ctrl.fw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) MODULE_FIRMWARE("yamaha/ds1e_ctrl.fw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) static void snd_ymfpci_download_image(struct snd_ymfpci *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) u16 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) const __le32 *inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) snd_ymfpci_disable_dsp(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00010000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) /* setup DSP instruction code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) inst = (const __le32 *)chip->dsp_microcode->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) for (i = 0; i < YDSXG_DSPLENGTH / 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) snd_ymfpci_writel(chip, YDSXGR_DSPINSTRAM + (i << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) le32_to_cpu(inst[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) /* setup control instruction code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) inst = (const __le32 *)chip->controller_microcode->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) for (i = 0; i < YDSXG_CTRLLENGTH / 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) snd_ymfpci_writel(chip, YDSXGR_CTRLINSTRAM + (i << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) le32_to_cpu(inst[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) snd_ymfpci_enable_dsp(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) static int snd_ymfpci_memalloc(struct snd_ymfpci *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) long size, playback_ctrl_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) int voice, bank, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) u8 *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) dma_addr_t ptr_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) playback_ctrl_size = 4 + 4 * YDSXG_PLAYBACK_VOICES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) chip->bank_size_playback = snd_ymfpci_readl(chip, YDSXGR_PLAYCTRLSIZE) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) chip->bank_size_capture = snd_ymfpci_readl(chip, YDSXGR_RECCTRLSIZE) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) chip->bank_size_effect = snd_ymfpci_readl(chip, YDSXGR_EFFCTRLSIZE) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) chip->work_size = YDSXG_DEFAULT_WORK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) size = ALIGN(playback_ctrl_size, 0x100) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) ALIGN(chip->bank_size_playback * 2 * YDSXG_PLAYBACK_VOICES, 0x100) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) ALIGN(chip->bank_size_capture * 2 * YDSXG_CAPTURE_VOICES, 0x100) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) ALIGN(chip->bank_size_effect * 2 * YDSXG_EFFECT_VOICES, 0x100) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) chip->work_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) /* work_ptr must be aligned to 256 bytes, but it's already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) covered with the kernel page allocation mechanism */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) size, &chip->work_ptr) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) ptr = chip->work_ptr.area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) ptr_addr = chip->work_ptr.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) memset(ptr, 0, size); /* for sure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) chip->bank_base_playback = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) chip->bank_base_playback_addr = ptr_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) chip->ctrl_playback = (__le32 *)ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) chip->ctrl_playback[0] = cpu_to_le32(YDSXG_PLAYBACK_VOICES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) ptr += ALIGN(playback_ctrl_size, 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) ptr_addr += ALIGN(playback_ctrl_size, 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) for (voice = 0; voice < YDSXG_PLAYBACK_VOICES; voice++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) chip->voices[voice].number = voice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) chip->voices[voice].bank = (struct snd_ymfpci_playback_bank *)ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) chip->voices[voice].bank_addr = ptr_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) for (bank = 0; bank < 2; bank++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) chip->bank_playback[voice][bank] = (struct snd_ymfpci_playback_bank *)ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) ptr += chip->bank_size_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) ptr_addr += chip->bank_size_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) ptr_addr = ALIGN(ptr_addr, 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) chip->bank_base_capture = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) chip->bank_base_capture_addr = ptr_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) for (voice = 0; voice < YDSXG_CAPTURE_VOICES; voice++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) for (bank = 0; bank < 2; bank++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) chip->bank_capture[voice][bank] = (struct snd_ymfpci_capture_bank *)ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) ptr += chip->bank_size_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) ptr_addr += chip->bank_size_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) ptr_addr = ALIGN(ptr_addr, 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) chip->bank_base_effect = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) chip->bank_base_effect_addr = ptr_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) for (voice = 0; voice < YDSXG_EFFECT_VOICES; voice++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) for (bank = 0; bank < 2; bank++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) chip->bank_effect[voice][bank] = (struct snd_ymfpci_effect_bank *)ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) ptr += chip->bank_size_effect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) ptr_addr += chip->bank_size_effect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) ptr_addr = ALIGN(ptr_addr, 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) chip->work_base = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) chip->work_base_addr = ptr_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) snd_BUG_ON(ptr + chip->work_size !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) chip->work_ptr.area + chip->work_ptr.bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, chip->bank_base_playback_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, chip->bank_base_capture_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, chip->bank_base_effect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) snd_ymfpci_writel(chip, YDSXGR_WORKBASE, chip->work_base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, chip->work_size >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) /* S/PDIF output initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) chip->spdif_bits = chip->spdif_pcm_bits = SNDRV_PCM_DEFAULT_CON_SPDIF & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) /* S/PDIF input initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) snd_ymfpci_writew(chip, YDSXGR_SPDIFINCTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) /* digital mixer setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) for (reg = 0x80; reg < 0xc0; reg += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) snd_ymfpci_writel(chip, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x3fff3fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0x3fff3fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) snd_ymfpci_writel(chip, YDSXGR_ZVOUTVOL, 0x3fff3fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) snd_ymfpci_writel(chip, YDSXGR_SPDIFOUTVOL, 0x3fff3fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) snd_ymfpci_writel(chip, YDSXGR_NATIVEADCINVOL, 0x3fff3fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) snd_ymfpci_writel(chip, YDSXGR_NATIVEDACINVOL, 0x3fff3fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) snd_ymfpci_writel(chip, YDSXGR_PRIADCLOOPVOL, 0x3fff3fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0x3fff3fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) static int snd_ymfpci_free(struct snd_ymfpci *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) u16 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) if (snd_BUG_ON(!chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) if (chip->res_reg_area) { /* don't touch busy hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) snd_ymfpci_writel(chip, YDSXGR_STATUS, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) snd_ymfpci_disable_dsp(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) snd_ymfpci_writel(chip, YDSXGR_WORKBASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) snd_ymfpci_ac3_done(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) /* Set PCI device to D3 state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) /* FIXME: temporarily disabled, otherwise we cannot fire up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) * the chip again unless reboot. ACPI bug?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) pci_set_power_state(chip->pci, PCI_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) kfree(chip->saved_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) if (chip->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) free_irq(chip->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) release_and_free_resource(chip->mpu_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) release_and_free_resource(chip->fm_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) snd_ymfpci_free_gameport(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) iounmap(chip->reg_area_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) if (chip->work_ptr.area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) snd_dma_free_pages(&chip->work_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) release_and_free_resource(chip->res_reg_area);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) pci_write_config_word(chip->pci, 0x40, chip->old_legacy_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) pci_disable_device(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) release_firmware(chip->dsp_microcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) release_firmware(chip->controller_microcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) static int snd_ymfpci_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) struct snd_ymfpci *chip = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) return snd_ymfpci_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) static const int saved_regs_index[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) /* spdif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) YDSXGR_SPDIFOUTCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) YDSXGR_SPDIFOUTSTATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) YDSXGR_SPDIFINCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) /* volumes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) YDSXGR_PRIADCLOOPVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) YDSXGR_NATIVEDACINVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) YDSXGR_NATIVEDACOUTVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) YDSXGR_BUF441OUTVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) YDSXGR_NATIVEADCINVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) YDSXGR_SPDIFLOOPVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) YDSXGR_SPDIFOUTVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) YDSXGR_ZVOUTVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) YDSXGR_LEGACYOUTVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) /* address bases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) YDSXGR_PLAYCTRLBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) YDSXGR_RECCTRLBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) YDSXGR_EFFCTRLBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) YDSXGR_WORKBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) /* capture set up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) YDSXGR_MAPOFREC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) YDSXGR_RECFORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) YDSXGR_RECSLOTSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) YDSXGR_ADCFORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) YDSXGR_ADCSLOTSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) #define YDSXGR_NUM_SAVED_REGS ARRAY_SIZE(saved_regs_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) static int snd_ymfpci_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) struct snd_ymfpci *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) snd_ac97_suspend(chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) chip->saved_regs[i] = snd_ymfpci_readl(chip, saved_regs_index[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) chip->saved_ydsxgr_mode = snd_ymfpci_readl(chip, YDSXGR_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) pci_read_config_word(chip->pci, PCIR_DSXG_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) &chip->saved_dsxg_legacy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) pci_read_config_word(chip->pci, PCIR_DSXG_ELEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) &chip->saved_dsxg_elegacy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) snd_ymfpci_disable_dsp(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) static int snd_ymfpci_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) struct pci_dev *pci = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) struct snd_ymfpci *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) snd_ymfpci_aclink_reset(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) snd_ymfpci_codec_ready(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) snd_ymfpci_download_image(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) snd_ymfpci_writel(chip, saved_regs_index[i], chip->saved_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) snd_ac97_resume(chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) pci_write_config_word(chip->pci, PCIR_DSXG_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) chip->saved_dsxg_legacy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) pci_write_config_word(chip->pci, PCIR_DSXG_ELEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) chip->saved_dsxg_elegacy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) /* start hw again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) if (chip->start_count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) snd_ymfpci_writel(chip, YDSXGR_MODE, chip->saved_ydsxgr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) SIMPLE_DEV_PM_OPS(snd_ymfpci_pm, snd_ymfpci_suspend, snd_ymfpci_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) int snd_ymfpci_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) unsigned short old_legacy_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) struct snd_ymfpci **rchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) struct snd_ymfpci *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .dev_free = snd_ymfpci_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) *rchip = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) /* enable PCI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) if ((err = pci_enable_device(pci)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) chip = kzalloc(sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) if (chip == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) chip->old_legacy_ctrl = old_legacy_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) spin_lock_init(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) spin_lock_init(&chip->voice_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) init_waitqueue_head(&chip->interrupt_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) atomic_set(&chip->interrupt_sleep_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) chip->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) chip->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) chip->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) chip->device_id = pci->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) chip->rev = pci->revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) chip->reg_area_phys = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) chip->reg_area_virt = ioremap(chip->reg_area_phys, 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) chip->src441_used = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) if ((chip->res_reg_area = request_mem_region(chip->reg_area_phys, 0x8000, "YMFPCI")) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) "unable to grab memory region 0x%lx-0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) chip->reg_area_phys, chip->reg_area_phys + 0x8000 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) goto free_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) if (request_irq(pci->irq, snd_ymfpci_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) KBUILD_MODNAME, chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) goto free_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) chip->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) card->sync_irq = chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) snd_ymfpci_aclink_reset(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) if (snd_ymfpci_codec_ready(chip, 0) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) goto free_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) err = snd_ymfpci_request_firmware(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) dev_err(chip->card->dev, "firmware request failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) goto free_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) snd_ymfpci_download_image(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) udelay(100); /* seems we need a delay after downloading image.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) if (snd_ymfpci_memalloc(chip) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) goto free_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) err = snd_ymfpci_ac3_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) goto free_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) chip->saved_regs = kmalloc_array(YDSXGR_NUM_SAVED_REGS, sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) if (chip->saved_regs == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) goto free_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) goto free_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) snd_ymfpci_proc_init(card, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) *rchip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) free_chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) snd_ymfpci_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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