^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __SOUND_YMFPCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __SOUND_YMFPCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Definitions for Yahama YMF724/740/744/754 chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <sound/rawmidi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gameport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Direct registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define YMFREG(chip, reg) (chip->port + YDSXGR_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define YDSXGR_INTFLAG 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define YDSXGR_ACTIVITY 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define YDSXGR_GLOBALCTRL 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define YDSXGR_ZVCTRL 0x000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define YDSXGR_TIMERCTRL 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define YDSXGR_TIMERCOUNT 0x0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define YDSXGR_SPDIFOUTCTRL 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define YDSXGR_SPDIFOUTSTATUS 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define YDSXGR_EEPROMCTRL 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define YDSXGR_SPDIFINCTRL 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define YDSXGR_SPDIFINSTATUS 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define YDSXGR_DSPPROGRAMDL 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define YDSXGR_DLCNTRL 0x004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define YDSXGR_GPIOININTFLAG 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define YDSXGR_GPIOININTENABLE 0x0052
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define YDSXGR_GPIOINSTATUS 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define YDSXGR_GPIOOUTCTRL 0x0056
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define YDSXGR_GPIOFUNCENABLE 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define YDSXGR_GPIOTYPECONFIG 0x005A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define YDSXGR_AC97CMDDATA 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define YDSXGR_AC97CMDADR 0x0062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define YDSXGR_PRISTATUSDATA 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define YDSXGR_PRISTATUSADR 0x0066
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define YDSXGR_SECSTATUSDATA 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define YDSXGR_SECSTATUSADR 0x006A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define YDSXGR_SECCONFIG 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define YDSXGR_LEGACYOUTVOL 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define YDSXGR_LEGACYOUTVOLL 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define YDSXGR_LEGACYOUTVOLR 0x0082
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define YDSXGR_NATIVEDACOUTVOL 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define YDSXGR_NATIVEDACOUTVOLL 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define YDSXGR_NATIVEDACOUTVOLR 0x0086
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define YDSXGR_ZVOUTVOL 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define YDSXGR_ZVOUTVOLL 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define YDSXGR_ZVOUTVOLR 0x008A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define YDSXGR_SECADCOUTVOL 0x008C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define YDSXGR_SECADCOUTVOLL 0x008C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define YDSXGR_SECADCOUTVOLR 0x008E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define YDSXGR_PRIADCOUTVOL 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define YDSXGR_PRIADCOUTVOLL 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define YDSXGR_PRIADCOUTVOLR 0x0092
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define YDSXGR_LEGACYLOOPVOL 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define YDSXGR_LEGACYLOOPVOLL 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define YDSXGR_LEGACYLOOPVOLR 0x0096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define YDSXGR_NATIVEDACLOOPVOL 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define YDSXGR_NATIVEDACLOOPVOLL 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define YDSXGR_NATIVEDACLOOPVOLR 0x009A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define YDSXGR_ZVLOOPVOL 0x009C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define YDSXGR_ZVLOOPVOLL 0x009E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define YDSXGR_ZVLOOPVOLR 0x009E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define YDSXGR_SECADCLOOPVOL 0x00A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define YDSXGR_SECADCLOOPVOLL 0x00A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define YDSXGR_SECADCLOOPVOLR 0x00A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define YDSXGR_PRIADCLOOPVOL 0x00A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define YDSXGR_PRIADCLOOPVOLL 0x00A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define YDSXGR_PRIADCLOOPVOLR 0x00A6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define YDSXGR_NATIVEADCINVOL 0x00A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define YDSXGR_NATIVEADCINVOLL 0x00A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define YDSXGR_NATIVEADCINVOLR 0x00AA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define YDSXGR_NATIVEDACINVOL 0x00AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define YDSXGR_NATIVEDACINVOLL 0x00AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define YDSXGR_NATIVEDACINVOLR 0x00AE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define YDSXGR_BUF441OUTVOL 0x00B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define YDSXGR_BUF441OUTVOLL 0x00B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define YDSXGR_BUF441OUTVOLR 0x00B2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define YDSXGR_BUF441LOOPVOL 0x00B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define YDSXGR_BUF441LOOPVOLL 0x00B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define YDSXGR_BUF441LOOPVOLR 0x00B6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define YDSXGR_SPDIFOUTVOL 0x00B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define YDSXGR_SPDIFOUTVOLL 0x00B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define YDSXGR_SPDIFOUTVOLR 0x00BA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define YDSXGR_SPDIFLOOPVOL 0x00BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define YDSXGR_SPDIFLOOPVOLL 0x00BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define YDSXGR_SPDIFLOOPVOLR 0x00BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define YDSXGR_ADCSLOTSR 0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define YDSXGR_RECSLOTSR 0x00C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define YDSXGR_ADCFORMAT 0x00C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define YDSXGR_RECFORMAT 0x00CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define YDSXGR_P44SLOTSR 0x00D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define YDSXGR_STATUS 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define YDSXGR_CTRLSELECT 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define YDSXGR_MODE 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define YDSXGR_SAMPLECOUNT 0x010C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define YDSXGR_NUMOFSAMPLES 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define YDSXGR_CONFIG 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define YDSXGR_PLAYCTRLSIZE 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define YDSXGR_RECCTRLSIZE 0x0144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define YDSXGR_EFFCTRLSIZE 0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define YDSXGR_WORKSIZE 0x014C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define YDSXGR_MAPOFREC 0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define YDSXGR_MAPOFEFFECT 0x0154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define YDSXGR_PLAYCTRLBASE 0x0158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define YDSXGR_RECCTRLBASE 0x015C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define YDSXGR_EFFCTRLBASE 0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define YDSXGR_WORKBASE 0x0164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define YDSXGR_DSPINSTRAM 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define YDSXGR_CTRLINSTRAM 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define YDSXG_AC97READCMD 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define YDSXG_AC97WRITECMD 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PCIR_DSXG_LEGACY 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PCIR_DSXG_ELEGACY 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PCIR_DSXG_CTRL 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PCIR_DSXG_PWRCTRL1 0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PCIR_DSXG_PWRCTRL2 0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PCIR_DSXG_FMBASE 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PCIR_DSXG_SBBASE 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PCIR_DSXG_MPU401BASE 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PCIR_DSXG_JOYBASE 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define YDSXG_DSPLENGTH 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define YDSXG_CTRLLENGTH 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define YDSXG_DEFAULT_WORK_SIZE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define YDSXG_PLAYBACK_VOICES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define YDSXG_CAPTURE_VOICES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define YDSXG_EFFECT_VOICES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define YMFPCI_LEGACY_SBEN (1 << 0) /* soundblaster enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define YMFPCI_LEGACY_FMEN (1 << 1) /* OPL3 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define YMFPCI_LEGACY_JPEN (1 << 2) /* joystick enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define YMFPCI_LEGACY_MEN (1 << 3) /* MPU401 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define YMFPCI_LEGACY_MIEN (1 << 4) /* MPU RX irq enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define YMFPCI_LEGACY_IOBITS (1 << 5) /* i/o bits range, 0 = 16bit, 1 =10bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define YMFPCI_LEGACY_SDMA (3 << 6) /* SB DMA select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define YMFPCI_LEGACY_SBIRQ (7 << 8) /* SB IRQ select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define YMFPCI_LEGACY_MPUIRQ (7 << 11) /* MPU IRQ select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define YMFPCI_LEGACY_SIEN (1 << 14) /* serialized IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define YMFPCI_LEGACY_LAD (1 << 15) /* legacy audio disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define YMFPCI_LEGACY2_FMIO (3 << 0) /* OPL3 i/o address (724/740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define YMFPCI_LEGACY2_SBIO (3 << 2) /* SB i/o address (724/740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define YMFPCI_LEGACY2_MPUIO (3 << 4) /* MPU401 i/o address (724/740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define YMFPCI_LEGACY2_JSIO (3 << 6) /* joystick i/o address (724/740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define YMFPCI_LEGACY2_MAIM (1 << 8) /* MPU401 ack intr mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define YMFPCI_LEGACY2_SMOD (3 << 11) /* SB DMA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define YMFPCI_LEGACY2_SBVER (3 << 13) /* SB version select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define YMFPCI_LEGACY2_IMOD (1 << 15) /* legacy IRQ mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* SIEN:IMOD 0:0 = legacy irq, 0:1 = INTA, 1:0 = serialized IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #if IS_REACHABLE(CONFIG_GAMEPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct snd_ymfpci_playback_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) __le32 format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) __le32 loop_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __le32 base; /* 32-bit address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) __le32 loop_start; /* 32-bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) __le32 loop_end; /* 32-bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) __le32 loop_frac; /* 8-bit fraction - loop_start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) __le32 delta_end; /* pitch delta end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) __le32 lpfK_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __le32 eg_gain_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) __le32 left_gain_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __le32 right_gain_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) __le32 eff1_gain_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) __le32 eff2_gain_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __le32 eff3_gain_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) __le32 lpfQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) __le32 num_of_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) __le32 loop_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) __le32 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) __le32 start_frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) __le32 delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) __le32 lpfK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) __le32 eg_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __le32 left_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __le32 right_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) __le32 eff1_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __le32 eff2_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) __le32 eff3_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) __le32 lpfD1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) __le32 lpfD2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct snd_ymfpci_capture_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) __le32 base; /* 32-bit address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) __le32 loop_end; /* 32-bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) __le32 start; /* 32-bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) __le32 num_of_loops; /* counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct snd_ymfpci_effect_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) __le32 base; /* 32-bit address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) __le32 loop_end; /* 32-bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) __le32 start; /* 32-bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) __le32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct snd_ymfpci_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct snd_ymfpci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) enum snd_ymfpci_voice_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) YMFPCI_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) YMFPCI_SYNTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) YMFPCI_MIDI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct snd_ymfpci_voice {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct snd_ymfpci *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned int use: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pcm: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) synth: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) midi: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct snd_ymfpci_playback_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dma_addr_t bank_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) void (*interrupt)(struct snd_ymfpci *chip, struct snd_ymfpci_voice *voice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct snd_ymfpci_pcm *ypcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) enum snd_ymfpci_pcm_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PLAYBACK_VOICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) CAPTURE_REC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) CAPTURE_AC97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) EFFECT_DRY_LEFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) EFFECT_DRY_RIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) EFFECT_EFF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) EFFECT_EFF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) EFFECT_EFF3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct snd_ymfpci_pcm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct snd_ymfpci *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) enum snd_ymfpci_pcm_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct snd_ymfpci_voice *voices[2]; /* playback only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned int running: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) use_441_slot: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) output_front: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) output_rear: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) swap_rear: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int update_pcm_vol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 period_size; /* cached from runtime->period_size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 buffer_size; /* cached from runtime->buffer_size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 period_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 last_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 capture_bank_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct snd_ymfpci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int device_id; /* PCI device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned char rev; /* PCI revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned long reg_area_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) void __iomem *reg_area_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct resource *res_reg_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct resource *fm_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct resource *mpu_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned short old_legacy_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct gameport *gameport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct snd_dma_buffer work_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned int bank_size_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned int bank_size_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned int bank_size_effect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned int work_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) void *bank_base_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) void *bank_base_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) void *bank_base_effect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) void *work_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dma_addr_t bank_base_playback_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dma_addr_t bank_base_capture_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dma_addr_t bank_base_effect_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dma_addr_t work_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct snd_dma_buffer ac3_tmp_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) __le32 *ctrl_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct snd_ymfpci_playback_bank *bank_playback[YDSXG_PLAYBACK_VOICES][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct snd_ymfpci_capture_bank *bank_capture[YDSXG_CAPTURE_VOICES][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct snd_ymfpci_effect_bank *bank_effect[YDSXG_EFFECT_VOICES][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int start_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 active_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct snd_ymfpci_voice voices[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int src441_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct snd_ac97_bus *ac97_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct snd_ac97 *ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct snd_rawmidi *rawmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct snd_timer *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned int timer_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct snd_pcm *pcm2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct snd_pcm *pcm_spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct snd_pcm *pcm_4ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct snd_pcm_substream *capture_substream[YDSXG_CAPTURE_VOICES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct snd_pcm_substream *effect_substream[YDSXG_EFFECT_VOICES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct snd_kcontrol *ctl_vol_recsrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct snd_kcontrol *ctl_vol_adcrec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct snd_kcontrol *ctl_vol_spdifrec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned short spdif_bits, spdif_pcm_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct snd_kcontrol *spdif_pcm_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int mode_dup4ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int rear_opened;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int spdif_opened;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct snd_ymfpci_pcm_mixer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u16 left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u16 right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct snd_kcontrol *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) } pcm_mixer[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) spinlock_t voice_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) wait_queue_head_t interrupt_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) atomic_t interrupt_sleep_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct snd_info_entry *proc_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) const struct firmware *dsp_microcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) const struct firmware *controller_microcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 *saved_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u32 saved_ydsxgr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u16 saved_dsxg_legacy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u16 saved_dsxg_elegacy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int snd_ymfpci_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned short old_legacy_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct snd_ymfpci ** rcodec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) void snd_ymfpci_free_gameport(struct snd_ymfpci *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) extern const struct dev_pm_ops snd_ymfpci_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int snd_ymfpci_pcm(struct snd_ymfpci *chip, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int snd_ymfpci_pcm2(struct snd_ymfpci *chip, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int snd_ymfpci_pcm_spdif(struct snd_ymfpci *chip, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int snd_ymfpci_pcm_4ch(struct snd_ymfpci *chip, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int snd_ymfpci_mixer(struct snd_ymfpci *chip, int rear_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int snd_ymfpci_timer(struct snd_ymfpci *chip, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #endif /* __SOUND_YMFPCI_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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