^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Digigram VX222 V2/Mic soundcards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * VX222-specific low-level routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "vx222.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const int vx2_reg_offset[VX_REG_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) [VX_ICR] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) [VX_CVR] = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) [VX_ISR] = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) [VX_IVR] = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) [VX_RXH] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) [VX_RXM] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) [VX_RXL] = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) [VX_DMA] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) [VX_CDSP] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) [VX_CFG] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) [VX_RUER] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) [VX_DATA] = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) [VX_STATUS] = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) [VX_LOFREQ] = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) [VX_HIFREQ] = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) [VX_CSUER] = 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) [VX_SELMIC] = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) [VX_COMPOT] = 0x44, // Write: POTENTIOMETER ; Read: COMPRESSION LEVEL activate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) [VX_SCOMPR] = 0x48, // Read: COMPRESSION THRESHOLD activate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) [VX_GLIMIT] = 0x4c, // Read: LEVEL LIMITATION activate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) [VX_INTCSR] = 0x4c, // VX_INTCSR_REGISTER_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) [VX_CNTRL] = 0x50, // VX_CNTRL_REGISTER_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) [VX_GPIOC] = 0x54, // VX_GPIOC (new with PLX9030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const int vx2_reg_index[VX_REG_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) [VX_ICR] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) [VX_CVR] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) [VX_ISR] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) [VX_IVR] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) [VX_RXH] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) [VX_RXM] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) [VX_RXL] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) [VX_DMA] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) [VX_CDSP] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) [VX_CFG] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) [VX_RUER] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) [VX_DATA] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) [VX_STATUS] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) [VX_LOFREQ] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) [VX_HIFREQ] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) [VX_CSUER] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [VX_SELMIC] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) [VX_COMPOT] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) [VX_SCOMPR] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) [VX_GLIMIT] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) [VX_INTCSR] = 0, /* on the PLX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) [VX_CNTRL] = 0, /* on the PLX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) [VX_GPIOC] = 0, /* on the PLX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static inline unsigned long vx2_reg_addr(struct vx_core *_chip, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct snd_vx222 *chip = to_vx222(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return chip->port[vx2_reg_index[reg]] + vx2_reg_offset[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * snd_vx_inb - read a byte from the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @chip: VX core instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @offset: register enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static unsigned char vx2_inb(struct vx_core *chip, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return inb(vx2_reg_addr(chip, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * snd_vx_outb - write a byte on the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @chip: VX core instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @offset: the register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @val: the value to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void vx2_outb(struct vx_core *chip, int offset, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) outb(val, vx2_reg_addr(chip, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dev_dbg(chip->card->dev, "outb: %x -> %x\n", val, vx2_reg_addr(chip, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * snd_vx_inl - read a 32bit word from the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @chip: VX core instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @offset: register enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static unsigned int vx2_inl(struct vx_core *chip, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return inl(vx2_reg_addr(chip, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * snd_vx_outl - write a 32bit word on the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @chip: VX core instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @offset: the register enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @val: the value to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void vx2_outl(struct vx_core *chip, int offset, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_dbg(chip->card->dev, "outl: %x -> %x\n", val, vx2_reg_addr(chip, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) outl(val, vx2_reg_addr(chip, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * redefine macros to call directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #undef vx_inb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define vx_inb(chip,reg) vx2_inb((struct vx_core*)(chip), VX_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #undef vx_outb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define vx_outb(chip,reg,val) vx2_outb((struct vx_core*)(chip), VX_##reg, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #undef vx_inl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define vx_inl(chip,reg) vx2_inl((struct vx_core*)(chip), VX_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #undef vx_outl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define vx_outl(chip,reg,val) vx2_outl((struct vx_core*)(chip), VX_##reg, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * vx_reset_dsp - reset the DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define XX_DSP_RESET_WAIT_TIME 2 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void vx2_reset_dsp(struct vx_core *_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct snd_vx222 *chip = to_vx222(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* set the reset dsp bit to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mdelay(XX_DSP_RESET_WAIT_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) chip->regCDSP |= VX_CDSP_DSP_RESET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* set the reset dsp bit to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) vx_outl(chip, CDSP, chip->regCDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int vx2_test_xilinx(struct vx_core *_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct snd_vx222 *chip = to_vx222(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_dbg(_chip->card->dev, "testing xilinx...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* This test uses several write/read sequences on TEST0 and TEST1 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * to figure out whever or not the xilinx was correctly loaded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* We write 1 on CDSP.TEST0. We should get 0 on STATUS.TEST0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) vx_inl(chip, ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) data = vx_inl(chip, STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if ((data & VX_STATUS_VAL_TEST0_MASK) == VX_STATUS_VAL_TEST0_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_dbg(_chip->card->dev, "bad!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* We write 0 on CDSP.TEST0. We should get 1 on STATUS.TEST0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) vx_inl(chip, ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) data = vx_inl(chip, STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (! (data & VX_STATUS_VAL_TEST0_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dev_dbg(_chip->card->dev, "bad! #2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (_chip->type == VX_TYPE_BOARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* not implemented on VX_2_BOARDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* We write 1 on CDSP.TEST1. We should get 0 on STATUS.TEST1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST1_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) vx_inl(chip, ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) data = vx_inl(chip, STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if ((data & VX_STATUS_VAL_TEST1_MASK) == VX_STATUS_VAL_TEST1_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dev_dbg(_chip->card->dev, "bad! #3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* We write 0 on CDSP.TEST1. We should get 1 on STATUS.TEST1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST1_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) vx_inl(chip, ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) data = vx_inl(chip, STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (! (data & VX_STATUS_VAL_TEST1_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_dbg(_chip->card->dev, "bad! #4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev_dbg(_chip->card->dev, "ok, xilinx fine.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * vx_setup_pseudo_dma - set up the pseudo dma read/write mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * @chip: VX core instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @do_write: 0 = read, 1 = set up for DMA write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void vx2_setup_pseudo_dma(struct vx_core *chip, int do_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Interrupt mode and HREQ pin enabled for host transmit data transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * (in case of the use of the pseudo-dma facility).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) vx_outl(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Reset the pseudo-dma register (in case of the use of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * pseudo-dma facility).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) vx_outl(chip, RESET_DMA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * vx_release_pseudo_dma - disable the pseudo-DMA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static inline void vx2_release_pseudo_dma(struct vx_core *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* HREQ pin disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) vx_outl(chip, ICR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* pseudo-dma write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void vx2_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct vx_pipe *pipe, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned long port = vx2_reg_addr(chip, VX_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int offset = pipe->hw_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 *addr = (u32 *)(runtime->dma_area + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (snd_BUG_ON(count % 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) vx2_setup_pseudo_dma(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Transfer using pseudo-dma.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (offset + count >= pipe->buffer_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int length = pipe->buffer_bytes - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) count -= length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) length >>= 2; /* in 32bit words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Transfer using pseudo-dma. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) for (; length > 0; length--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) outl(*addr, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) addr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) addr = (u32 *)runtime->dma_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) pipe->hw_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) pipe->hw_ptr += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) count >>= 2; /* in 32bit words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Transfer using pseudo-dma. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) for (; count > 0; count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) outl(*addr, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) addr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) vx2_release_pseudo_dma(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* pseudo dma read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static void vx2_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct vx_pipe *pipe, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int offset = pipe->hw_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 *addr = (u32 *)(runtime->dma_area + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned long port = vx2_reg_addr(chip, VX_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (snd_BUG_ON(count % 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) vx2_setup_pseudo_dma(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Transfer using pseudo-dma.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (offset + count >= pipe->buffer_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int length = pipe->buffer_bytes - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) count -= length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) length >>= 2; /* in 32bit words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Transfer using pseudo-dma. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) for (; length > 0; length--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) *addr++ = inl(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) addr = (u32 *)runtime->dma_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) pipe->hw_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) pipe->hw_ptr += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) count >>= 2; /* in 32bit words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Transfer using pseudo-dma. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) for (; count > 0; count--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) *addr++ = inl(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) vx2_release_pseudo_dma(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define VX_XILINX_RESET_MASK 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define VX_USERBIT0_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define VX_USERBIT1_MASK 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define VX_CNTRL_REGISTER_VALUE 0x00172012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * transfer counts bits to PLX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int put_xilinx_data(struct vx_core *chip, unsigned int port, unsigned int counts, unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) for (i = 0; i < counts; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* set the clock bit to 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) val = VX_CNTRL_REGISTER_VALUE & ~VX_USERBIT0_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) vx2_outl(chip, port, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) vx2_inl(chip, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (data & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) val |= VX_USERBIT1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) val &= ~VX_USERBIT1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) vx2_outl(chip, port, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) vx2_inl(chip, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* set the clock bit to 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) val |= VX_USERBIT0_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) vx2_outl(chip, port, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) vx2_inl(chip, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * load the xilinx image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int vx2_load_xilinx_binary(struct vx_core *chip, const struct firmware *xilinx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) const unsigned char *image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* XILINX reset (wait at least 1 millisecond between reset on and off). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) vx_inl(chip, CNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) vx_inl(chip, CNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (chip->type == VX_TYPE_BOARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) port = VX_CNTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) port = VX_GPIOC; /* VX222 V2 and VX222_MIC_BOARD with new PLX9030 use this register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) image = xilinx->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) for (i = 0; i < xilinx->size; i++, image++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (put_xilinx_data(chip, port, 8, *image) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* don't take too much time in this loop... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) put_xilinx_data(chip, port, 4, 0xff); /* end signature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* test after loading (is buggy with VX222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (chip->type != VX_TYPE_BOARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Test if load successful: test bit 8 of register GPIOC (VX222: use CNTRL) ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) i = vx_inl(chip, GPIOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (i & 0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) "xilinx test failed after load, GPIOC=0x%x\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * load the boot/dsp images
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int vx2_load_dsp(struct vx_core *vx, int index, const struct firmware *dsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* xilinx image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if ((err = vx2_load_xilinx_binary(vx, dsp)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if ((err = vx2_test_xilinx(vx)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* DSP boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return snd_vx_dsp_boot(vx, dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* DSP image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return snd_vx_dsp_load(vx, dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * vx_test_and_ack - test and acknowledge interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * called from irq hander, too
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * spinlock held!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int vx2_test_and_ack(struct vx_core *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* not booted yet? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (! (chip->chip_status & VX_STAT_XILINX_LOADED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (! (vx_inl(chip, STATUS) & VX_STATUS_MEMIRQ_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* ok, interrupts generated, now ack it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* set ACQUIT bit up and down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) vx_outl(chip, STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* useless read just to spend some time and maintain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * the ACQUIT signal up for a while ( a bus cycle )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) vx_inl(chip, STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) vx_outl(chip, STATUS, VX_STATUS_MEMIRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* useless read just to spend some time and maintain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * the ACQUIT signal up for a while ( a bus cycle ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) vx_inl(chip, STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) vx_outl(chip, STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * vx_validate_irq - enable/disable IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static void vx2_validate_irq(struct vx_core *_chip, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct snd_vx222 *chip = to_vx222(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Set the interrupt enable bit to 1 in CDSP register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Set the PCI interrupt enable bit to 1.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) vx_outl(chip, INTCSR, VX_INTCSR_VALUE|VX_PCI_INTERRUPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) chip->regCDSP |= VX_CDSP_VALID_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Set the PCI interrupt enable bit to 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) vx_outl(chip, INTCSR, VX_INTCSR_VALUE&~VX_PCI_INTERRUPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) chip->regCDSP &= ~VX_CDSP_VALID_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) vx_outl(chip, CDSP, chip->regCDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * write an AKM codec data (24bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static void vx2_write_codec_reg(struct vx_core *chip, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) vx_inl(chip, HIFREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* We have to send 24 bits (3 x 8 bits). Start with most signif. Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) for (i = 0; i < 24; i++, data <<= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Terminate access to codec registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) vx_inl(chip, RUER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define AKM_CODEC_POWER_CONTROL_CMD 0xA007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define AKM_CODEC_RESET_ON_CMD 0xA100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define AKM_CODEC_RESET_OFF_CMD 0xA103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define AKM_CODEC_CLOCK_FORMAT_CMD 0xA240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define AKM_CODEC_MUTE_CMD 0xA38D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define AKM_CODEC_UNMUTE_CMD 0xA30D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define AKM_CODEC_LEFT_LEVEL_CMD 0xA400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define AKM_CODEC_RIGHT_LEVEL_CMD 0xA500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const u8 vx2_akm_gains_lut[VX2_AKM_LEVEL_MAX+1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 0x7f, // [000] = +0.000 dB -> AKM(0x7f) = +0.000 dB error(+0.000 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 0x7d, // [001] = -0.500 dB -> AKM(0x7d) = -0.572 dB error(-0.072 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 0x7c, // [002] = -1.000 dB -> AKM(0x7c) = -0.873 dB error(+0.127 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 0x7a, // [003] = -1.500 dB -> AKM(0x7a) = -1.508 dB error(-0.008 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 0x79, // [004] = -2.000 dB -> AKM(0x79) = -1.844 dB error(+0.156 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 0x77, // [005] = -2.500 dB -> AKM(0x77) = -2.557 dB error(-0.057 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 0x76, // [006] = -3.000 dB -> AKM(0x76) = -2.937 dB error(+0.063 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 0x75, // [007] = -3.500 dB -> AKM(0x75) = -3.334 dB error(+0.166 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 0x73, // [008] = -4.000 dB -> AKM(0x73) = -4.188 dB error(-0.188 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 0x72, // [009] = -4.500 dB -> AKM(0x72) = -4.648 dB error(-0.148 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 0x71, // [010] = -5.000 dB -> AKM(0x71) = -5.134 dB error(-0.134 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 0x70, // [011] = -5.500 dB -> AKM(0x70) = -5.649 dB error(-0.149 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 0x6f, // [012] = -6.000 dB -> AKM(0x6f) = -6.056 dB error(-0.056 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 0x6d, // [013] = -6.500 dB -> AKM(0x6d) = -6.631 dB error(-0.131 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 0x6c, // [014] = -7.000 dB -> AKM(0x6c) = -6.933 dB error(+0.067 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 0x6a, // [015] = -7.500 dB -> AKM(0x6a) = -7.571 dB error(-0.071 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 0x69, // [016] = -8.000 dB -> AKM(0x69) = -7.909 dB error(+0.091 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 0x67, // [017] = -8.500 dB -> AKM(0x67) = -8.626 dB error(-0.126 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 0x66, // [018] = -9.000 dB -> AKM(0x66) = -9.008 dB error(-0.008 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 0x65, // [019] = -9.500 dB -> AKM(0x65) = -9.407 dB error(+0.093 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 0x64, // [020] = -10.000 dB -> AKM(0x64) = -9.826 dB error(+0.174 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 0x62, // [021] = -10.500 dB -> AKM(0x62) = -10.730 dB error(-0.230 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 0x61, // [022] = -11.000 dB -> AKM(0x61) = -11.219 dB error(-0.219 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 0x60, // [023] = -11.500 dB -> AKM(0x60) = -11.738 dB error(-0.238 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 0x5f, // [024] = -12.000 dB -> AKM(0x5f) = -12.149 dB error(-0.149 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 0x5e, // [025] = -12.500 dB -> AKM(0x5e) = -12.434 dB error(+0.066 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 0x5c, // [026] = -13.000 dB -> AKM(0x5c) = -13.033 dB error(-0.033 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 0x5b, // [027] = -13.500 dB -> AKM(0x5b) = -13.350 dB error(+0.150 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 0x59, // [028] = -14.000 dB -> AKM(0x59) = -14.018 dB error(-0.018 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 0x58, // [029] = -14.500 dB -> AKM(0x58) = -14.373 dB error(+0.127 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 0x56, // [030] = -15.000 dB -> AKM(0x56) = -15.130 dB error(-0.130 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 0x55, // [031] = -15.500 dB -> AKM(0x55) = -15.534 dB error(-0.034 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 0x54, // [032] = -16.000 dB -> AKM(0x54) = -15.958 dB error(+0.042 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 0x53, // [033] = -16.500 dB -> AKM(0x53) = -16.404 dB error(+0.096 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 0x52, // [034] = -17.000 dB -> AKM(0x52) = -16.874 dB error(+0.126 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 0x51, // [035] = -17.500 dB -> AKM(0x51) = -17.371 dB error(+0.129 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 0x50, // [036] = -18.000 dB -> AKM(0x50) = -17.898 dB error(+0.102 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 0x4e, // [037] = -18.500 dB -> AKM(0x4e) = -18.605 dB error(-0.105 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 0x4d, // [038] = -19.000 dB -> AKM(0x4d) = -18.905 dB error(+0.095 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 0x4b, // [039] = -19.500 dB -> AKM(0x4b) = -19.538 dB error(-0.038 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 0x4a, // [040] = -20.000 dB -> AKM(0x4a) = -19.872 dB error(+0.128 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 0x48, // [041] = -20.500 dB -> AKM(0x48) = -20.583 dB error(-0.083 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 0x47, // [042] = -21.000 dB -> AKM(0x47) = -20.961 dB error(+0.039 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 0x46, // [043] = -21.500 dB -> AKM(0x46) = -21.356 dB error(+0.144 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 0x44, // [044] = -22.000 dB -> AKM(0x44) = -22.206 dB error(-0.206 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 0x43, // [045] = -22.500 dB -> AKM(0x43) = -22.664 dB error(-0.164 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 0x42, // [046] = -23.000 dB -> AKM(0x42) = -23.147 dB error(-0.147 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 0x41, // [047] = -23.500 dB -> AKM(0x41) = -23.659 dB error(-0.159 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 0x40, // [048] = -24.000 dB -> AKM(0x40) = -24.203 dB error(-0.203 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 0x3f, // [049] = -24.500 dB -> AKM(0x3f) = -24.635 dB error(-0.135 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 0x3e, // [050] = -25.000 dB -> AKM(0x3e) = -24.935 dB error(+0.065 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 0x3c, // [051] = -25.500 dB -> AKM(0x3c) = -25.569 dB error(-0.069 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 0x3b, // [052] = -26.000 dB -> AKM(0x3b) = -25.904 dB error(+0.096 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 0x39, // [053] = -26.500 dB -> AKM(0x39) = -26.615 dB error(-0.115 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 0x38, // [054] = -27.000 dB -> AKM(0x38) = -26.994 dB error(+0.006 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 0x37, // [055] = -27.500 dB -> AKM(0x37) = -27.390 dB error(+0.110 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 0x36, // [056] = -28.000 dB -> AKM(0x36) = -27.804 dB error(+0.196 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 0x34, // [057] = -28.500 dB -> AKM(0x34) = -28.699 dB error(-0.199 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 0x33, // [058] = -29.000 dB -> AKM(0x33) = -29.183 dB error(-0.183 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 0x32, // [059] = -29.500 dB -> AKM(0x32) = -29.696 dB error(-0.196 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 0x31, // [060] = -30.000 dB -> AKM(0x31) = -30.241 dB error(-0.241 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 0x31, // [061] = -30.500 dB -> AKM(0x31) = -30.241 dB error(+0.259 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 0x30, // [062] = -31.000 dB -> AKM(0x30) = -30.823 dB error(+0.177 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 0x2e, // [063] = -31.500 dB -> AKM(0x2e) = -31.610 dB error(-0.110 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 0x2d, // [064] = -32.000 dB -> AKM(0x2d) = -31.945 dB error(+0.055 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 0x2b, // [065] = -32.500 dB -> AKM(0x2b) = -32.659 dB error(-0.159 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 0x2a, // [066] = -33.000 dB -> AKM(0x2a) = -33.038 dB error(-0.038 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 0x29, // [067] = -33.500 dB -> AKM(0x29) = -33.435 dB error(+0.065 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 0x28, // [068] = -34.000 dB -> AKM(0x28) = -33.852 dB error(+0.148 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 0x27, // [069] = -34.500 dB -> AKM(0x27) = -34.289 dB error(+0.211 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 0x25, // [070] = -35.000 dB -> AKM(0x25) = -35.235 dB error(-0.235 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 0x24, // [071] = -35.500 dB -> AKM(0x24) = -35.750 dB error(-0.250 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 0x24, // [072] = -36.000 dB -> AKM(0x24) = -35.750 dB error(+0.250 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 0x23, // [073] = -36.500 dB -> AKM(0x23) = -36.297 dB error(+0.203 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 0x22, // [074] = -37.000 dB -> AKM(0x22) = -36.881 dB error(+0.119 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 0x21, // [075] = -37.500 dB -> AKM(0x21) = -37.508 dB error(-0.008 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 0x20, // [076] = -38.000 dB -> AKM(0x20) = -38.183 dB error(-0.183 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 0x1f, // [077] = -38.500 dB -> AKM(0x1f) = -38.726 dB error(-0.226 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 0x1e, // [078] = -39.000 dB -> AKM(0x1e) = -39.108 dB error(-0.108 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 0x1d, // [079] = -39.500 dB -> AKM(0x1d) = -39.507 dB error(-0.007 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 0x1c, // [080] = -40.000 dB -> AKM(0x1c) = -39.926 dB error(+0.074 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 0x1b, // [081] = -40.500 dB -> AKM(0x1b) = -40.366 dB error(+0.134 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 0x1a, // [082] = -41.000 dB -> AKM(0x1a) = -40.829 dB error(+0.171 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 0x19, // [083] = -41.500 dB -> AKM(0x19) = -41.318 dB error(+0.182 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 0x18, // [084] = -42.000 dB -> AKM(0x18) = -41.837 dB error(+0.163 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 0x17, // [085] = -42.500 dB -> AKM(0x17) = -42.389 dB error(+0.111 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 0x16, // [086] = -43.000 dB -> AKM(0x16) = -42.978 dB error(+0.022 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 0x15, // [087] = -43.500 dB -> AKM(0x15) = -43.610 dB error(-0.110 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 0x14, // [088] = -44.000 dB -> AKM(0x14) = -44.291 dB error(-0.291 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 0x14, // [089] = -44.500 dB -> AKM(0x14) = -44.291 dB error(+0.209 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 0x13, // [090] = -45.000 dB -> AKM(0x13) = -45.031 dB error(-0.031 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 0x12, // [091] = -45.500 dB -> AKM(0x12) = -45.840 dB error(-0.340 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 0x12, // [092] = -46.000 dB -> AKM(0x12) = -45.840 dB error(+0.160 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 0x11, // [093] = -46.500 dB -> AKM(0x11) = -46.731 dB error(-0.231 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 0x11, // [094] = -47.000 dB -> AKM(0x11) = -46.731 dB error(+0.269 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 0x10, // [095] = -47.500 dB -> AKM(0x10) = -47.725 dB error(-0.225 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 0x10, // [096] = -48.000 dB -> AKM(0x10) = -47.725 dB error(+0.275 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 0x0f, // [097] = -48.500 dB -> AKM(0x0f) = -48.553 dB error(-0.053 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 0x0e, // [098] = -49.000 dB -> AKM(0x0e) = -49.152 dB error(-0.152 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 0x0d, // [099] = -49.500 dB -> AKM(0x0d) = -49.796 dB error(-0.296 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 0x0d, // [100] = -50.000 dB -> AKM(0x0d) = -49.796 dB error(+0.204 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 0x0c, // [101] = -50.500 dB -> AKM(0x0c) = -50.491 dB error(+0.009 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 0x0b, // [102] = -51.000 dB -> AKM(0x0b) = -51.247 dB error(-0.247 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 0x0b, // [103] = -51.500 dB -> AKM(0x0b) = -51.247 dB error(+0.253 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 0x0a, // [104] = -52.000 dB -> AKM(0x0a) = -52.075 dB error(-0.075 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 0x0a, // [105] = -52.500 dB -> AKM(0x0a) = -52.075 dB error(+0.425 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 0x09, // [106] = -53.000 dB -> AKM(0x09) = -52.990 dB error(+0.010 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 0x09, // [107] = -53.500 dB -> AKM(0x09) = -52.990 dB error(+0.510 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 0x08, // [108] = -54.000 dB -> AKM(0x08) = -54.013 dB error(-0.013 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 0x08, // [109] = -54.500 dB -> AKM(0x08) = -54.013 dB error(+0.487 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 0x07, // [110] = -55.000 dB -> AKM(0x07) = -55.173 dB error(-0.173 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 0x07, // [111] = -55.500 dB -> AKM(0x07) = -55.173 dB error(+0.327 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 0x06, // [112] = -56.000 dB -> AKM(0x06) = -56.512 dB error(-0.512 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 0x06, // [113] = -56.500 dB -> AKM(0x06) = -56.512 dB error(-0.012 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 0x06, // [114] = -57.000 dB -> AKM(0x06) = -56.512 dB error(+0.488 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 0x05, // [115] = -57.500 dB -> AKM(0x05) = -58.095 dB error(-0.595 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 0x05, // [116] = -58.000 dB -> AKM(0x05) = -58.095 dB error(-0.095 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 0x05, // [117] = -58.500 dB -> AKM(0x05) = -58.095 dB error(+0.405 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 0x05, // [118] = -59.000 dB -> AKM(0x05) = -58.095 dB error(+0.905 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 0x04, // [119] = -59.500 dB -> AKM(0x04) = -60.034 dB error(-0.534 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 0x04, // [120] = -60.000 dB -> AKM(0x04) = -60.034 dB error(-0.034 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 0x04, // [121] = -60.500 dB -> AKM(0x04) = -60.034 dB error(+0.466 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 0x04, // [122] = -61.000 dB -> AKM(0x04) = -60.034 dB error(+0.966 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 0x03, // [123] = -61.500 dB -> AKM(0x03) = -62.532 dB error(-1.032 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 0x03, // [124] = -62.000 dB -> AKM(0x03) = -62.532 dB error(-0.532 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 0x03, // [125] = -62.500 dB -> AKM(0x03) = -62.532 dB error(-0.032 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 0x03, // [126] = -63.000 dB -> AKM(0x03) = -62.532 dB error(+0.468 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 0x03, // [127] = -63.500 dB -> AKM(0x03) = -62.532 dB error(+0.968 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 0x03, // [128] = -64.000 dB -> AKM(0x03) = -62.532 dB error(+1.468 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 0x02, // [129] = -64.500 dB -> AKM(0x02) = -66.054 dB error(-1.554 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 0x02, // [130] = -65.000 dB -> AKM(0x02) = -66.054 dB error(-1.054 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 0x02, // [131] = -65.500 dB -> AKM(0x02) = -66.054 dB error(-0.554 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 0x02, // [132] = -66.000 dB -> AKM(0x02) = -66.054 dB error(-0.054 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 0x02, // [133] = -66.500 dB -> AKM(0x02) = -66.054 dB error(+0.446 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 0x02, // [134] = -67.000 dB -> AKM(0x02) = -66.054 dB error(+0.946 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 0x02, // [135] = -67.500 dB -> AKM(0x02) = -66.054 dB error(+1.446 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 0x02, // [136] = -68.000 dB -> AKM(0x02) = -66.054 dB error(+1.946 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 0x02, // [137] = -68.500 dB -> AKM(0x02) = -66.054 dB error(+2.446 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 0x02, // [138] = -69.000 dB -> AKM(0x02) = -66.054 dB error(+2.946 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 0x01, // [139] = -69.500 dB -> AKM(0x01) = -72.075 dB error(-2.575 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 0x01, // [140] = -70.000 dB -> AKM(0x01) = -72.075 dB error(-2.075 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 0x01, // [141] = -70.500 dB -> AKM(0x01) = -72.075 dB error(-1.575 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 0x01, // [142] = -71.000 dB -> AKM(0x01) = -72.075 dB error(-1.075 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 0x01, // [143] = -71.500 dB -> AKM(0x01) = -72.075 dB error(-0.575 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 0x01, // [144] = -72.000 dB -> AKM(0x01) = -72.075 dB error(-0.075 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 0x01, // [145] = -72.500 dB -> AKM(0x01) = -72.075 dB error(+0.425 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 0x01, // [146] = -73.000 dB -> AKM(0x01) = -72.075 dB error(+0.925 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 0x00}; // [147] = -73.500 dB -> AKM(0x00) = mute error(+infini)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * pseudo-codec write entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static void vx2_write_akm(struct vx_core *chip, int reg, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (reg == XX_CODEC_DAC_CONTROL_REGISTER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) vx2_write_codec_reg(chip, data ? AKM_CODEC_MUTE_CMD : AKM_CODEC_UNMUTE_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* `data' is a value between 0x0 and VX2_AKM_LEVEL_MAX = 0x093, in the case of the AKM codecs, we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) a look up table, as there is no linear matching between the driver codec values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) and the real dBu value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (snd_BUG_ON(data >= sizeof(vx2_akm_gains_lut)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) case XX_CODEC_LEVEL_LEFT_REGISTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) val = AKM_CODEC_LEFT_LEVEL_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) case XX_CODEC_LEVEL_RIGHT_REGISTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) val = AKM_CODEC_RIGHT_LEVEL_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) val |= vx2_akm_gains_lut[data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) vx2_write_codec_reg(chip, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * write codec bit for old VX222 board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static void vx2_old_write_codec_bit(struct vx_core *chip, int codec, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* activate access to codec registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) vx_inl(chip, HIFREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) for (i = 0; i < 24; i++, data <<= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* Terminate access to codec registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) vx_inl(chip, RUER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * reset codec bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static void vx2_reset_codec(struct vx_core *_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct snd_vx222 *chip = to_vx222(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* Set the reset CODEC bit to 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) vx_inl(chip, CDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* Set the reset CODEC bit to 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) chip->regCDSP |= VX_CDSP_CODEC_RESET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) vx_outl(chip, CDSP, chip->regCDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) vx_inl(chip, CDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (_chip->type == VX_TYPE_BOARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) msleep(5); /* additionnel wait time for AKM's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) vx2_write_codec_reg(_chip, AKM_CODEC_POWER_CONTROL_CMD); /* DAC power up, ADC power up, Vref power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) vx2_write_codec_reg(_chip, AKM_CODEC_CLOCK_FORMAT_CMD); /* default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) vx2_write_codec_reg(_chip, AKM_CODEC_MUTE_CMD); /* Mute = ON ,Deemphasis = OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) vx2_write_codec_reg(_chip, AKM_CODEC_RESET_OFF_CMD); /* DAC and ADC normal operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (_chip->type == VX_TYPE_MIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* set up the micro input selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) chip->regSELMIC = MICRO_SELECT_INPUT_NORM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) MICRO_SELECT_PREAMPLI_G_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) MICRO_SELECT_NOISE_T_52DB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* reset phantom power supply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) chip->regSELMIC &= ~MICRO_SELECT_PHANTOM_ALIM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) vx_outl(_chip, SELMIC, chip->regSELMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * change the audio source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static void vx2_change_audio_source(struct vx_core *_chip, int src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct snd_vx222 *chip = to_vx222(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) switch (src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) case VX_AUDIO_SRC_DIGITAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) chip->regCFG |= VX_CFG_DATAIN_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) chip->regCFG &= ~VX_CFG_DATAIN_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) vx_outl(chip, CFG, chip->regCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * set the clock source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static void vx2_set_clock_source(struct vx_core *_chip, int source)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct snd_vx222 *chip = to_vx222(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (source == INTERNAL_QUARTZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) chip->regCFG &= ~VX_CFG_CLOCKIN_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) chip->regCFG |= VX_CFG_CLOCKIN_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) vx_outl(chip, CFG, chip->regCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * reset the board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static void vx2_reset_board(struct vx_core *_chip, int cold_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct snd_vx222 *chip = to_vx222(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* initialize the register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) chip->regCDSP = VX_CDSP_CODEC_RESET_MASK | VX_CDSP_DSP_RESET_MASK ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) chip->regCFG = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * input level controls for VX222 Mic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* Micro level is specified to be adjustable from -96dB to 63 dB (board coded 0x00 ... 318),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * 318 = 210 + 36 + 36 + 36 (210 = +9dB variable) (3 * 36 = 3 steps of 18dB pre ampli)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * as we will mute if less than -110dB, so let's simply use line input coded levels and add constant offset !
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define V2_MICRO_LEVEL_RANGE (318 - 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static void vx2_set_input_level(struct snd_vx222 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) int i, miclevel, preamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) miclevel = chip->mic_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) miclevel += V2_MICRO_LEVEL_RANGE; /* add 318 - 0xff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) preamp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) while (miclevel > 210) { /* limitation to +9dB of 3310 real gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) preamp++; /* raise pre ampli + 18dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) miclevel -= (18 * 2); /* lower level 18 dB (*2 because of 0.5 dB steps !) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (snd_BUG_ON(preamp >= 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* set pre-amp level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) chip->regSELMIC &= ~MICRO_SELECT_PREAMPLI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) chip->regSELMIC |= (preamp << MICRO_SELECT_PREAMPLI_OFFSET) & MICRO_SELECT_PREAMPLI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) vx_outl(chip, SELMIC, chip->regSELMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) data = (unsigned int)miclevel << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) (unsigned int)chip->input_level[1] << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) (unsigned int)chip->input_level[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) vx_inl(chip, DATA); /* Activate input level programming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* We have to send 32 bits (4 x 8 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) for (i = 0; i < 32; i++, data <<= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) vx_outl(chip, DATA, ((data & 0x80000000) ? VX_DATA_CODEC_MASK : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) vx_inl(chip, RUER); /* Terminate input level programming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define MIC_LEVEL_MAX 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static const DECLARE_TLV_DB_SCALE(db_scale_mic, -6450, 50, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * controls API for input levels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* input levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static int vx_input_level_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) uinfo->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) uinfo->value.integer.max = MIC_LEVEL_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static int vx_input_level_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct vx_core *_chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct snd_vx222 *chip = to_vx222(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) mutex_lock(&_chip->mixer_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ucontrol->value.integer.value[0] = chip->input_level[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ucontrol->value.integer.value[1] = chip->input_level[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) mutex_unlock(&_chip->mixer_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static int vx_input_level_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct vx_core *_chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct snd_vx222 *chip = to_vx222(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (ucontrol->value.integer.value[0] < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ucontrol->value.integer.value[0] > MIC_LEVEL_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (ucontrol->value.integer.value[1] < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ucontrol->value.integer.value[1] > MIC_LEVEL_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) mutex_lock(&_chip->mixer_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (chip->input_level[0] != ucontrol->value.integer.value[0] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) chip->input_level[1] != ucontrol->value.integer.value[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) chip->input_level[0] = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) chip->input_level[1] = ucontrol->value.integer.value[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) vx2_set_input_level(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) mutex_unlock(&_chip->mixer_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) mutex_unlock(&_chip->mixer_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* mic level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static int vx_mic_level_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) uinfo->value.integer.max = MIC_LEVEL_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static int vx_mic_level_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct vx_core *_chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct snd_vx222 *chip = to_vx222(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ucontrol->value.integer.value[0] = chip->mic_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static int vx_mic_level_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct vx_core *_chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct snd_vx222 *chip = to_vx222(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (ucontrol->value.integer.value[0] < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ucontrol->value.integer.value[0] > MIC_LEVEL_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) mutex_lock(&_chip->mixer_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (chip->mic_level != ucontrol->value.integer.value[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) chip->mic_level = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) vx2_set_input_level(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) mutex_unlock(&_chip->mixer_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) mutex_unlock(&_chip->mixer_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static const struct snd_kcontrol_new vx_control_input_level = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) SNDRV_CTL_ELEM_ACCESS_TLV_READ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .name = "Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .info = vx_input_level_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .get = vx_input_level_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .put = vx_input_level_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .tlv = { .p = db_scale_mic },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static const struct snd_kcontrol_new vx_control_mic_level = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) SNDRV_CTL_ELEM_ACCESS_TLV_READ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .name = "Mic Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .info = vx_mic_level_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .get = vx_mic_level_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .put = vx_mic_level_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .tlv = { .p = db_scale_mic },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * FIXME: compressor/limiter implementation is missing yet...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static int vx2_add_mic_controls(struct vx_core *_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct snd_vx222 *chip = to_vx222(_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (_chip->type != VX_TYPE_MIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /* mute input levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) chip->input_level[0] = chip->input_level[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) chip->mic_level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) vx2_set_input_level(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if ((err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_input_level, chip))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if ((err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_mic_level, chip))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) const struct snd_vx_ops vx222_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .in8 = vx2_inb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .in32 = vx2_inl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .out8 = vx2_outb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .out32 = vx2_outl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .test_and_ack = vx2_test_and_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .validate_irq = vx2_validate_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .akm_write = vx2_write_akm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .reset_codec = vx2_reset_codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .change_audio_source = vx2_change_audio_source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .set_clock_source = vx2_set_clock_source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .load_dsp = vx2_load_dsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .reset_dsp = vx2_reset_dsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .reset_board = vx2_reset_board,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .dma_write = vx2_dma_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .dma_read = vx2_dma_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .add_controls = vx2_add_mic_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /* for old VX222 board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) const struct snd_vx_ops vx222_old_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .in8 = vx2_inb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .in32 = vx2_inl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .out8 = vx2_outb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .out32 = vx2_outl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .test_and_ack = vx2_test_and_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .validate_irq = vx2_validate_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .write_codec = vx2_old_write_codec_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .reset_codec = vx2_reset_codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .change_audio_source = vx2_change_audio_source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .set_clock_source = vx2_set_clock_source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .load_dsp = vx2_load_dsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .reset_dsp = vx2_reset_dsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .reset_board = vx2_reset_board,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .dma_write = vx2_dma_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .dma_read = vx2_dma_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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