^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Digigram VX222 PCI soundcards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __VX222_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __VX222_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <sound/vx_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct snd_vx222 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct vx_core core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* h/w config; for PLX and for DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) unsigned long port[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) unsigned int regCDSP; /* current CDSP register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned int regCFG; /* current CFG register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int regSELMIC; /* current SELMIC reg. (for VX222 Mic) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) int input_level[2]; /* input level for vx222 mic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) int mic_level; /* mic level for vx222 mic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define to_vx222(x) container_of(x, struct snd_vx222, core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* we use a lookup table with 148 values, see vx_mixer.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define VX2_AKM_LEVEL_MAX 0x93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) extern const struct snd_vx_ops vx222_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) extern const struct snd_vx_ops vx222_old_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Offset of registers with base equal to portDSP. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VX_RESET_DMA_REGISTER_OFFSET 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Constants used to access the INTCSR register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VX_INTCSR_VALUE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VX_PCI_INTERRUPT_MASK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Constants used to access the CDSP register (0x20). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define VX_CDSP_TEST1_MASK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define VX_CDSP_TOR1_MASK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define VX_CDSP_TOR2_MASK 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VX_CDSP_RESERVED0_0_MASK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VX_CDSP_CODEC_RESET_MASK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VX_CDSP_VALID_IRQ_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VX_CDSP_TEST0_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VX_CDSP_DSP_RESET_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VX_CDSP_GPIO_OUT_MASK 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define VX_GPIO_OUT_BIT_OFFSET 5 // transform output to bit 0 and 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Constants used to access the CFG register (0x24). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define VX_CFG_SYNCDSP_MASK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VX_CFG_RESERVED0_0_MASK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define VX_CFG_RESERVED1_0_MASK 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define VX_CFG_RESERVED2_0_MASK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VX_CFG_DATAIN_SEL_MASK 0x00000008 // 0 (ana), 1 (UER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define VX_CFG_RESERVED3_0_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define VX_CFG_RESERVED4_0_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define VX_CFG_CLOCKIN_SEL_MASK 0x00000001 // 0 (internal), 1 (AES/EBU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Constants used to access the STATUS register (0x30). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define VX_STATUS_DATA_XICOR_MASK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define VX_STATUS_VAL_TEST1_MASK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VX_STATUS_VAL_TEST0_MASK 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define VX_STATUS_RESERVED0_MASK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define VX_STATUS_VAL_TOR1_MASK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define VX_STATUS_VAL_TOR0_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define VX_STATUS_LEVEL_IN_MASK 0x00000002 // 6 dBu (0), 22 dBu (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define VX_STATUS_MEMIRQ_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define VX_STATUS_GPIO_IN_MASK 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define VX_GPIO_IN_BIT_OFFSET 0 // leave input as bit 2 and 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Constants used to access the MICRO INPUT SELECT register (0x40). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MICRO_SELECT_INPUT_NORM 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MICRO_SELECT_INPUT_MUTE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MICRO_SELECT_INPUT_LIMIT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MICRO_SELECT_INPUT_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MICRO_SELECT_PREAMPLI_G_0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MICRO_SELECT_PREAMPLI_G_1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MICRO_SELECT_PREAMPLI_G_2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MICRO_SELECT_PREAMPLI_G_3 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MICRO_SELECT_PREAMPLI_MASK 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MICRO_SELECT_PREAMPLI_OFFSET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MICRO_SELECT_RAISE_COMPR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MICRO_SELECT_NOISE_T_52DB 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MICRO_SELECT_NOISE_T_42DB 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MICRO_SELECT_NOISE_T_32DB 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MICRO_SELECT_NOISE_T_MASK 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MICRO_SELECT_PHANTOM_ALIM 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif /* __VX222_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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