^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA driver for VIA VT82xx (South Bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * VT82C686A/B/C, VT8233A/C, VT8235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Tjeerd.Mulder <Tjeerd.Mulder@fujitsu-siemens.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * 2002 Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Changes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Dec. 19, 2002 Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * - use the DSX channels for the first pcm playback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * (on VIA8233, 8233C and 8235 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * this will allow you play simultaneously up to 4 streams.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * multi-channel playback is assigned to the second device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * on these chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * - support the secondary capture (on VIA8233/C,8235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * - SPDIF support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * the DSX3 channel can be used for SPDIF output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * on VIA8233A, this channel is assigned to the second pcm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * playback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * the card config of alsa-lib will assign the correct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * device for applications.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * - clean up the code, separate low-level initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * routines for each chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Sep. 26, 2005 Karsten Wiese <annabellesgarden@yahoo.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * - Optimize position calculation for the 823x chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/gameport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <sound/mpu401.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define POINTER_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MODULE_DESCRIPTION("VIA VT82xx audio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MODULE_SUPPORTED_DEVICE("{{VIA,VT82C686A/B/C,pci},{VIA,VT8233A/C,8235}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #if IS_REACHABLE(CONFIG_GAMEPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SUPPORT_JOYSTICK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static long mpu_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static bool joystick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int ac97_clock = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static char *ac97_quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int dxs_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int dxs_init_volume = 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int nodelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) module_param(index, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MODULE_PARM_DESC(index, "Index value for VIA 82xx bridge.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) module_param(id, charp, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MODULE_PARM_DESC(id, "ID string for VIA 82xx bridge.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) module_param_hw(mpu_port, long, ioport, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MODULE_PARM_DESC(mpu_port, "MPU-401 port. (VT82C686x only)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) module_param(joystick, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MODULE_PARM_DESC(joystick, "Enable joystick. (VT82C686x only)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) module_param(ac97_clock, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) module_param(ac97_quirk, charp, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) module_param(dxs_support, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MODULE_PARM_DESC(dxs_support, "Support for DXS channels (0 = auto, 1 = enable, 2 = disable, 3 = 48k only, 4 = no VRA, 5 = enable any sample rate)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) module_param(dxs_init_volume, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MODULE_PARM_DESC(dxs_init_volume, "initial DXS volume (0-31)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) module_param(nodelay, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MODULE_PARM_DESC(nodelay, "Disable 500ms init delay");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* just for backward compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static bool enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) module_param(enable, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* revision numbers for via686 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define VIA_REV_686_A 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define VIA_REV_686_B 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define VIA_REV_686_C 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define VIA_REV_686_D 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define VIA_REV_686_E 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VIA_REV_686_H 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* revision numbers for via8233 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define VIA_REV_PRE_8233 0x10 /* not in market */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define VIA_REV_8233C 0x20 /* 2 rec, 4 pb, 1 multi-pb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define VIA_REV_8233 0x30 /* 2 rec, 4 pb, 1 multi-pb, spdif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define VIA_REV_8233A 0x40 /* 1 rec, 1 multi-pb, spdf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define VIA_REV_8235 0x50 /* 2 rec, 4 pb, 1 multi-pb, spdif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define VIA_REV_8237 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define VIA_REV_8251 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Direct registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define VIAREG(via, x) ((via)->port + VIA_REG_##x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define VIADEV_REG(viadev, x) ((viadev)->port + VIA_REG_##x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* common offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define VIA_REG_OFFSET_STATUS 0x00 /* byte - channel status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define VIA_REG_STAT_ACTIVE 0x80 /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define VIA8233_SHADOW_STAT_ACTIVE 0x08 /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define VIA_REG_STAT_PAUSED 0x40 /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define VIA_REG_STAT_TRIGGER_QUEUED 0x08 /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define VIA_REG_STAT_STOPPED 0x04 /* RWC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define VIA_REG_STAT_EOL 0x02 /* RWC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define VIA_REG_STAT_FLAG 0x01 /* RWC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define VIA_REG_OFFSET_CONTROL 0x01 /* byte - channel control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define VIA_REG_CTRL_START 0x80 /* WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define VIA_REG_CTRL_TERMINATE 0x40 /* WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define VIA_REG_CTRL_AUTOSTART 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define VIA_REG_CTRL_PAUSE 0x08 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define VIA_REG_CTRL_INT_STOP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define VIA_REG_CTRL_INT_EOL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define VIA_REG_CTRL_INT_FLAG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define VIA_REG_CTRL_RESET 0x01 /* RW - probably reset? undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define VIA_REG_CTRL_INT (VIA_REG_CTRL_INT_FLAG | VIA_REG_CTRL_INT_EOL | VIA_REG_CTRL_AUTOSTART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define VIA_REG_OFFSET_TYPE 0x02 /* byte - channel type (686 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define VIA_REG_TYPE_AUTOSTART 0x80 /* RW - autostart at EOL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define VIA_REG_TYPE_16BIT 0x20 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define VIA_REG_TYPE_STEREO 0x10 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define VIA_REG_TYPE_INT_LLINE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define VIA_REG_TYPE_INT_LSAMPLE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define VIA_REG_TYPE_INT_LESSONE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define VIA_REG_TYPE_INT_MASK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define VIA_REG_TYPE_INT_EOL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define VIA_REG_TYPE_INT_FLAG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define VIA_REG_OFFSET_TABLE_PTR 0x04 /* dword - channel table pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define VIA_REG_OFFSET_CURR_PTR 0x04 /* dword - channel current pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define VIA_REG_OFFSET_STOP_IDX 0x08 /* dword - stop index, channel type, sample rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define VIA8233_REG_TYPE_16BIT 0x00200000 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define VIA8233_REG_TYPE_STEREO 0x00100000 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define VIA_REG_OFFSET_CURR_COUNT 0x0c /* dword - channel current count (24 bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define VIA_REG_OFFSET_CURR_INDEX 0x0f /* byte - channel current index (for via8233 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DEFINE_VIA_REGSET(name,val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) enum {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) VIA_REG_##name##_STATUS = (val),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) VIA_REG_##name##_CONTROL = (val) + 0x01,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) VIA_REG_##name##_TYPE = (val) + 0x02,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) VIA_REG_##name##_TABLE_PTR = (val) + 0x04,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) VIA_REG_##name##_CURR_PTR = (val) + 0x04,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) VIA_REG_##name##_STOP_IDX = (val) + 0x08,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) VIA_REG_##name##_CURR_COUNT = (val) + 0x0c,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* playback block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) DEFINE_VIA_REGSET(PLAYBACK, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) DEFINE_VIA_REGSET(CAPTURE, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DEFINE_VIA_REGSET(FM, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* AC'97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define VIA_REG_AC97 0x80 /* dword */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define VIA_REG_AC97_CODEC_ID_MASK (3<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define VIA_REG_AC97_CODEC_ID_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define VIA_REG_AC97_CODEC_ID_PRIMARY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define VIA_REG_AC97_CODEC_ID_SECONDARY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define VIA_REG_AC97_SECONDARY_VALID (1<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define VIA_REG_AC97_PRIMARY_VALID (1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define VIA_REG_AC97_BUSY (1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define VIA_REG_AC97_READ (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define VIA_REG_AC97_CMD_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define VIA_REG_AC97_CMD_MASK 0x7e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define VIA_REG_AC97_DATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define VIA_REG_AC97_DATA_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define VIA_REG_SGD_SHADOW 0x84 /* dword */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* via686 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define VIA_REG_SGD_STAT_PB_FLAG (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define VIA_REG_SGD_STAT_CP_FLAG (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define VIA_REG_SGD_STAT_FM_FLAG (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define VIA_REG_SGD_STAT_PB_EOL (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define VIA_REG_SGD_STAT_CP_EOL (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define VIA_REG_SGD_STAT_FM_EOL (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define VIA_REG_SGD_STAT_PB_STOP (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define VIA_REG_SGD_STAT_CP_STOP (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define VIA_REG_SGD_STAT_FM_STOP (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define VIA_REG_SGD_STAT_PB_ACTIVE (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define VIA_REG_SGD_STAT_CP_ACTIVE (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define VIA_REG_SGD_STAT_FM_ACTIVE (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* via8233 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define VIA8233_REG_SGD_STAT_FLAG (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define VIA8233_REG_SGD_STAT_EOL (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define VIA8233_REG_SGD_STAT_STOP (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define VIA8233_REG_SGD_STAT_ACTIVE (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define VIA8233_INTR_MASK(chan) ((VIA8233_REG_SGD_STAT_FLAG|VIA8233_REG_SGD_STAT_EOL) << ((chan) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define VIA8233_REG_SGD_CHAN_SDX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define VIA8233_REG_SGD_CHAN_MULTI 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define VIA8233_REG_SGD_CHAN_REC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define VIA8233_REG_SGD_CHAN_REC1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define VIA_REG_GPI_STATUS 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define VIA_REG_GPI_INTR 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* multi-channel and capture registers for via8233 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) DEFINE_VIA_REGSET(MULTPLAY, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) DEFINE_VIA_REGSET(CAPTURE_8233, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* via8233-specific registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define VIA_REG_OFS_PLAYBACK_VOLUME_L 0x02 /* byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define VIA_REG_OFS_PLAYBACK_VOLUME_R 0x03 /* byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define VIA_REG_OFS_MULTPLAY_FORMAT 0x02 /* byte - format and channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define VIA_REG_MULTPLAY_FMT_8BIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define VIA_REG_MULTPLAY_FMT_16BIT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define VIA_REG_MULTPLAY_FMT_CH_MASK 0x70 /* # channels << 4 (valid = 1,2,4,6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define VIA_REG_OFS_CAPTURE_FIFO 0x02 /* byte - bit 6 = fifo enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define VIA_REG_CAPTURE_FIFO_ENABLE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define VIA_DXS_MAX_VOLUME 31 /* max. volume (attenuation) of reg 0x32/33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define VIA_REG_CAPTURE_CHANNEL 0x63 /* byte - input select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define VIA_REG_CAPTURE_CHANNEL_MIC 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define VIA_REG_CAPTURE_CHANNEL_LINE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define VIA_REG_CAPTURE_SELECT_CODEC 0x03 /* recording source codec (0 = primary) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define VIA_TBL_BIT_FLAG 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define VIA_TBL_BIT_EOL 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* pci space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define VIA_ACLINK_STAT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define VIA_ACLINK_C11_READY 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define VIA_ACLINK_C10_READY 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define VIA_ACLINK_C01_READY 0x04 /* secondary codec ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define VIA_ACLINK_LOWPOWER 0x02 /* low-power state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define VIA_ACLINK_C00_READY 0x01 /* primary codec ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define VIA_ACLINK_CTRL 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define VIA_ACLINK_CTRL_ENABLE 0x80 /* 0: disable, 1: enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define VIA_ACLINK_CTRL_RESET 0x40 /* 0: assert, 1: de-assert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define VIA_ACLINK_CTRL_SYNC 0x20 /* 0: release SYNC, 1: force SYNC hi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define VIA_ACLINK_CTRL_SDO 0x10 /* 0: release SDO, 1: force SDO hi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define VIA_ACLINK_CTRL_VRA 0x08 /* 0: disable VRA, 1: enable VRA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define VIA_ACLINK_CTRL_PCM 0x04 /* 0: disable PCM, 1: enable PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define VIA_ACLINK_CTRL_FM 0x02 /* via686 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define VIA_ACLINK_CTRL_SB 0x01 /* via686 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define VIA_ACLINK_CTRL_INIT (VIA_ACLINK_CTRL_ENABLE|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) VIA_ACLINK_CTRL_RESET|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) VIA_ACLINK_CTRL_PCM|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) VIA_ACLINK_CTRL_VRA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define VIA_FUNC_ENABLE 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define VIA_FUNC_MIDI_PNP 0x80 /* FIXME: it's 0x40 in the datasheet! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define VIA_FUNC_MIDI_IRQMASK 0x40 /* FIXME: not documented! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define VIA_FUNC_RX2C_WRITE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define VIA_FUNC_SB_FIFO_EMPTY 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define VIA_FUNC_ENABLE_GAME 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define VIA_FUNC_ENABLE_FM 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define VIA_FUNC_ENABLE_MIDI 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define VIA_FUNC_ENABLE_SB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define VIA_PNP_CONTROL 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define VIA_FM_NMI_CTRL 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define VIA8233_VOLCHG_CTRL 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define VIA8233_SPDIF_CTRL 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define VIA8233_SPDIF_DX3 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define VIA8233_SPDIF_SLOT_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define VIA8233_SPDIF_SLOT_1011 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define VIA8233_SPDIF_SLOT_34 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define VIA8233_SPDIF_SLOT_78 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define VIA8233_SPDIF_SLOT_69 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define VIA_DXS_AUTO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define VIA_DXS_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define VIA_DXS_DISABLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define VIA_DXS_48K 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define VIA_DXS_NO_VRA 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define VIA_DXS_SRC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * pcm stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct snd_via_sg_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define VIA_TABLE_SIZE 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define VIA_MAX_BUFSIZE (1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct viadev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned int reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned long port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int direction; /* playback = 0, capture = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned int tbl_entries; /* # descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct snd_dma_buffer table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct snd_via_sg_table *idx_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* for recovery from the unexpected pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned int lastpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned int fragsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned int bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned int bufsize2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int hwptr_done; /* processed frame position in the buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int in_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int shadow_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) enum { TYPE_CARD_VIA686 = 1, TYPE_CARD_VIA8233 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) enum { TYPE_VIA686, TYPE_VIA8233, TYPE_VIA8233A };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define VIA_MAX_DEVS 7 /* 4 playback, 1 multi, 2 capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct via_rate_lock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct via82xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned long port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct resource *mpu_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int chip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned char revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned char old_legacy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned char old_legacy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) unsigned char legacy_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned char legacy_cfg_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned char spdif_ctrl_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned char capture_src_saved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned int mpu_port_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned char playback_volume[4][2]; /* for VIA8233/C/8235; default = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned char playback_volume_c[2]; /* for VIA8233/C/8235; default = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned int intr_mask; /* SGD_SHADOW mask to check interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned int num_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned int playback_devno, multi_devno, capture_devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct viadev devs[VIA_MAX_DEVS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct via_rate_lock rates[2]; /* playback and capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned int dxs_fixed: 1; /* DXS channel accepts only 48kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned int no_vra: 1; /* no need to set VRA on DXS channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned int dxs_src: 1; /* use full SRC capabilities of DXS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned int spdif_on: 1; /* only spdif rates work to external DACs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct snd_pcm *pcms[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct snd_rawmidi *rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct snd_kcontrol *dxs_controls[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct snd_ac97_bus *ac97_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct snd_ac97 *ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned int ac97_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned int ac97_secondary; /* secondary AC'97 codec is present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct snd_info_entry *proc_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct gameport *gameport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const struct pci_device_id snd_via82xx_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* 0x1106, 0x3058 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C686_5), TYPE_CARD_VIA686, }, /* 686A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* 0x1106, 0x3059 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_8233_5), TYPE_CARD_VIA8233, }, /* VT8233 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MODULE_DEVICE_TABLE(pci, snd_via82xx_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * allocate and initialize the descriptor buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * periods = number of periods
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * fragsize = period size in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int build_via_table(struct viadev *dev, struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned int periods, unsigned int fragsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned int i, idx, ofs, rest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct via82xx *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) __le32 *pgtbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (dev->table.area == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* the start of each lists must be aligned to 8 bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * but the kernel pages are much bigger, so we don't care
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PAGE_ALIGN(VIA_TABLE_SIZE * 2 * 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) &dev->table) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (! dev->idx_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev->idx_table = kmalloc_array(VIA_TABLE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) sizeof(*dev->idx_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (! dev->idx_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* fill the entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ofs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pgtbl = (__le32 *)dev->table.area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) for (i = 0; i < periods; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) rest = fragsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* fill descriptors for a period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * a period can be split to several descriptors if it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * over page boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned int flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (idx >= VIA_TABLE_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dev_err(&pci->dev, "too much table size!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) addr = snd_pcm_sgbuf_get_addr(substream, ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pgtbl[idx << 1] = cpu_to_le32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) r = snd_pcm_sgbuf_get_chunk_size(substream, ofs, rest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) rest -= r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (! rest) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (i == periods - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) flag = VIA_TBL_BIT_EOL; /* buffer boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) flag = VIA_TBL_BIT_FLAG; /* period boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) flag = 0; /* period continues to the next */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev_dbg(&pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) "tbl %d: at %d size %d (rest %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) idx, ofs, r, rest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pgtbl[(idx<<1) + 1] = cpu_to_le32(r | flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev->idx_table[idx].offset = ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dev->idx_table[idx].size = r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ofs += r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } while (rest > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev->tbl_entries = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dev->bufsize = periods * fragsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev->bufsize2 = dev->bufsize / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev->fragsize = fragsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int clean_via_table(struct viadev *dev, struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (dev->table.area) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) snd_dma_free_pages(&dev->table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev->table.area = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) kfree(dev->idx_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dev->idx_table = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * Basic I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static inline unsigned int snd_via82xx_codec_xread(struct via82xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return inl(VIAREG(chip, AC97));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static inline void snd_via82xx_codec_xwrite(struct via82xx *chip, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) outl(val, VIAREG(chip, AC97));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int snd_via82xx_codec_ready(struct via82xx *chip, int secondary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) unsigned int timeout = 1000; /* 1ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) while (timeout-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (!((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return val & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev_err(chip->card->dev, "codec_ready: codec %i is not ready [0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) secondary, snd_via82xx_codec_xread(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int snd_via82xx_codec_valid(struct via82xx *chip, int secondary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) unsigned int timeout = 1000; /* 1ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) unsigned int val, val1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) unsigned int stat = !secondary ? VIA_REG_AC97_PRIMARY_VALID :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) VIA_REG_AC97_SECONDARY_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) while (timeout-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) val = snd_via82xx_codec_xread(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) val1 = val & (VIA_REG_AC97_BUSY | stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (val1 == stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return val & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static void snd_via82xx_codec_wait(struct snd_ac97 *ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct via82xx *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) __always_unused int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) err = snd_via82xx_codec_ready(chip, ac97->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* here we need to wait fairly for long time.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (!nodelay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) msleep(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static void snd_via82xx_codec_write(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned short reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct via82xx *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) unsigned int xval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) xval = !ac97->num ? VIA_REG_AC97_CODEC_ID_PRIMARY : VIA_REG_AC97_CODEC_ID_SECONDARY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) xval <<= VIA_REG_AC97_CODEC_ID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) xval |= reg << VIA_REG_AC97_CMD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) xval |= val << VIA_REG_AC97_DATA_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) snd_via82xx_codec_xwrite(chip, xval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) snd_via82xx_codec_ready(chip, ac97->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static unsigned short snd_via82xx_codec_read(struct snd_ac97 *ac97, unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct via82xx *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) unsigned int xval, val = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int again = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) xval = ac97->num << VIA_REG_AC97_CODEC_ID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) xval |= ac97->num ? VIA_REG_AC97_SECONDARY_VALID : VIA_REG_AC97_PRIMARY_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) xval |= VIA_REG_AC97_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) xval |= (reg & 0x7f) << VIA_REG_AC97_CMD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (again++ > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) "codec_read: codec %i is not valid [0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ac97->num, snd_via82xx_codec_xread(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) snd_via82xx_codec_xwrite(chip, xval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) udelay (20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (snd_via82xx_codec_valid(chip, ac97->num) >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) udelay(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) val = snd_via82xx_codec_xread(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return val & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static void snd_via82xx_channel_reset(struct via82xx *chip, struct viadev *viadev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) outb(VIA_REG_CTRL_PAUSE | VIA_REG_CTRL_TERMINATE | VIA_REG_CTRL_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) VIADEV_REG(viadev, OFFSET_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) inb(VIADEV_REG(viadev, OFFSET_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) outb(0x00, VIADEV_REG(viadev, OFFSET_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* clear interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) outb(0x03, VIADEV_REG(viadev, OFFSET_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) outb(0x00, VIADEV_REG(viadev, OFFSET_TYPE)); /* for via686 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) // outl(0, VIADEV_REG(viadev, OFFSET_CURR_PTR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) viadev->lastpos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) viadev->hwptr_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * Interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * Used for 686 and 8233A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static irqreturn_t snd_via686_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct via82xx *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) status = inl(VIAREG(chip, SGD_SHADOW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (! (status & chip->intr_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (chip->rmidi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* check mpu401 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* check status for each stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) for (i = 0; i < chip->num_devs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct viadev *viadev = &chip->devs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) unsigned char c_status = inb(VIADEV_REG(viadev, OFFSET_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (! (c_status & (VIA_REG_STAT_EOL|VIA_REG_STAT_FLAG|VIA_REG_STAT_STOPPED)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (viadev->substream && viadev->running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * Update hwptr_done based on 'period elapsed'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * interrupts. We'll use it, when the chip returns 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * for OFFSET_CURR_COUNT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (c_status & VIA_REG_STAT_EOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) viadev->hwptr_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) viadev->hwptr_done += viadev->fragsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) viadev->in_interrupt = c_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) snd_pcm_period_elapsed(viadev->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) viadev->in_interrupt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) outb(c_status, VIADEV_REG(viadev, OFFSET_STATUS)); /* ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * Interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static irqreturn_t snd_via8233_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct via82xx *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int irqreturn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* check status for each stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) status = inl(VIAREG(chip, SGD_SHADOW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) for (i = 0; i < chip->num_devs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct viadev *viadev = &chip->devs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) unsigned char c_status, shadow_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) shadow_status = (status >> viadev->shadow_shift) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) (VIA8233_SHADOW_STAT_ACTIVE|VIA_REG_STAT_EOL|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) VIA_REG_STAT_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) c_status = shadow_status & (VIA_REG_STAT_EOL|VIA_REG_STAT_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (!c_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) substream = viadev->substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (substream && viadev->running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * Update hwptr_done based on 'period elapsed'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * interrupts. We'll use it, when the chip returns 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * for OFFSET_CURR_COUNT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (c_status & VIA_REG_STAT_EOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) viadev->hwptr_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) viadev->hwptr_done += viadev->fragsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) viadev->in_interrupt = c_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (shadow_status & VIA8233_SHADOW_STAT_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) viadev->in_interrupt |= VIA_REG_STAT_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) snd_pcm_period_elapsed(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) viadev->in_interrupt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) outb(c_status, VIADEV_REG(viadev, OFFSET_STATUS)); /* ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) irqreturn = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return IRQ_RETVAL(irqreturn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * PCM callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * trigger callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int snd_via82xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct via82xx *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct viadev *viadev = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (chip->chip_type != TYPE_VIA686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) val = VIA_REG_CTRL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) val |= VIA_REG_CTRL_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) viadev->running = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) val = VIA_REG_CTRL_TERMINATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) viadev->running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) val |= VIA_REG_CTRL_PAUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) viadev->running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) viadev->running = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) outb(val, VIADEV_REG(viadev, OFFSET_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (cmd == SNDRV_PCM_TRIGGER_STOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) snd_via82xx_channel_reset(chip, viadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * pointer callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * calculate the linear position at the given sg-buffer index and the rest count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define check_invalid_pos(viadev,pos) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ((pos) < viadev->lastpos && ((pos) >= viadev->bufsize2 ||\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) viadev->lastpos < viadev->bufsize2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static inline unsigned int calc_linear_pos(struct via82xx *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct viadev *viadev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) unsigned int idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) unsigned int size, base, res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) size = viadev->idx_table[idx].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) base = viadev->idx_table[idx].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) res = base + size - count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (res >= viadev->bufsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) res -= viadev->bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* check the validity of the calculated position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (size < count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) "invalid via82xx_cur_ptr (size = %d, count = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) (int)size, (int)count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) res = viadev->lastpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (! count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* Some mobos report count = 0 on the DMA boundary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * i.e. count = size indeed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * Let's check whether this step is above the expected size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int delta = res - viadev->lastpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (delta < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) delta += viadev->bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if ((unsigned int)delta > viadev->fragsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) res = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (check_invalid_pos(viadev, res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #ifdef POINTER_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) "fail: idx = %i/%i, lastpos = 0x%x, bufsize2 = 0x%x, offsize = 0x%x, size = 0x%x, count = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) idx, viadev->tbl_entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) viadev->lastpos, viadev->bufsize2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) viadev->idx_table[idx].offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) viadev->idx_table[idx].size, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* count register returns full size when end of buffer is reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) res = base + size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (check_invalid_pos(viadev, res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) "invalid via82xx_cur_ptr (2), using last valid pointer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) res = viadev->lastpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * get the current pointer on via686
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static snd_pcm_uframes_t snd_via686_pcm_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct via82xx *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct viadev *viadev = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) unsigned int idx, ptr, count, res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (snd_BUG_ON(!viadev->tbl_entries))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (!(inb(VIADEV_REG(viadev, OFFSET_STATUS)) & VIA_REG_STAT_ACTIVE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) count = inl(VIADEV_REG(viadev, OFFSET_CURR_COUNT)) & 0xffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* The via686a does not have the current index register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * so we need to calculate the index from CURR_PTR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ptr = inl(VIADEV_REG(viadev, OFFSET_CURR_PTR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (ptr <= (unsigned int)viadev->table.addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) else /* CURR_PTR holds the address + 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) idx = ((ptr - (unsigned int)viadev->table.addr) / 8 - 1) % viadev->tbl_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) res = calc_linear_pos(chip, viadev, idx, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) viadev->lastpos = res; /* remember the last position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return bytes_to_frames(substream->runtime, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * get the current pointer on via823x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static snd_pcm_uframes_t snd_via8233_pcm_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct via82xx *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct viadev *viadev = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) unsigned int idx, count, res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (snd_BUG_ON(!viadev->tbl_entries))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) count = inl(VIADEV_REG(viadev, OFFSET_CURR_COUNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) status = viadev->in_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) status = inb(VIADEV_REG(viadev, OFFSET_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* An apparent bug in the 8251 is worked around by sending a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * REG_CTRL_START. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (chip->revision == VIA_REV_8251 && (status & VIA_REG_STAT_EOL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) snd_via82xx_pcm_trigger(substream, SNDRV_PCM_TRIGGER_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (!(status & VIA_REG_STAT_ACTIVE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (count & 0xffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) idx = count >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (idx >= viadev->tbl_entries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #ifdef POINTER_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) "fail: invalid idx = %i/%i\n", idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) viadev->tbl_entries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) res = viadev->lastpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) count &= 0xffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) res = calc_linear_pos(chip, viadev, idx, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) res = viadev->hwptr_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (!viadev->in_interrupt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (status & VIA_REG_STAT_EOL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (status & VIA_REG_STAT_FLAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) res += viadev->fragsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) viadev->lastpos = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return bytes_to_frames(substream->runtime, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * hw_params callback:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * allocate the buffer and build up the buffer description table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static int snd_via82xx_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct via82xx *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct viadev *viadev = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return build_via_table(viadev, substream, chip->pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) params_periods(hw_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) params_period_bytes(hw_params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * hw_free callback:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * clean up the buffer description table and release the buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static int snd_via82xx_hw_free(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct via82xx *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct viadev *viadev = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) clean_via_table(viadev, substream, chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * set up the table pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static void snd_via82xx_set_table_ptr(struct via82xx *chip, struct viadev *viadev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) snd_via82xx_codec_ready(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) outl((u32)viadev->table.addr, VIADEV_REG(viadev, OFFSET_TABLE_PTR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) snd_via82xx_codec_ready(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * prepare callback for playback and capture on via686
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static void via686_setup_format(struct via82xx *chip, struct viadev *viadev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct snd_pcm_runtime *runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) snd_via82xx_channel_reset(chip, viadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* this must be set after channel_reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) snd_via82xx_set_table_ptr(chip, viadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) outb(VIA_REG_TYPE_AUTOSTART |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) (runtime->format == SNDRV_PCM_FORMAT_S16_LE ? VIA_REG_TYPE_16BIT : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) (runtime->channels > 1 ? VIA_REG_TYPE_STEREO : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ((viadev->reg_offset & 0x10) == 0 ? VIA_REG_TYPE_INT_LSAMPLE : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) VIA_REG_TYPE_INT_EOL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) VIA_REG_TYPE_INT_FLAG, VIADEV_REG(viadev, OFFSET_TYPE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static int snd_via686_playback_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct via82xx *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct viadev *viadev = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) snd_ac97_set_rate(chip->ac97, AC97_PCM_FRONT_DAC_RATE, runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) snd_ac97_set_rate(chip->ac97, AC97_SPDIF, runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) via686_setup_format(chip, viadev, runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static int snd_via686_capture_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct via82xx *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct viadev *viadev = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) snd_ac97_set_rate(chip->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) via686_setup_format(chip, viadev, runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) * lock the current rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static int via_lock_rate(struct via_rate_lock *rec, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) int changed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) spin_lock_irq(&rec->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (rec->rate != rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (rec->rate && rec->used > 1) /* already set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) changed = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) rec->rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) changed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) spin_unlock_irq(&rec->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * prepare callback for DSX playback on via823x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static int snd_via8233_playback_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct via82xx *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) struct viadev *viadev = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) int ac97_rate = chip->dxs_src ? 48000 : runtime->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) int rate_changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) u32 rbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if ((rate_changed = via_lock_rate(&chip->rates[0], ac97_rate)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return rate_changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (rate_changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) snd_ac97_set_rate(chip->ac97, AC97_PCM_FRONT_DAC_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) chip->no_vra ? 48000 : runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (chip->spdif_on && viadev->reg_offset == 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) snd_ac97_set_rate(chip->ac97, AC97_SPDIF, runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (runtime->rate == 48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) rbits = 0xfffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) rbits = (0x100000 / 48000) * runtime->rate +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) ((0x100000 % 48000) * runtime->rate) / 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) snd_BUG_ON(rbits & ~0xfffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) snd_via82xx_channel_reset(chip, viadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) snd_via82xx_set_table_ptr(chip, viadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) outb(chip->playback_volume[viadev->reg_offset / 0x10][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) VIADEV_REG(viadev, OFS_PLAYBACK_VOLUME_L));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) outb(chip->playback_volume[viadev->reg_offset / 0x10][1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) VIADEV_REG(viadev, OFS_PLAYBACK_VOLUME_R));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) outl((runtime->format == SNDRV_PCM_FORMAT_S16_LE ? VIA8233_REG_TYPE_16BIT : 0) | /* format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) (runtime->channels > 1 ? VIA8233_REG_TYPE_STEREO : 0) | /* stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) rbits | /* rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) 0xff000000, /* STOP index is never reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) VIADEV_REG(viadev, OFFSET_STOP_IDX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) snd_via82xx_codec_ready(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * prepare callback for multi-channel playback on via823x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static int snd_via8233_multi_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) struct via82xx *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) struct viadev *viadev = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) unsigned int slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) int fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (via_lock_rate(&chip->rates[0], runtime->rate) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) snd_ac97_set_rate(chip->ac97, AC97_PCM_FRONT_DAC_RATE, runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) snd_ac97_set_rate(chip->ac97, AC97_PCM_SURR_DAC_RATE, runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) snd_ac97_set_rate(chip->ac97, AC97_PCM_LFE_DAC_RATE, runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) snd_ac97_set_rate(chip->ac97, AC97_SPDIF, runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) snd_via82xx_channel_reset(chip, viadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) snd_via82xx_set_table_ptr(chip, viadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) fmt = (runtime->format == SNDRV_PCM_FORMAT_S16_LE) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) VIA_REG_MULTPLAY_FMT_16BIT : VIA_REG_MULTPLAY_FMT_8BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) fmt |= runtime->channels << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) outb(fmt, VIADEV_REG(viadev, OFS_MULTPLAY_FORMAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (chip->revision == VIA_REV_8233A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) slots = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* set sample number to slot 3, 4, 7, 8, 6, 9 (for VIA8233/C,8235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) /* corresponding to FL, FR, RL, RR, C, LFE ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) switch (runtime->channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) case 1: slots = (1<<0) | (1<<4); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) case 2: slots = (1<<0) | (2<<4); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) case 3: slots = (1<<0) | (2<<4) | (5<<8); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) case 4: slots = (1<<0) | (2<<4) | (3<<8) | (4<<12); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) case 5: slots = (1<<0) | (2<<4) | (3<<8) | (4<<12) | (5<<16); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) case 6: slots = (1<<0) | (2<<4) | (3<<8) | (4<<12) | (5<<16) | (6<<20); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) default: slots = 0; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /* STOP index is never reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) outl(0xff000000 | slots, VIADEV_REG(viadev, OFFSET_STOP_IDX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) snd_via82xx_codec_ready(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * prepare callback for capture on via823x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static int snd_via8233_capture_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct via82xx *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct viadev *viadev = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (via_lock_rate(&chip->rates[1], runtime->rate) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) snd_ac97_set_rate(chip->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) snd_via82xx_channel_reset(chip, viadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) snd_via82xx_set_table_ptr(chip, viadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) outb(VIA_REG_CAPTURE_FIFO_ENABLE, VIADEV_REG(viadev, OFS_CAPTURE_FIFO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) outl((runtime->format == SNDRV_PCM_FORMAT_S16_LE ? VIA8233_REG_TYPE_16BIT : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) (runtime->channels > 1 ? VIA8233_REG_TYPE_STEREO : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) 0xff000000, /* STOP index is never reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) VIADEV_REG(viadev, OFFSET_STOP_IDX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) snd_via82xx_codec_ready(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * pcm hardware definition, identical for both playback and capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static const struct snd_pcm_hardware snd_via82xx_hw =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* SNDRV_PCM_INFO_RESUME | */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) SNDRV_PCM_INFO_PAUSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .rate_min = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .buffer_bytes_max = VIA_MAX_BUFSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .period_bytes_min = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .period_bytes_max = VIA_MAX_BUFSIZE / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .periods_max = VIA_TABLE_SIZE / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * open callback skeleton
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static int snd_via82xx_pcm_open(struct via82xx *chip, struct viadev *viadev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) struct via_rate_lock *ratep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) bool use_src = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) runtime->hw = snd_via82xx_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /* set the hw rate condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) ratep = &chip->rates[viadev->direction];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) spin_lock_irq(&ratep->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) ratep->used++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (chip->spdif_on && viadev->reg_offset == 0x30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /* DXS#3 and spdif is on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) runtime->hw.rates = chip->ac97->rates[AC97_RATES_SPDIF];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) snd_pcm_limit_hw_rates(runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) } else if (chip->dxs_fixed && viadev->reg_offset < 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* fixed DXS playback rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) runtime->hw.rates = SNDRV_PCM_RATE_48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) runtime->hw.rate_min = runtime->hw.rate_max = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) } else if (chip->dxs_src && viadev->reg_offset < 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* use full SRC capabilities of DXS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) runtime->hw.rates = (SNDRV_PCM_RATE_CONTINUOUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) SNDRV_PCM_RATE_8000_48000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) runtime->hw.rate_min = 8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) runtime->hw.rate_max = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) use_src = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) } else if (! ratep->rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) int idx = viadev->direction ? AC97_RATES_ADC : AC97_RATES_FRONT_DAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) runtime->hw.rates = chip->ac97->rates[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) snd_pcm_limit_hw_rates(runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /* a fixed rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) runtime->hw.rate_max = runtime->hw.rate_min = ratep->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) spin_unlock_irq(&ratep->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* we may remove following constaint when we modify table entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) in interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (use_src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) err = snd_pcm_hw_rule_noresample(runtime, 48000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) runtime->private_data = viadev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) viadev->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * open callback for playback on via686
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static int snd_via686_playback_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) struct via82xx *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) struct viadev *viadev = &chip->devs[chip->playback_devno + substream->number];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if ((err = snd_via82xx_pcm_open(chip, viadev, substream)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * open callback for playback on via823x DXS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) static int snd_via8233_playback_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct via82xx *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct viadev *viadev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) unsigned int stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) viadev = &chip->devs[chip->playback_devno + substream->number];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if ((err = snd_via82xx_pcm_open(chip, viadev, substream)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) stream = viadev->reg_offset / 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (chip->dxs_controls[stream]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) chip->playback_volume[stream][0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) VIA_DXS_MAX_VOLUME - (dxs_init_volume & 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) chip->playback_volume[stream][1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) VIA_DXS_MAX_VOLUME - (dxs_init_volume & 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) chip->dxs_controls[stream]->vd[0].access &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) SNDRV_CTL_EVENT_MASK_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) &chip->dxs_controls[stream]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * open callback for playback on via823x multi-channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static int snd_via8233_multi_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) struct via82xx *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) struct viadev *viadev = &chip->devs[chip->multi_devno];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) /* channels constraint for VIA8233A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) * 3 and 5 channels are not supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static const unsigned int channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) 1, 2, 4, 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static const struct snd_pcm_hw_constraint_list hw_constraints_channels = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .count = ARRAY_SIZE(channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .list = channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if ((err = snd_via82xx_pcm_open(chip, viadev, substream)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) substream->runtime->hw.channels_max = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (chip->revision == VIA_REV_8233A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) snd_pcm_hw_constraint_list(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) SNDRV_PCM_HW_PARAM_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) &hw_constraints_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * open callback for capture on via686 and via823x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) static int snd_via82xx_capture_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) struct via82xx *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) struct viadev *viadev = &chip->devs[chip->capture_devno + substream->pcm->device];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return snd_via82xx_pcm_open(chip, viadev, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * close callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static int snd_via82xx_pcm_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) struct via82xx *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) struct viadev *viadev = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) struct via_rate_lock *ratep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /* release the rate lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) ratep = &chip->rates[viadev->direction];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) spin_lock_irq(&ratep->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ratep->used--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (! ratep->used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) ratep->rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) spin_unlock_irq(&ratep->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (! ratep->rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (! viadev->direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) snd_ac97_update_power(chip->ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) AC97_PCM_FRONT_DAC_RATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) snd_ac97_update_power(chip->ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) AC97_PCM_SURR_DAC_RATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) snd_ac97_update_power(chip->ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) AC97_PCM_LFE_DAC_RATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) snd_ac97_update_power(chip->ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) AC97_PCM_LR_ADC_RATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) viadev->substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static int snd_via8233_playback_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) struct via82xx *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) struct viadev *viadev = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) unsigned int stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) stream = viadev->reg_offset / 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (chip->dxs_controls[stream]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) chip->dxs_controls[stream]->vd[0].access |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) &chip->dxs_controls[stream]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return snd_via82xx_pcm_close(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) /* via686 playback callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static const struct snd_pcm_ops snd_via686_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .open = snd_via686_playback_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .close = snd_via82xx_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .hw_params = snd_via82xx_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .hw_free = snd_via82xx_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .prepare = snd_via686_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .trigger = snd_via82xx_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .pointer = snd_via686_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) /* via686 capture callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) static const struct snd_pcm_ops snd_via686_capture_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .open = snd_via82xx_capture_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .close = snd_via82xx_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .hw_params = snd_via82xx_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .hw_free = snd_via82xx_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .prepare = snd_via686_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .trigger = snd_via82xx_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .pointer = snd_via686_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /* via823x DSX playback callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) static const struct snd_pcm_ops snd_via8233_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .open = snd_via8233_playback_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .close = snd_via8233_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .hw_params = snd_via82xx_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .hw_free = snd_via82xx_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .prepare = snd_via8233_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .trigger = snd_via82xx_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .pointer = snd_via8233_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /* via823x multi-channel playback callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) static const struct snd_pcm_ops snd_via8233_multi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .open = snd_via8233_multi_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .close = snd_via82xx_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .hw_params = snd_via82xx_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .hw_free = snd_via82xx_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .prepare = snd_via8233_multi_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .trigger = snd_via82xx_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .pointer = snd_via8233_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) /* via823x capture callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) static const struct snd_pcm_ops snd_via8233_capture_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .open = snd_via82xx_capture_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .close = snd_via82xx_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .hw_params = snd_via82xx_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .hw_free = snd_via82xx_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .prepare = snd_via8233_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .trigger = snd_via82xx_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .pointer = snd_via8233_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static void init_viadev(struct via82xx *chip, int idx, unsigned int reg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) int shadow_pos, int direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) chip->devs[idx].reg_offset = reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) chip->devs[idx].shadow_shift = shadow_pos * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) chip->devs[idx].direction = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) chip->devs[idx].port = chip->port + reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * create pcm instances for VIA8233, 8233C and 8235 (not 8233A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) static int snd_via8233_pcm_new(struct via82xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) struct snd_pcm_chmap *chmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) chip->playback_devno = 0; /* x 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) chip->multi_devno = 4; /* x 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) chip->capture_devno = 5; /* x 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) chip->num_devs = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) chip->intr_mask = 0x33033333; /* FLAG|EOL for rec0-1, mc, sdx0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /* PCM #0: 4 DSX playbacks and 1 capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) err = snd_pcm_new(chip->card, chip->card->shortname, 0, 4, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_via8233_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_via8233_capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) strcpy(pcm->name, chip->card->shortname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) chip->pcms[0] = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /* set up playbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) init_viadev(chip, i, 0x10 * i, i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) init_viadev(chip, chip->capture_devno, VIA_REG_CAPTURE_8233_STATUS, 6, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) &chip->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) 64*1024, VIA_MAX_BUFSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) snd_pcm_std_chmaps, 2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) &chmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /* PCM #1: multi-channel playback and 2nd capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) err = snd_pcm_new(chip->card, chip->card->shortname, 1, 1, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_via8233_multi_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_via8233_capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) strcpy(pcm->name, chip->card->shortname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) chip->pcms[1] = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) /* set up playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) init_viadev(chip, chip->multi_devno, VIA_REG_MULTPLAY_STATUS, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /* set up capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) init_viadev(chip, chip->capture_devno + 1, VIA_REG_CAPTURE_8233_STATUS + 0x10, 7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) &chip->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) 64*1024, VIA_MAX_BUFSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) snd_pcm_alt_chmaps, 6, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) &chmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) chip->ac97->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) * create pcm instances for VIA8233A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) static int snd_via8233a_pcm_new(struct via82xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) struct snd_pcm_chmap *chmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) chip->multi_devno = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) chip->playback_devno = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) chip->capture_devno = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) chip->num_devs = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) chip->intr_mask = 0x03033000; /* FLAG|EOL for rec0, mc, sdx3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) /* PCM #0: multi-channel playback and capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) err = snd_pcm_new(chip->card, chip->card->shortname, 0, 1, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_via8233_multi_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_via8233_capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) strcpy(pcm->name, chip->card->shortname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) chip->pcms[0] = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) /* set up playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) init_viadev(chip, chip->multi_devno, VIA_REG_MULTPLAY_STATUS, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /* capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) init_viadev(chip, chip->capture_devno, VIA_REG_CAPTURE_8233_STATUS, 6, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) &chip->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) 64*1024, VIA_MAX_BUFSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) snd_pcm_alt_chmaps, 6, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) &chmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) chip->ac97->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* SPDIF supported? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (! ac97_can_spdif(chip->ac97))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) /* PCM #1: DXS3 playback (for spdif) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) err = snd_pcm_new(chip->card, chip->card->shortname, 1, 1, 0, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_via8233_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) strcpy(pcm->name, chip->card->shortname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) chip->pcms[1] = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /* set up playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) init_viadev(chip, chip->playback_devno, 0x30, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) &chip->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) 64*1024, VIA_MAX_BUFSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) * create a pcm instance for via686a/b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) static int snd_via686_pcm_new(struct via82xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) chip->playback_devno = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) chip->capture_devno = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) chip->num_devs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) chip->intr_mask = 0x77; /* FLAG | EOL for PB, CP, FM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) err = snd_pcm_new(chip->card, chip->card->shortname, 0, 1, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_via686_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_via686_capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) strcpy(pcm->name, chip->card->shortname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) chip->pcms[0] = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) init_viadev(chip, 0, VIA_REG_PLAYBACK_STATUS, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) init_viadev(chip, 1, VIA_REG_CAPTURE_STATUS, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) &chip->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) 64*1024, VIA_MAX_BUFSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) * Mixer part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static int snd_via8233_capture_source_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) /* formerly they were "Line" and "Mic", but it looks like that they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) * have nothing to do with the actual physical connections...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) static const char * const texts[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) "Input1", "Input2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) return snd_ctl_enum_info(uinfo, 1, 2, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) static int snd_via8233_capture_source_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) struct via82xx *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) unsigned long port = chip->port + (kcontrol->id.index ? (VIA_REG_CAPTURE_CHANNEL + 0x10) : VIA_REG_CAPTURE_CHANNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) ucontrol->value.enumerated.item[0] = inb(port) & VIA_REG_CAPTURE_CHANNEL_MIC ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) static int snd_via8233_capture_source_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) struct via82xx *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) unsigned long port = chip->port + (kcontrol->id.index ? (VIA_REG_CAPTURE_CHANNEL + 0x10) : VIA_REG_CAPTURE_CHANNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) u8 val, oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) oval = inb(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) val = oval & ~VIA_REG_CAPTURE_CHANNEL_MIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) if (ucontrol->value.enumerated.item[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) val |= VIA_REG_CAPTURE_CHANNEL_MIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (val != oval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) outb(val, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) return val != oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) static struct snd_kcontrol_new snd_via8233_capture_source = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .name = "Input Source Select",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .info = snd_via8233_capture_source_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .get = snd_via8233_capture_source_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .put = snd_via8233_capture_source_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) #define snd_via8233_dxs3_spdif_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) static int snd_via8233_dxs3_spdif_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) struct via82xx *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) pci_read_config_byte(chip->pci, VIA8233_SPDIF_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) ucontrol->value.integer.value[0] = (val & VIA8233_SPDIF_DX3) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) static int snd_via8233_dxs3_spdif_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) struct via82xx *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) u8 val, oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) pci_read_config_byte(chip->pci, VIA8233_SPDIF_CTRL, &oval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) val = oval & ~VIA8233_SPDIF_DX3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) if (ucontrol->value.integer.value[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) val |= VIA8233_SPDIF_DX3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) /* save the spdif flag for rate filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) chip->spdif_on = ucontrol->value.integer.value[0] ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) if (val != oval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) pci_write_config_byte(chip->pci, VIA8233_SPDIF_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) static const struct snd_kcontrol_new snd_via8233_dxs3_spdif_control = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .info = snd_via8233_dxs3_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .get = snd_via8233_dxs3_spdif_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .put = snd_via8233_dxs3_spdif_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) static int snd_via8233_dxs_volume_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) uinfo->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) uinfo->value.integer.max = VIA_DXS_MAX_VOLUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static int snd_via8233_dxs_volume_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) struct via82xx *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) unsigned int idx = kcontrol->id.subdevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) ucontrol->value.integer.value[0] = VIA_DXS_MAX_VOLUME - chip->playback_volume[idx][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) ucontrol->value.integer.value[1] = VIA_DXS_MAX_VOLUME - chip->playback_volume[idx][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) static int snd_via8233_pcmdxs_volume_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) struct via82xx *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) ucontrol->value.integer.value[0] = VIA_DXS_MAX_VOLUME - chip->playback_volume_c[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) ucontrol->value.integer.value[1] = VIA_DXS_MAX_VOLUME - chip->playback_volume_c[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) static int snd_via8233_dxs_volume_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) struct via82xx *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) unsigned int idx = kcontrol->id.subdevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) unsigned long port = chip->port + 0x10 * idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) int i, change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) val = ucontrol->value.integer.value[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) if (val > VIA_DXS_MAX_VOLUME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) val = VIA_DXS_MAX_VOLUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) val = VIA_DXS_MAX_VOLUME - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) change |= val != chip->playback_volume[idx][i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) if (change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) chip->playback_volume[idx][i] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) outb(val, port + VIA_REG_OFS_PLAYBACK_VOLUME_L + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) static int snd_via8233_pcmdxs_volume_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) struct via82xx *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) int i, change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) val = ucontrol->value.integer.value[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) if (val > VIA_DXS_MAX_VOLUME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) val = VIA_DXS_MAX_VOLUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) val = VIA_DXS_MAX_VOLUME - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (val != chip->playback_volume_c[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) chip->playback_volume_c[i] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) for (idx = 0; idx < 4; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) unsigned long port = chip->port + 0x10 * idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) chip->playback_volume[idx][i] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) outb(val, port + VIA_REG_OFS_PLAYBACK_VOLUME_L + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) static const DECLARE_TLV_DB_SCALE(db_scale_dxs, -4650, 150, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) static const struct snd_kcontrol_new snd_via8233_pcmdxs_volume_control = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .name = "PCM Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) SNDRV_CTL_ELEM_ACCESS_TLV_READ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .info = snd_via8233_dxs_volume_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .get = snd_via8233_pcmdxs_volume_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .put = snd_via8233_pcmdxs_volume_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .tlv = { .p = db_scale_dxs }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) static const struct snd_kcontrol_new snd_via8233_dxs_volume_control = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .device = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) /* .subdevice set later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .name = "PCM Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) SNDRV_CTL_ELEM_ACCESS_TLV_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) SNDRV_CTL_ELEM_ACCESS_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .info = snd_via8233_dxs_volume_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .get = snd_via8233_dxs_volume_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .put = snd_via8233_dxs_volume_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .tlv = { .p = db_scale_dxs }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) static void snd_via82xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) struct via82xx *chip = bus->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) chip->ac97_bus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) static void snd_via82xx_mixer_free_ac97(struct snd_ac97 *ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) struct via82xx *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) chip->ac97 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) static const struct ac97_quirk ac97_quirks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .subvendor = 0x1106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .subdevice = 0x4161,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .codec_id = 0x56494161, /* VT1612A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .name = "Soltek SL-75DRV5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .type = AC97_TUNE_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) { /* FIXME: which codec? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .subvendor = 0x1106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .subdevice = 0x4161,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .name = "ASRock K7VT2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .subvendor = 0x110a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .subdevice = 0x0079,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .name = "Fujitsu Siemens D1289",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .subvendor = 0x1019,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .subdevice = 0x0a81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .name = "ECS K7VTA3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .subvendor = 0x1019,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .subdevice = 0x0a85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .name = "ECS L7VMM2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .subvendor = 0x1019,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .subdevice = 0x1841,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .name = "ECS K7VTA3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .subvendor = 0x1849,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .subdevice = 0x3059,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .name = "ASRock K7VM2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .type = AC97_TUNE_HP_ONLY /* VT1616 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) .subvendor = 0x14cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .subdevice = 0x7002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .name = "Unknown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .type = AC97_TUNE_ALC_JACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .subvendor = 0x1071,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .subdevice = 0x8590,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .name = "Mitac Mobo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .type = AC97_TUNE_ALC_JACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .subvendor = 0x161f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .subdevice = 0x202b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .name = "Arima Notebook",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .type = AC97_TUNE_HP_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .subvendor = 0x161f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .subdevice = 0x2032,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .name = "Targa Traveller 811",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .type = AC97_TUNE_HP_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .subvendor = 0x161f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .subdevice = 0x2032,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .name = "m680x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .type = AC97_TUNE_HP_ONLY, /* http://launchpad.net/bugs/38546 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .subvendor = 0x1297,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .subdevice = 0xa232,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .name = "Shuttle AK32VN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) { } /* terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) static int snd_via82xx_mixer_new(struct via82xx *chip, const char *quirk_override)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) struct snd_ac97_template ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) static const struct snd_ac97_bus_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .write = snd_via82xx_codec_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .read = snd_via82xx_codec_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .wait = snd_via82xx_codec_wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) chip->ac97_bus->private_free = snd_via82xx_mixer_free_ac97_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) chip->ac97_bus->clock = chip->ac97_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) memset(&ac97, 0, sizeof(ac97));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) ac97.private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) ac97.private_free = snd_via82xx_mixer_free_ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) ac97.pci = chip->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) snd_ac97_tune_hardware(chip->ac97, ac97_quirks, quirk_override);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) if (chip->chip_type != TYPE_VIA686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) /* use slot 10/11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) snd_ac97_update_bits(chip->ac97, AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) #define JOYSTICK_ADDR 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) static int snd_via686_create_gameport(struct via82xx *chip, unsigned char *legacy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) struct gameport *gp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) if (!joystick)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) r = request_region(JOYSTICK_ADDR, 8, "VIA686 gameport");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) if (!r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) dev_warn(chip->card->dev, "cannot reserve joystick port %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) JOYSTICK_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) chip->gameport = gp = gameport_allocate_port();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) if (!gp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) "cannot allocate memory for gameport\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) release_and_free_resource(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) gameport_set_name(gp, "VIA686 Gameport");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) gameport_set_dev_parent(gp, &chip->pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) gp->io = JOYSTICK_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) gameport_set_port_data(gp, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) /* Enable legacy joystick port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) *legacy |= VIA_FUNC_ENABLE_GAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE, *legacy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) gameport_register_port(chip->gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) static void snd_via686_free_gameport(struct via82xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) if (chip->gameport) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) struct resource *r = gameport_get_port_data(chip->gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) gameport_unregister_port(chip->gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) chip->gameport = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) release_and_free_resource(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) static inline int snd_via686_create_gameport(struct via82xx *chip, unsigned char *legacy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) static inline void snd_via686_free_gameport(struct via82xx *chip) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) static int snd_via8233_init_misc(struct via82xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) int i, err, caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) caps = chip->chip_type == TYPE_VIA8233A ? 1 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) for (i = 0; i < caps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) snd_via8233_capture_source.index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_via8233_capture_source, chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) if (ac97_can_spdif(chip->ac97)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_via8233_dxs3_spdif_control, chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) if (chip->chip_type != TYPE_VIA8233A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) /* when no h/w PCM volume control is found, use DXS volume control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) * as the PCM vol control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) struct snd_ctl_elem_id sid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) memset(&sid, 0, sizeof(sid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) strcpy(sid.name, "PCM Playback Volume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) sid.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) if (! snd_ctl_find_id(chip->card, &sid)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) dev_info(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) "Using DXS as PCM Playback\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_via8233_pcmdxs_volume_control, chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) else /* Using DXS when PCM emulation is enabled is really weird */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) for (i = 0; i < 4; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) kctl = snd_ctl_new1(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) &snd_via8233_dxs_volume_control, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) if (!kctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) kctl->id.subdevice = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) err = snd_ctl_add(chip->card, kctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) chip->dxs_controls[i] = kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) /* select spdif data slot 10/11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) pci_read_config_byte(chip->pci, VIA8233_SPDIF_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) val = (val & ~VIA8233_SPDIF_SLOT_MASK) | VIA8233_SPDIF_SLOT_1011;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) val &= ~VIA8233_SPDIF_DX3; /* SPDIF off as default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) pci_write_config_byte(chip->pci, VIA8233_SPDIF_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) static int snd_via686_init_misc(struct via82xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) unsigned char legacy, legacy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) int rev_h = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) legacy = chip->old_legacy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) legacy_cfg = chip->old_legacy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) legacy |= VIA_FUNC_MIDI_IRQMASK; /* FIXME: correct? (disable MIDI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) legacy &= ~VIA_FUNC_ENABLE_GAME; /* disable joystick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) if (chip->revision >= VIA_REV_686_H) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) rev_h = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) if (mpu_port >= 0x200) { /* force MIDI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) mpu_port &= 0xfffc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) pci_write_config_dword(chip->pci, 0x18, mpu_port | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) chip->mpu_port_saved = mpu_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) mpu_port = pci_resource_start(chip->pci, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) switch (mpu_port) { /* force MIDI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) case 0x300:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) case 0x310:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) case 0x320:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) case 0x330:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) legacy_cfg &= ~(3 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) legacy_cfg |= (mpu_port & 0x0030) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) default: /* no, use BIOS settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) if (legacy & VIA_FUNC_ENABLE_MIDI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) mpu_port = 0x300 + ((legacy_cfg & 0x000c) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) if (mpu_port >= 0x200 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) (chip->mpu_res = request_region(mpu_port, 2, "VIA82xx MPU401"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) if (rev_h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) legacy |= VIA_FUNC_MIDI_PNP; /* enable PCI I/O 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) legacy |= VIA_FUNC_ENABLE_MIDI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) if (rev_h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) legacy &= ~VIA_FUNC_MIDI_PNP; /* disable PCI I/O 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) legacy &= ~VIA_FUNC_ENABLE_MIDI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) mpu_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE, legacy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) pci_write_config_byte(chip->pci, VIA_PNP_CONTROL, legacy_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) if (chip->mpu_res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) if (snd_mpu401_uart_new(chip->card, 0, MPU401_HW_VIA686A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) mpu_port, MPU401_INFO_INTEGRATED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) MPU401_INFO_IRQ_HOOK, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) &chip->rmidi) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) dev_warn(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) "unable to initialize MPU-401 at 0x%lx, skipping\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) mpu_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) legacy &= ~VIA_FUNC_ENABLE_MIDI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) legacy &= ~VIA_FUNC_MIDI_IRQMASK; /* enable MIDI interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE, legacy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) snd_via686_create_gameport(chip, &legacy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) chip->legacy_saved = legacy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) chip->legacy_cfg_saved = legacy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) * proc interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) static void snd_via82xx_proc_read(struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) struct via82xx *chip = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) snd_iprintf(buffer, "%s\n\n", chip->card->longname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) for (i = 0; i < 0xa0; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) snd_iprintf(buffer, "%02x: %08x\n", i, inl(chip->port + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) static void snd_via82xx_proc_init(struct via82xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) snd_card_ro_proc_new(chip->card, "via82xx", chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) snd_via82xx_proc_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) static int snd_via82xx_chip_init(struct via82xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) unsigned long end_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) unsigned char pval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) #if 0 /* broken on K7M? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) if (chip->chip_type == TYPE_VIA686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) /* disable all legacy ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) pci_read_config_byte(chip->pci, VIA_ACLINK_STAT, &pval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) if (! (pval & VIA_ACLINK_C00_READY)) { /* codec not ready? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) /* deassert ACLink reset, force SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) VIA_ACLINK_CTRL_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) VIA_ACLINK_CTRL_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) VIA_ACLINK_CTRL_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) #if 1 /* FIXME: should we do full reset here for all chip models? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) /* deassert ACLink reset, force SYNC (warm AC'97 reset) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) VIA_ACLINK_CTRL_RESET|VIA_ACLINK_CTRL_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) /* ACLink on, deassert ACLink reset, VSR, SGD data out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) /* note - FM data out has trouble with non VRA codecs !! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL, VIA_ACLINK_CTRL_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) /* Make sure VRA is enabled, in case we didn't do a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) * complete codec reset, above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) pci_read_config_byte(chip->pci, VIA_ACLINK_CTRL, &pval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) if ((pval & VIA_ACLINK_CTRL_INIT) != VIA_ACLINK_CTRL_INIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) /* ACLink on, deassert ACLink reset, VSR, SGD data out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) /* note - FM data out has trouble with non VRA codecs !! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL, VIA_ACLINK_CTRL_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) /* wait until codec ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) end_time = jiffies + msecs_to_jiffies(750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) pci_read_config_byte(chip->pci, VIA_ACLINK_STAT, &pval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) if (pval & VIA_ACLINK_C00_READY) /* primary codec ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) } while (time_before(jiffies, end_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) if ((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) "AC'97 codec is not ready [0x%x]\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) #if 0 /* FIXME: we don't support the second codec yet so skip the detection now.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) VIA_REG_AC97_SECONDARY_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) (VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) end_time = jiffies + msecs_to_jiffies(750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) VIA_REG_AC97_SECONDARY_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) (VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) if ((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_SECONDARY_VALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) chip->ac97_secondary = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) goto __ac97_ok2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) } while (time_before(jiffies, end_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) /* This is ok, the most of motherboards have only one codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) __ac97_ok2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) if (chip->chip_type == TYPE_VIA686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) /* route FM trap to IRQ, disable FM trap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) pci_write_config_byte(chip->pci, VIA_FM_NMI_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) /* disable all GPI interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) outl(0, VIAREG(chip, GPI_INTR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) if (chip->chip_type != TYPE_VIA686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) /* Workaround for Award BIOS bug:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) * DXS channels don't work properly with VRA if MC97 is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) pci = pci_get_device(0x1106, 0x3068, NULL); /* MC97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) if (pci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) unsigned char data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) pci_read_config_byte(pci, 0x44, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) pci_write_config_byte(pci, 0x44, data | 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) pci_dev_put(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) if (chip->chip_type != TYPE_VIA8233A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) int i, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) for (idx = 0; idx < 4; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) unsigned long port = chip->port + 0x10 * idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) chip->playback_volume[idx][i]=chip->playback_volume_c[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) outb(chip->playback_volume_c[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) port + VIA_REG_OFS_PLAYBACK_VOLUME_L + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) * power management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) static int snd_via82xx_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) struct via82xx *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) for (i = 0; i < chip->num_devs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) snd_via82xx_channel_reset(chip, &chip->devs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) snd_ac97_suspend(chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) /* save misc values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) if (chip->chip_type != TYPE_VIA686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) pci_read_config_byte(chip->pci, VIA8233_SPDIF_CTRL, &chip->spdif_ctrl_saved);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) chip->capture_src_saved[0] = inb(chip->port + VIA_REG_CAPTURE_CHANNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) chip->capture_src_saved[1] = inb(chip->port + VIA_REG_CAPTURE_CHANNEL + 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) static int snd_via82xx_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) struct via82xx *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) snd_via82xx_chip_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) if (chip->chip_type == TYPE_VIA686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) if (chip->mpu_port_saved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) pci_write_config_dword(chip->pci, 0x18, chip->mpu_port_saved | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE, chip->legacy_saved);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) pci_write_config_byte(chip->pci, VIA_PNP_CONTROL, chip->legacy_cfg_saved);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) pci_write_config_byte(chip->pci, VIA8233_SPDIF_CTRL, chip->spdif_ctrl_saved);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) outb(chip->capture_src_saved[0], chip->port + VIA_REG_CAPTURE_CHANNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) outb(chip->capture_src_saved[1], chip->port + VIA_REG_CAPTURE_CHANNEL + 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) snd_ac97_resume(chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) for (i = 0; i < chip->num_devs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) snd_via82xx_channel_reset(chip, &chip->devs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) static SIMPLE_DEV_PM_OPS(snd_via82xx_pm, snd_via82xx_suspend, snd_via82xx_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) #define SND_VIA82XX_PM_OPS &snd_via82xx_pm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) #define SND_VIA82XX_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) static int snd_via82xx_free(struct via82xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) if (chip->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) goto __end_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) for (i = 0; i < chip->num_devs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) snd_via82xx_channel_reset(chip, &chip->devs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) if (chip->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) free_irq(chip->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) __end_hw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) release_and_free_resource(chip->mpu_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) pci_release_regions(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) if (chip->chip_type == TYPE_VIA686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) snd_via686_free_gameport(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE, chip->old_legacy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) pci_write_config_byte(chip->pci, VIA_PNP_CONTROL, chip->old_legacy_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) pci_disable_device(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) static int snd_via82xx_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) struct via82xx *chip = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) return snd_via82xx_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) static int snd_via82xx_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) int chip_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) int revision,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) unsigned int ac97_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) struct via82xx **r_via)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) struct via82xx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .dev_free = snd_via82xx_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) if ((err = pci_enable_device(pci)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) if ((chip = kzalloc(sizeof(*chip), GFP_KERNEL)) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) chip->chip_type = chip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) chip->revision = revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) spin_lock_init(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) spin_lock_init(&chip->rates[0].lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) spin_lock_init(&chip->rates[1].lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) chip->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) chip->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) chip->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) pci_read_config_byte(pci, VIA_FUNC_ENABLE, &chip->old_legacy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) pci_read_config_byte(pci, VIA_PNP_CONTROL, &chip->old_legacy_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) chip->old_legacy & ~(VIA_FUNC_ENABLE_SB|VIA_FUNC_ENABLE_FM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) if ((err = pci_request_regions(pci, card->driver)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) chip->port = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) if (request_irq(pci->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) chip_type == TYPE_VIA8233 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) snd_via8233_interrupt : snd_via686_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) KBUILD_MODNAME, chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) snd_via82xx_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) chip->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) card->sync_irq = chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) if (ac97_clock >= 8000 && ac97_clock <= 48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) chip->ac97_clock = ac97_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) if ((err = snd_via82xx_chip_init(chip)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) snd_via82xx_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) snd_via82xx_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) /* The 8233 ac97 controller does not implement the master bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) * in the pci command register. IMHO this is a violation of the PCI spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) * We call pci_set_master here because it does not hurt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) *r_via = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) struct via823x_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) int revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) static const struct via823x_info via823x_cards[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) { VIA_REV_PRE_8233, "VIA 8233-Pre", TYPE_VIA8233 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) { VIA_REV_8233C, "VIA 8233C", TYPE_VIA8233 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) { VIA_REV_8233, "VIA 8233", TYPE_VIA8233 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) { VIA_REV_8233A, "VIA 8233A", TYPE_VIA8233A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) { VIA_REV_8235, "VIA 8235", TYPE_VIA8233 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) { VIA_REV_8237, "VIA 8237", TYPE_VIA8233 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) { VIA_REV_8251, "VIA 8251", TYPE_VIA8233 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) * auto detection of DXS channel supports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) static const struct snd_pci_quirk dxs_allowlist[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) SND_PCI_QUIRK(0x1005, 0x4710, "Avance Logic Mobo", VIA_DXS_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) SND_PCI_QUIRK(0x1019, 0x0996, "ESC Mobo", VIA_DXS_48K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) SND_PCI_QUIRK(0x1019, 0x0a81, "ECS K7VTA3 v8.0", VIA_DXS_NO_VRA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) SND_PCI_QUIRK(0x1019, 0x0a85, "ECS L7VMM2", VIA_DXS_NO_VRA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) SND_PCI_QUIRK_VENDOR(0x1019, "ESC K8", VIA_DXS_SRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) SND_PCI_QUIRK(0x1019, 0xaa01, "ESC K8T890-A", VIA_DXS_SRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) SND_PCI_QUIRK(0x1025, 0x0033, "Acer Inspire 1353LM", VIA_DXS_NO_VRA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) SND_PCI_QUIRK(0x1025, 0x0046, "Acer Aspire 1524 WLMi", VIA_DXS_SRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) SND_PCI_QUIRK_VENDOR(0x1043, "ASUS A7/A8", VIA_DXS_NO_VRA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) SND_PCI_QUIRK_VENDOR(0x1071, "Diverse Notebook", VIA_DXS_NO_VRA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) SND_PCI_QUIRK(0x10cf, 0x118e, "FSC Laptop", VIA_DXS_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) SND_PCI_QUIRK_VENDOR(0x1106, "ASRock", VIA_DXS_SRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) SND_PCI_QUIRK(0x1297, 0xa231, "Shuttle AK31v2", VIA_DXS_SRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) SND_PCI_QUIRK(0x1297, 0xa232, "Shuttle", VIA_DXS_SRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) SND_PCI_QUIRK(0x1297, 0xc160, "Shuttle Sk41G", VIA_DXS_SRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte GA-7VAXP", VIA_DXS_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) SND_PCI_QUIRK(0x1462, 0x3800, "MSI KT266", VIA_DXS_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) SND_PCI_QUIRK(0x1462, 0x7120, "MSI KT4V", VIA_DXS_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) SND_PCI_QUIRK(0x1462, 0x7142, "MSI K8MM-V", VIA_DXS_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) SND_PCI_QUIRK_VENDOR(0x1462, "MSI Mobo", VIA_DXS_SRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) SND_PCI_QUIRK(0x147b, 0x1401, "ABIT KD7(-RAID)", VIA_DXS_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) SND_PCI_QUIRK(0x147b, 0x1411, "ABIT VA-20", VIA_DXS_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) SND_PCI_QUIRK(0x147b, 0x1413, "ABIT KV8 Pro", VIA_DXS_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) SND_PCI_QUIRK(0x147b, 0x1415, "ABIT AV8", VIA_DXS_NO_VRA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) SND_PCI_QUIRK(0x14ff, 0x0403, "Twinhead mobo", VIA_DXS_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) SND_PCI_QUIRK(0x14ff, 0x0408, "Twinhead laptop", VIA_DXS_SRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) SND_PCI_QUIRK(0x1558, 0x4701, "Clevo D470", VIA_DXS_SRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) SND_PCI_QUIRK(0x1584, 0x8120, "Diverse Laptop", VIA_DXS_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) SND_PCI_QUIRK(0x1584, 0x8123, "Targa/Uniwill", VIA_DXS_NO_VRA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) SND_PCI_QUIRK(0x161f, 0x202b, "Amira Notebook", VIA_DXS_NO_VRA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) SND_PCI_QUIRK(0x161f, 0x2032, "m680x machines", VIA_DXS_48K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) SND_PCI_QUIRK(0x1631, 0xe004, "PB EasyNote 3174", VIA_DXS_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) SND_PCI_QUIRK(0x1695, 0x3005, "EPoX EP-8K9A", VIA_DXS_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) SND_PCI_QUIRK_VENDOR(0x1695, "EPoX mobo", VIA_DXS_SRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) SND_PCI_QUIRK_VENDOR(0x16f3, "Jetway K8", VIA_DXS_SRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) SND_PCI_QUIRK_VENDOR(0x1734, "FSC Laptop", VIA_DXS_SRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) SND_PCI_QUIRK(0x1849, 0x3059, "ASRock K7VM2", VIA_DXS_NO_VRA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) SND_PCI_QUIRK_VENDOR(0x1849, "ASRock mobo", VIA_DXS_SRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) SND_PCI_QUIRK(0x1919, 0x200a, "Soltek SL-K8", VIA_DXS_NO_VRA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) SND_PCI_QUIRK(0x4005, 0x4710, "MSI K7T266", VIA_DXS_SRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) { } /* terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) static int check_dxs_list(struct pci_dev *pci, int revision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) const struct snd_pci_quirk *w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) w = snd_pci_quirk_lookup(pci, dxs_allowlist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) if (w) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) dev_dbg(&pci->dev, "DXS allow list for %s found\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) snd_pci_quirk_name(w));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) return w->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) /* for newer revision, default to DXS_SRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) if (revision >= VIA_REV_8235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) return VIA_DXS_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) * not detected, try 48k rate only to be sure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) dev_info(&pci->dev, "Assuming DXS channels with 48k fixed sample rate.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) dev_info(&pci->dev, " Please try dxs_support=5 option\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) dev_info(&pci->dev, " and report if it works on your machine.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) dev_info(&pci->dev, " For more details, read ALSA-Configuration.txt.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) return VIA_DXS_48K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) static int snd_via82xx_probe(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) struct via82xx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) int chip_type = 0, card_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) card_type = pci_id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) switch (card_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) case TYPE_CARD_VIA686:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) strcpy(card->driver, "VIA686A");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) sprintf(card->shortname, "VIA 82C686A/B rev%x", pci->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) chip_type = TYPE_VIA686;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) case TYPE_CARD_VIA8233:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) chip_type = TYPE_VIA8233;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) sprintf(card->shortname, "VIA 823x rev%x", pci->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) for (i = 0; i < ARRAY_SIZE(via823x_cards); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) if (pci->revision == via823x_cards[i].revision) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) chip_type = via823x_cards[i].type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) strcpy(card->shortname, via823x_cards[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) if (chip_type != TYPE_VIA8233A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) if (dxs_support == VIA_DXS_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) dxs_support = check_dxs_list(pci, pci->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) /* force to use VIA8233 or 8233A model according to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) * dxs_support module option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) if (dxs_support == VIA_DXS_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) chip_type = TYPE_VIA8233A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) chip_type = TYPE_VIA8233;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) if (chip_type == TYPE_VIA8233A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) strcpy(card->driver, "VIA8233A");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) else if (pci->revision >= VIA_REV_8237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) strcpy(card->driver, "VIA8237"); /* no slog assignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) strcpy(card->driver, "VIA8233");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) dev_err(card->dev, "invalid card type %d\n", card_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) if ((err = snd_via82xx_create(card, pci, chip_type, pci->revision,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) ac97_clock, &chip)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) card->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) if ((err = snd_via82xx_mixer_new(chip, ac97_quirk)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) if (chip_type == TYPE_VIA686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) if ((err = snd_via686_pcm_new(chip)) < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) (err = snd_via686_init_misc(chip)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) if (chip_type == TYPE_VIA8233A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) if ((err = snd_via8233a_pcm_new(chip)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) // chip->dxs_fixed = 1; /* FIXME: use 48k for DXS #3? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) if ((err = snd_via8233_pcm_new(chip)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) if (dxs_support == VIA_DXS_48K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) chip->dxs_fixed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) else if (dxs_support == VIA_DXS_NO_VRA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) chip->no_vra = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) else if (dxs_support == VIA_DXS_SRC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) chip->no_vra = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) chip->dxs_src = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) if ((err = snd_via8233_init_misc(chip)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) for (i = 0; i < chip->num_devs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) snd_via82xx_channel_reset(chip, &chip->devs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) snprintf(card->longname, sizeof(card->longname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) "%s with %s at %#lx, irq %d", card->shortname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) snd_ac97_get_short_name(chip->ac97), chip->port, chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) snd_via82xx_proc_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) if ((err = snd_card_register(card)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) __error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) static void snd_via82xx_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) snd_card_free(pci_get_drvdata(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) static struct pci_driver via82xx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) .id_table = snd_via82xx_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) .probe = snd_via82xx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .remove = snd_via82xx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) .pm = SND_VIA82XX_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) module_pci_driver(via82xx_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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