^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __SOUND_TRIDENT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __SOUND_TRIDENT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * audio@tridentmicro.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Fri Feb 19 15:55:28 MST 1999
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Definitions for Trident 4DWave DX/NX chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/mpu401.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/util_mem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TRIDENT_DEVICE_ID_DX ((PCI_VENDOR_ID_TRIDENT<<16)|PCI_DEVICE_ID_TRIDENT_4DWAVE_DX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TRIDENT_DEVICE_ID_NX ((PCI_VENDOR_ID_TRIDENT<<16)|PCI_DEVICE_ID_TRIDENT_4DWAVE_NX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TRIDENT_DEVICE_ID_SI7018 ((PCI_VENDOR_ID_SI<<16)|PCI_DEVICE_ID_SI_7018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SNDRV_TRIDENT_VOICE_TYPE_PCM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SNDRV_TRIDENT_VOICE_TYPE_SYNTH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SNDRV_TRIDENT_VOICE_TYPE_MIDI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SNDRV_TRIDENT_VFLG_RUNNING (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* TLB code constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SNDRV_TRIDENT_PAGE_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SNDRV_TRIDENT_PAGE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SNDRV_TRIDENT_PAGE_MASK ((1<<SNDRV_TRIDENT_PAGE_SHIFT)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SNDRV_TRIDENT_MAX_PAGES 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Direct registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TRID_REG(trident, x) ((trident)->port + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ID_4DWAVE_DX 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ID_4DWAVE_NX 0x2001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Bank definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define T4D_BANK_A 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define T4D_BANK_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define T4D_NUM_BANKS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Global registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) enum global_control_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) CHANNEL_IDX = 0x0000003f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) OVERRUN_IE = 0x00000400, /* interrupt enable: capture overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) UNDERRUN_IE = 0x00000800, /* interrupt enable: playback underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ENDLP_IE = 0x00001000, /* interrupt enable: end of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MIDLP_IE = 0x00002000, /* interrupt enable: middle buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ETOG_IE = 0x00004000, /* interrupt enable: envelope toggling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) EDROP_IE = 0x00008000, /* interrupt enable: envelope drop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) BANK_B_EN = 0x00010000, /* SiS: enable bank B (64 channels) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PCMIN_B_MIX = 0x00020000, /* SiS: PCM IN B mixing enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) I2S_OUT_ASSIGN = 0x00040000, /* SiS: I2S Out contains surround PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) SPDIF_OUT_ASSIGN= 0x00080000, /* SiS: 0=S/PDIF L/R | 1=PCM Out FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MAIN_OUT_ASSIGN = 0x00100000, /* SiS: 0=PCM Out FIFO | 1=MMC Out buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) enum miscint_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PB_UNDERRUN_IRQ = 0x00000001, REC_OVERRUN_IRQ = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) SB_IRQ = 0x00000004, MPU401_IRQ = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) OPL3_IRQ = 0x00000010, ADDRESS_IRQ = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ENVELOPE_IRQ = 0x00000040, PB_UNDERRUN = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) REC_OVERRUN = 0x00000200, MIXER_UNDERFLOW = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MIXER_OVERFLOW = 0x00000800, NX_SB_IRQ_DISABLE = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ST_TARGET_REACHED = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PB_24K_MODE = 0x00010000, ST_IRQ_EN = 0x00800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ACGPIO_IRQ = 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* T2 legacy dma control registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define LEGACY_DMAR0 0x00 // ADR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LEGACY_DMAR4 0x04 // CNT0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define LEGACY_DMAR6 0x06 // CNT0 - High bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LEGACY_DMAR11 0x0b // MOD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define LEGACY_DMAR15 0x0f // MMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define T4D_START_A 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define T4D_STOP_A 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define T4D_DLY_A 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define T4D_SIGN_CSO_A 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define T4D_CSPF_A 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define T4D_CSPF_B 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define T4D_CEBC_A 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define T4D_AINT_A 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define T4D_AINTEN_A 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define T4D_LFO_GC_CIR 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define T4D_MUSICVOL_WAVEVOL 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define T4D_SBDELTA_DELTA_R 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define T4D_MISCINT 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define T4D_START_B 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define T4D_STOP_B 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define T4D_SBBL_SBCL 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define T4D_SBCTRL_SBE2R_SBDD 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define T4D_STIMER 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define T4D_AINT_B 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define T4D_AINTEN_B 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define T4D_RCI 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* MPU-401 UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define T4D_MPU401_BASE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define T4D_MPUR0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define T4D_MPUR1 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define T4D_MPUR2 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define T4D_MPUR3 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* S/PDIF Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define NX_SPCTRL_SPCSO 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define NX_SPLBA 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define NX_SPESO 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define NX_SPCSTATUS 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Joystick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GAMEPORT_GCR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GAMEPORT_MODE_ADC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GAMEPORT_LEGACY 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GAMEPORT_AXES 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* NX Specific Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define NX_TLBC 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Channel Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CH_START 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CH_DX_CSO_ALPHA_FMS 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CH_DX_ESO_DELTA 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CH_DX_FMC_RVOL_CVOL 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CH_NX_DELTA_CSO 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CH_NX_DELTA_ESO 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CH_NX_ALPHA_FMS_FMC_RVOL_CVOL 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CH_LBA 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CH_GVSEL_PAN_VOL_CTRL_EC 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CH_EBUF1 0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CH_EBUF2 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* AC-97 Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DX_ACR0_AC97_W 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DX_ACR1_AC97_R 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DX_ACR2_AC97_COM_STAT 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define NX_ACR0_AC97_COM_STAT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define NX_ACR1_AC97_W 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define NX_ACR2_AC97_R_PRIMARY 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define NX_ACR3_AC97_R_SECONDARY 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SI_AC97_WRITE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SI_AC97_READ 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SI_SERIAL_INTF_CTRL 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SI_AC97_GPIO 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SI_ASR0 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SI_SPDIF_CS 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SI_GPIO 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) enum trident_nx_ac97_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* ACR1-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) NX_AC97_BUSY_WRITE = 0x0800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) NX_AC97_BUSY_READ = 0x0800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) NX_AC97_BUSY_DATA = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) NX_AC97_WRITE_SECONDARY = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* ACR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) NX_AC97_SECONDARY_READY = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) NX_AC97_SECONDARY_RECORD = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) NX_AC97_SURROUND_OUTPUT = 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) NX_AC97_PRIMARY_READY = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) NX_AC97_PRIMARY_RECORD = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) NX_AC97_PCM_OUTPUT = 0x0002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) NX_AC97_WARM_RESET = 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) enum trident_dx_ac97_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) DX_AC97_BUSY_WRITE = 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) DX_AC97_BUSY_READ = 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) DX_AC97_READY = 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) DX_AC97_RECORD = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) DX_AC97_PLAYBACK = 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) enum sis7018_ac97_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) SI_AC97_BUSY_WRITE = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) SI_AC97_AUDIO_BUSY = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) SI_AC97_MODEM_BUSY = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) SI_AC97_BUSY_READ = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) SI_AC97_SECONDARY = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) enum serial_intf_ctrl_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) WARM_RESET = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) COLD_RESET = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) I2S_CLOCK = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PCM_SEC_AC97 = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) AC97_DBL_RATE = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) SPDIF_EN = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) I2S_OUTPUT_EN = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) I2S_INPUT_EN = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PCMIN = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) LINE1IN = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MICIN = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) LINE2IN = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) HEAD_SET_IN = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) GPIOIN = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* 7018 spec says id = 01 but the demo board routed to 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) SECONDARY_ID= 0x00004000, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) SECONDARY_ID = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PCMOUT = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) SURROUT = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) CENTEROUT = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) LFEOUT = 0x00080000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) LINE1OUT = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) LINE2OUT = 0x00200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) GPIOOUT = 0x00400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) SI_AC97_PRIMARY_READY = 0x01000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) SI_AC97_SECONDARY_READY = 0x02000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) SI_AC97_POWERDOWN = 0x04000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* PCM defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define T4D_DEFAULT_PCM_VOL 10 /* 0 - 255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define T4D_DEFAULT_PCM_PAN 0 /* 0 - 127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define T4D_DEFAULT_PCM_RVOL 127 /* 0 - 127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define T4D_DEFAULT_PCM_CVOL 127 /* 0 - 127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct snd_trident;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct snd_trident_voice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct snd_trident_pcm_mixer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct snd_trident_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct snd_midi_channel_set * chset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct snd_trident * trident;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int mode; /* operation mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int client; /* sequencer client number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int port; /* sequencer port number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned int midi_has_voices: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct snd_trident_memblk_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) short first_page, last_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct snd_trident_tlb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) __le32 *entries; /* 16k-aligned TLB table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dma_addr_t entries_dmaaddr; /* 16k-aligned PCI address to TLB table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned long * shadow_entries; /* shadow entries with virtual addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct snd_dma_buffer buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct snd_util_memhdr * memhdr; /* page allocation list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct snd_dma_buffer silent_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct snd_trident_voice {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned int number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int use: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pcm: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) synth:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) midi: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned char client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned char port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned char index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct snd_trident_sample_ops *sample_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* channel parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int CSO; /* 24 bits (16 on DX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int ESO; /* 24 bits (16 on DX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned int LBA; /* 30 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned short EC; /* 12 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned short Alpha; /* 12 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned short Delta; /* 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned short Attribute; /* 16 bits - SiS 7018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned short Vol; /* 12 bits (6.6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned char Pan; /* 7 bits (1.4.2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned char GVSel; /* 1 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned char RVol; /* 7 bits (5.2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned char CVol; /* 7 bits (5.2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned char FMC; /* 2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned char CTRL; /* 4 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned char FMS; /* 4 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned char LFO; /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned int negCSO; /* nonzero - use negative CSO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct snd_util_memblk *memblk; /* memory block if TLB enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* PCM data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct snd_trident *trident;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct snd_trident_voice *extra; /* extra PCM voice (acts as interrupt generator) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int running: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) capture: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) spdif: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) foldback: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) isync: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) isync2: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) isync3: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int foldback_chan; /* foldback subdevice number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned int stimer; /* global sample timer (to detect spurious interrupts) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned int spurious_threshold; /* spurious threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned int isync_mark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned int isync_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned int isync_ESO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) void *private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) void (*private_free)(struct snd_trident_voice *voice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct snd_4dwave {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int seq_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct snd_trident_port seq_ports[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct snd_trident_voice voices[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int ChanSynthCount; /* number of allocated synth channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int max_size; /* maximum synth memory size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int current_size; /* current allocated synth mem in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct snd_trident_pcm_mixer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct snd_trident_voice *voice; /* active voice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned short vol; /* front volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned char pan; /* pan control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned char rvol; /* rear volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned char cvol; /* center volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned char pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct snd_trident {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned int device; /* device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned char bDMAStart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned long port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned long midi_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned int spurious_irq_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned int spurious_irq_max_delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct snd_trident_tlb tlb; /* TLB entries for NX cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned char spdif_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned char spdif_pcm_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned int spdif_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned int spdif_pcm_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct snd_kcontrol *spdif_pcm_ctl; /* S/PDIF settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned int ac97_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned int ChanMap[2]; /* allocation map for hardware channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int ChanPCM; /* max number of PCM channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int ChanPCMcnt; /* actual number of PCM channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned int ac97_detect: 1; /* 1 = AC97 in detection phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned int in_suspend: 1; /* 1 during suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct snd_4dwave synth; /* synth specific variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) spinlock_t event_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) spinlock_t voice_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct snd_dma_device dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct snd_pcm *pcm; /* ADC/DAC PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct snd_pcm *foldback; /* Foldback PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct snd_pcm *spdif; /* SPDIF PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct snd_rawmidi *rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct snd_ac97_bus *ac97_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct snd_ac97 *ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct snd_ac97 *ac97_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned int musicvol_wavevol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct snd_trident_pcm_mixer pcm_mixer[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct snd_kcontrol *ctl_vol; /* front volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct snd_kcontrol *ctl_pan; /* pan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct snd_kcontrol *ctl_rvol; /* rear volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct snd_kcontrol *ctl_cvol; /* center volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct gameport *gameport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int snd_trident_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int pcm_streams,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int pcm_spdif_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int max_wavetable_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct snd_trident ** rtrident);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int snd_trident_create_gameport(struct snd_trident *trident);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int snd_trident_pcm(struct snd_trident *trident, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int snd_trident_foldback_pcm(struct snd_trident *trident, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int snd_trident_spdif_pcm(struct snd_trident *trident, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int snd_trident_attach_synthesizer(struct snd_trident * trident);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct snd_trident_voice *snd_trident_alloc_voice(struct snd_trident * trident, int type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int client, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) void snd_trident_free_voice(struct snd_trident * trident, struct snd_trident_voice *voice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) void snd_trident_start_voice(struct snd_trident * trident, unsigned int voice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) void snd_trident_stop_voice(struct snd_trident * trident, unsigned int voice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) void snd_trident_write_voice_regs(struct snd_trident * trident, struct snd_trident_voice *voice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) extern const struct dev_pm_ops snd_trident_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* TLB memory allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct snd_util_memblk *snd_trident_alloc_pages(struct snd_trident *trident,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct snd_pcm_substream *substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int snd_trident_free_pages(struct snd_trident *trident, struct snd_util_memblk *blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct snd_util_memblk *snd_trident_synth_alloc(struct snd_trident *trident, unsigned int size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int snd_trident_synth_free(struct snd_trident *trident, struct snd_util_memblk *blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int snd_trident_synth_copy_from_user(struct snd_trident *trident, struct snd_util_memblk *blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int offset, const char __user *data, int size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #endif /* __SOUND_TRIDENT_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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