Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef __sis7019_h__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define __sis7019_h__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Definitions for SiS7019 Audio Accelerator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  Copyright (C) 2004-2007, David Dillow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  Written by David Dillow <dave@thedillows.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *  Inspired by the Trident 4D-WaveDX/NX driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /* General Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define SIS_GCR		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define		SIS_GCR_MACRO_POWER_DOWN		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define		SIS_GCR_MODEM_ENABLE			0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define		SIS_GCR_SOFTWARE_RESET			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* General Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SIS_GIER	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define		SIS_GIER_MODEM_TIMER_IRQ_ENABLE		0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define		SIS_GIER_MODEM_RX_DMA_IRQ_ENABLE	0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define		SIS_GIER_MODEM_TX_DMA_IRQ_ENABLE	0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define		SIS_GIER_AC97_GPIO1_IRQ_ENABLE		0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define		SIS_GIER_AC97_GPIO0_IRQ_ENABLE		0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define		SIS_GIER_AC97_SAMPLE_TIMER_IRQ_ENABLE	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define		SIS_GIER_AUDIO_GLOBAL_TIMER_IRQ_ENABLE	0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define		SIS_GIER_AUDIO_RECORD_DMA_IRQ_ENABLE	0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define		SIS_GIER_AUDIO_PLAY_DMA_IRQ_ENABLE	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define		SIS_GIER_AUDIO_WAVE_ENGINE_IRQ_ENABLE	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* General Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SIS_GISR	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define		SIS_GISR_MODEM_TIMER_IRQ_STATUS		0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define		SIS_GISR_MODEM_RX_DMA_IRQ_STATUS	0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define		SIS_GISR_MODEM_TX_DMA_IRQ_STATUS	0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define		SIS_GISR_AC97_GPIO1_IRQ_STATUS		0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define		SIS_GISR_AC97_GPIO0_IRQ_STATUS		0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define		SIS_GISR_AC97_SAMPLE_TIMER_IRQ_STATUS	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define		SIS_GISR_AUDIO_GLOBAL_TIMER_IRQ_STATUS	0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define		SIS_GISR_AUDIO_RECORD_DMA_IRQ_STATUS	0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define		SIS_GISR_AUDIO_PLAY_DMA_IRQ_STATUS	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define		SIS_GISR_AUDIO_WAVE_ENGINE_IRQ_STATUS	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* DMA Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SIS_DMA_CSR	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define		SIS_DMA_CSR_PCI_SETTINGS		0x0000001d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define		SIS_DMA_CSR_CONCURRENT_ENABLE		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define		SIS_DMA_CSR_PIPELINE_ENABLE		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define		SIS_DMA_CSR_RX_DRAIN_ENABLE		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define		SIS_DMA_CSR_RX_FILL_ENABLE		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define		SIS_DMA_CSR_TX_DRAIN_ENABLE		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define		SIS_DMA_CSR_TX_LOWPRI_FILL_ENABLE	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define		SIS_DMA_CSR_TX_HIPRI_FILL_ENABLE	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* Playback Channel Start Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SIS_PLAY_START_A_REG	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define SIS_PLAY_START_B_REG	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* Playback Channel Stop Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SIS_PLAY_STOP_A_REG	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define SIS_PLAY_STOP_B_REG	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* Recording Channel Start Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define SIS_RECORD_START_REG	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /* Recording Channel Stop Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define SIS_RECORD_STOP_REG	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* Playback Interrupt Status Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define SIS_PISR_A	0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define SIS_PISR_B	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /* Recording Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define SIS_RISR	0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) /* AC97 AC-link Playback Source Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define SIS_AC97_PSR	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define		SIS_AC97_PSR_MODEM_HEADSET_SRC_MIXER	0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define		SIS_AC97_PSR_MODEM_LINE2_SRC_MIXER	0x00f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define		SIS_AC97_PSR_MODEM_LINE1_SRC_MIXER	0x000f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define		SIS_AC97_PSR_PCM_LFR_SRC_MIXER		0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define		SIS_AC97_PSR_PCM_SURROUND_SRC_MIXER	0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define		SIS_AC97_PSR_PCM_CENTER_SRC_MIXER	0x000000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define		SIS_AC97_PSR_PCM_LR_SRC_MIXER		0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) /* AC97 AC-link Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define SIS_AC97_CMD	0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define 	SIS_AC97_CMD_DATA_MASK			0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define		SIS_AC97_CMD_REG_MASK			0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define		SIS_AC97_CMD_CODEC3_READ		0x0000000d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define		SIS_AC97_CMD_CODEC3_WRITE		0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define		SIS_AC97_CMD_CODEC2_READ		0x0000000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define		SIS_AC97_CMD_CODEC2_WRITE		0x0000000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define		SIS_AC97_CMD_CODEC_READ			0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define		SIS_AC97_CMD_CODEC_WRITE		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define		SIS_AC97_CMD_CODEC_WARM_RESET		0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define		SIS_AC97_CMD_CODEC_COLD_RESET		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define		SIS_AC97_CMD_DONE			0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* AC97 AC-link Semaphore Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SIS_AC97_SEMA	0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define		SIS_AC97_SEMA_BUSY			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define		SIS_AC97_SEMA_RELEASE			0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* AC97 AC-link Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SIS_AC97_STATUS	0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define		SIS_AC97_STATUS_AUDIO_D2_INACT_SECS	0x03f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define		SIS_AC97_STATUS_MODEM_ALIVE		0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define		SIS_AC97_STATUS_AUDIO_ALIVE		0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define		SIS_AC97_STATUS_CODEC3_READY		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define		SIS_AC97_STATUS_CODEC2_READY		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define		SIS_AC97_STATUS_CODEC_READY		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define		SIS_AC97_STATUS_WARM_RESET		0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define		SIS_AC97_STATUS_COLD_RESET		0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define		SIS_AC97_STATUS_POWERED_DOWN		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define		SIS_AC97_STATUS_NORMAL			0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define		SIS_AC97_STATUS_READ_EXPIRED		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define		SIS_AC97_STATUS_SEMAPHORE		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define		SIS_AC97_STATUS_BUSY			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* AC97 AC-link Audio Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SIS_AC97_CONF	0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define		SIS_AC97_CONF_AUDIO_ALIVE		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define		SIS_AC97_CONF_WARM_RESET_ENABLE		0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define		SIS_AC97_CONF_PR6_ENABLE		0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define		SIS_AC97_CONF_PR5_ENABLE		0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define		SIS_AC97_CONF_PR4_ENABLE		0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define		SIS_AC97_CONF_PR3_ENABLE		0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define		SIS_AC97_CONF_PR2_PR7_ENABLE		0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define		SIS_AC97_CONF_PR0_PR1_ENABLE		0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define		SIS_AC97_CONF_AUTO_PM_ENABLE		0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define		SIS_AC97_CONF_PCM_LFE_ENABLE		0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define		SIS_AC97_CONF_PCM_SURROUND_ENABLE	0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define		SIS_AC97_CONF_PCM_CENTER_ENABLE		0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define		SIS_AC97_CONF_PCM_LR_ENABLE		0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define		SIS_AC97_CONF_PCM_CAP_MIC_ENABLE	0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define		SIS_AC97_CONF_PCM_CAP_LR_ENABLE		0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define		SIS_AC97_CONF_PCM_CAP_MIC_FROM_CODEC3	0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define		SIS_AC97_CONF_PCM_CAP_LR_FROM_CODEC3	0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define		SIS_AC97_CONF_CODEC3_PM_VRM		0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define		SIS_AC97_CONF_CODEC_PM_VRM		0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define		SIS_AC97_CONF_CODEC3_VRA_ENABLE		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define		SIS_AC97_CONF_CODEC_VRA_ENABLE		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define		SIS_AC97_CONF_CODEC3_PM_EAC		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define		SIS_AC97_CONF_CODEC_PM_EAC		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define		SIS_AC97_CONF_CODEC3_EXISTS		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define		SIS_AC97_CONF_CODEC_EXISTS		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Playback Channel Sync Group registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SIS_PLAY_SYNC_GROUP_A	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SIS_PLAY_SYNC_GROUP_B	0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SIS_PLAY_SYNC_GROUP_C	0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SIS_PLAY_SYNC_GROUP_D	0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SIS_MIXER_SYNC_GROUP	0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Wave Engine Config and Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SIS_WECCR	0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define		SIS_WECCR_TESTMODE_MASK			0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define			SIS_WECCR_TESTMODE_NORMAL		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define			SIS_WECCR_TESTMODE_BYPASS_NSO_ALPHA	0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define			SIS_WECCR_TESTMODE_BYPASS_FC		0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define			SIS_WECCR_TESTMODE_BYPASS_WOL		0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define		SIS_WECCR_RESONANCE_DELAY_MASK		0x00060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define			SIS_WECCR_RESONANCE_DELAY_NONE		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define			SIS_WECCR_RESONANCE_DELAY_FC_1F00	0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define			SIS_WECCR_RESONANCE_DELAY_FC_1E00	0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define			SIS_WECCR_RESONANCE_DELAY_FC_1C00	0x00060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define		SIS_WECCR_IGNORE_CHANNEL_PARMS		0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define		SIS_WECCR_COMMAND_CHANNEL_ID_MASK	0x0003ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define		SIS_WECCR_COMMAND_MASK			0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define			SIS_WECCR_COMMAND_NONE			0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define			SIS_WECCR_COMMAND_DONE			0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define			SIS_WECCR_COMMAND_PAUSE			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define			SIS_WECCR_COMMAND_TOGGLE_VEG		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define			SIS_WECCR_COMMAND_TOGGLE_MEG		0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define			SIS_WECCR_COMMAND_TOGGLE_VEG_MEG	0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Wave Engine Volume Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SIS_WEVCR	0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define		SIS_WEVCR_LEFT_MUSIC_ATTENUATION_MASK	0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define		SIS_WEVCR_RIGHT_MUSIC_ATTENUATION_MASK	0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define		SIS_WEVCR_LEFT_WAVE_ATTENUATION_MASK	0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define		SIS_WEVCR_RIGHT_WAVE_ATTENUATION_MASK	0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Wave Engine Interrupt Status Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SIS_WEISR_A	0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SIS_WEISR_B	0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Playback DMA parameters (parameter RAM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SIS_PLAY_DMA_OFFSET	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SIS_PLAY_DMA_SIZE	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SIS_PLAY_DMA_ADDR(addr, num) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	((num * SIS_PLAY_DMA_SIZE) + (addr) + SIS_PLAY_DMA_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SIS_PLAY_DMA_FORMAT_CSO	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define		SIS_PLAY_DMA_FORMAT_UNSIGNED	0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define		SIS_PLAY_DMA_FORMAT_8BIT	0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define		SIS_PLAY_DMA_FORMAT_MONO	0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define		SIS_PLAY_DMA_CSO_MASK		0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SIS_PLAY_DMA_BASE	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SIS_PLAY_DMA_CONTROL	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define		SIS_PLAY_DMA_STOP_AT_SSO	0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define		SIS_PLAY_DMA_RELEASE		0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define		SIS_PLAY_DMA_LOOP		0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define		SIS_PLAY_DMA_INTR_AT_SSO	0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define		SIS_PLAY_DMA_INTR_AT_ESO	0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define		SIS_PLAY_DMA_INTR_AT_LEO	0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define		SIS_PLAY_DMA_INTR_AT_MLP	0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define		SIS_PLAY_DMA_LEO_MASK		0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SIS_PLAY_DMA_SSO_ESO	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define		SIS_PLAY_DMA_SSO_MASK		0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define		SIS_PLAY_DMA_ESO_MASK		0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Capture DMA parameters (parameter RAM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SIS_CAPTURE_DMA_OFFSET	0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SIS_CAPTURE_DMA_SIZE	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SIS_CAPTURE_DMA_ADDR(addr, num) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	((num * SIS_CAPTURE_DMA_SIZE) + (addr) + SIS_CAPTURE_DMA_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define	SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_0	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define	SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_1	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define	SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_2	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define	SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_3	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define	SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_4	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define	SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_5	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define	SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_6	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define	SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_7	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define	SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_8	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define	SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_9	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define	SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_10	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define	SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_11	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define	SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_12	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define	SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_13	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define	SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_14	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define	SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_15	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define	SIS_CAPTURE_CHAN_AC97_PCM_IN		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define	SIS_CAPTURE_CHAN_AC97_MIC_IN		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define	SIS_CAPTURE_CHAN_AC97_LINE1_IN		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define	SIS_CAPTURE_CHAN_AC97_LINE2_IN		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define	SIS_CAPTURE_CHAN_AC97_HANDSE_IN		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SIS_CAPTURE_DMA_FORMAT_CSO	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define		SIS_CAPTURE_DMA_MONO_MODE_MASK	0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define		SIS_CAPTURE_DMA_MONO_MODE_AVG	0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define		SIS_CAPTURE_DMA_MONO_MODE_LEFT	0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define		SIS_CAPTURE_DMA_MONO_MODE_RIGHT	0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define		SIS_CAPTURE_DMA_FORMAT_UNSIGNED	0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define		SIS_CAPTURE_DMA_FORMAT_8BIT	0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define		SIS_CAPTURE_DMA_FORMAT_MONO	0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define		SIS_CAPTURE_DMA_CSO_MASK		0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SIS_CAPTURE_DMA_BASE		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SIS_CAPTURE_DMA_CONTROL		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define		SIS_CAPTURE_DMA_STOP_AT_SSO	0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define		SIS_CAPTURE_DMA_RELEASE		0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define		SIS_CAPTURE_DMA_LOOP		0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define		SIS_CAPTURE_DMA_INTR_AT_LEO	0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define		SIS_CAPTURE_DMA_INTR_AT_MLP	0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define		SIS_CAPTURE_DMA_LEO_MASK		0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SIS_CAPTURE_DMA_RESERVED	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Mixer routing list start pointer (parameter RAM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SIS_MIXER_START_OFFSET	0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SIS_MIXER_START_SIZE	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SIS_MIXER_START_ADDR(addr, num) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	((num * SIS_MIXER_START_SIZE) + (addr) + SIS_MIXER_START_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SIS_MIXER_START_MASK	0x0000007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Mixer routing table (parameter RAM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SIS_MIXER_OFFSET	0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SIS_MIXER_SIZE		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SIS_MIXER_ADDR(addr, num) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	((num * SIS_MIXER_SIZE) + (addr) + SIS_MIXER_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SIS_MIXER_RIGHT_ATTENUTATION_MASK	0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define 	SIS_MIXER_RIGHT_NO_ATTEN		0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SIS_MIXER_LEFT_ATTENUTATION_MASK	0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define 	SIS_MIXER_LEFT_NO_ATTEN			0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SIS_MIXER_NEXT_ENTRY_MASK		0x00007f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define 	SIS_MIXER_NEXT_ENTRY_NONE		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SIS_MIXER_DEST_MASK			0x0000007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define 	SIS_MIXER_DEST_0			0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define 	SIS_MIXER_DEST_1			0x00000021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define 	SIS_MIXER_DEST_2			0x00000022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define 	SIS_MIXER_DEST_3			0x00000023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define 	SIS_MIXER_DEST_4			0x00000024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define 	SIS_MIXER_DEST_5			0x00000025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define 	SIS_MIXER_DEST_6			0x00000026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define 	SIS_MIXER_DEST_7			0x00000027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define 	SIS_MIXER_DEST_8			0x00000028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define 	SIS_MIXER_DEST_9			0x00000029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define 	SIS_MIXER_DEST_10			0x0000002a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define 	SIS_MIXER_DEST_11			0x0000002b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define 	SIS_MIXER_DEST_12			0x0000002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define 	SIS_MIXER_DEST_13			0x0000002d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define 	SIS_MIXER_DEST_14			0x0000002e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define 	SIS_MIXER_DEST_15			0x0000002f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Wave Engine Control Parameters (parameter RAM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SIS_WAVE_OFFSET		0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SIS_WAVE_SIZE		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SIS_WAVE_ADDR(addr, num) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	((num * SIS_WAVE_SIZE) + (addr) + SIS_WAVE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SIS_WAVE_GENERAL		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define		SIS_WAVE_GENERAL_WAVE_VOLUME			0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define		SIS_WAVE_GENERAL_MUSIC_VOLUME			0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define		SIS_WAVE_GENERAL_VOLUME_MASK			0x7f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SIS_WAVE_GENERAL_ARTICULATION	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define		SIS_WAVE_GENERAL_ARTICULATION_DELTA_MASK	0x3fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SIS_WAVE_ARTICULATION		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SIS_WAVE_TIMER			0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define SIS_WAVE_GENERATOR		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define SIS_WAVE_CHANNEL_CONTROL	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define		SIS_WAVE_CHANNEL_CONTROL_FIRST_SAMPLE		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define		SIS_WAVE_CHANNEL_CONTROL_AMP_ENABLE		0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define		SIS_WAVE_CHANNEL_CONTROL_FILTER_ENABLE		0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define		SIS_WAVE_CHANNEL_CONTROL_INTERPOLATE_ENABLE	0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SIS_WAVE_LFO_EG_CONTROL		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SIS_WAVE_LFO_EG_CONTROL_2	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SIS_WAVE_LFO_EG_CONTROL_3	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SIS_WAVE_LFO_EG_CONTROL_4	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #endif /* __sis7019_h__ */