^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA driver for RME Digi9652 audio interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 1999 IEM - Winfried Ritsch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 1999-2001 Paul Davis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/nospec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/asoundef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/current.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static bool precise_ptr[SNDRV_CARDS]; /* Enable precise pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MODULE_PARM_DESC(index, "Index value for RME Digi9652 (Hammerfall) soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MODULE_PARM_DESC(id, "ID string for RME Digi9652 (Hammerfall) soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MODULE_PARM_DESC(enable, "Enable/disable specific RME96{52,36} soundcards.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) module_param_array(precise_ptr, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MODULE_PARM_DESC(precise_ptr, "Enable precise pointer (doesn't work reliably).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MODULE_AUTHOR("Paul Davis <pbd@op.net>, Winfried Ritsch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MODULE_DESCRIPTION("RME Digi9652/Digi9636");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MODULE_SUPPORTED_DEVICE("{{RME,Hammerfall},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "{RME,Hammerfall-Light}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* The Hammerfall has two sets of 24 ADAT + 2 S/PDIF channels, one for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) capture, one for playback. Both the ADAT and S/PDIF channels appear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) to the host CPU in the same block of memory. There is no functional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) difference between them in terms of access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) The Hammerfall Light is identical to the Hammerfall, except that it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) has 2 sets 18 channels (16 ADAT + 2 S/PDIF) for capture and playback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RME9652_NCHANNELS 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RME9636_NCHANNELS 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Preferred sync source choices - used by "sync_pref" control switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RME9652_SYNC_FROM_SPDIF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RME9652_SYNC_FROM_ADAT1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RME9652_SYNC_FROM_ADAT2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RME9652_SYNC_FROM_ADAT3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Possible sources of S/PDIF input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RME9652_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RME9652_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RME9652_SPDIFIN_INTERN 2 /* internal (CDROM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* ------------- Status-Register bits --------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RME9652_IRQ (1<<0) /* IRQ is High if not reset by irq_clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RME9652_lock_2 (1<<1) /* ADAT 3-PLL: 1=locked, 0=unlocked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RME9652_lock_1 (1<<2) /* ADAT 2-PLL: 1=locked, 0=unlocked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RME9652_lock_0 (1<<3) /* ADAT 1-PLL: 1=locked, 0=unlocked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RME9652_fs48 (1<<4) /* sample rate is 0=44.1/88.2,1=48/96 Khz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RME9652_wsel_rd (1<<5) /* if Word-Clock is used and valid then 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* bits 6-15 encode h/w buffer pointer position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RME9652_sync_2 (1<<16) /* if ADAT-IN 3 in sync to system clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RME9652_sync_1 (1<<17) /* if ADAT-IN 2 in sync to system clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RME9652_sync_0 (1<<18) /* if ADAT-IN 1 in sync to system clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RME9652_DS_rd (1<<19) /* 1=Double Speed Mode, 0=Normal Speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RME9652_tc_busy (1<<20) /* 1=time-code copy in progress (960ms) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RME9652_tc_out (1<<21) /* time-code out bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RME9652_F_0 (1<<22) /* 000=64kHz, 100=88.2kHz, 011=96kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RME9652_F_1 (1<<23) /* 111=32kHz, 110=44.1kHz, 101=48kHz, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RME9652_F_2 (1<<24) /* external Crystal Chip if ERF=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RME9652_ERF (1<<25) /* Error-Flag of SDPIF Receiver (1=No Lock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RME9652_buffer_id (1<<26) /* toggles by each interrupt on rec/play */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RME9652_tc_valid (1<<27) /* 1 = a signal is detected on time-code input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RME9652_SPDIF_READ (1<<28) /* byte available from Rev 1.5+ S/PDIF interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RME9652_sync (RME9652_sync_0|RME9652_sync_1|RME9652_sync_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RME9652_lock (RME9652_lock_0|RME9652_lock_1|RME9652_lock_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RME9652_F (RME9652_F_0|RME9652_F_1|RME9652_F_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define rme9652_decode_spdif_rate(x) ((x)>>22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Bit 6..15 : h/w buffer pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RME9652_buf_pos 0x000FFC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Bits 31,30,29 are bits 5,4,3 of h/w pointer position on later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) Rev G EEPROMS and Rev 1.5 cards or later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RME9652_REV15_buf_pos(x) ((((x)&0xE0000000)>>26)|((x)&RME9652_buf_pos))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* amount of io space we remap for register access. i'm not sure we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) even need this much, but 1K is nice round number :)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RME9652_IO_EXTENT 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RME9652_init_buffer 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RME9652_play_buffer 32 /* holds ptr to 26x64kBit host RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RME9652_rec_buffer 36 /* holds ptr to 26x64kBit host RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RME9652_control_register 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RME9652_irq_clear 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RME9652_time_code 100 /* useful if used with alesis adat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RME9652_thru_base 128 /* 132...228 Thru for 26 channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Read-only registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Writing to any of the register locations writes to the status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) register. We'll use the first location as our point of access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RME9652_status_register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* --------- Control-Register Bits ---------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RME9652_start_bit (1<<0) /* start record/play */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* bits 1-3 encode buffersize/latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RME9652_Master (1<<4) /* Clock Mode Master=1,Slave/Auto=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RME9652_IE (1<<5) /* Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RME9652_freq (1<<6) /* samplerate 0=44.1/88.2, 1=48/96 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define RME9652_freq1 (1<<7) /* if 0, 32kHz, else always 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define RME9652_DS (1<<8) /* Doule Speed 0=44.1/48, 1=88.2/96 Khz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RME9652_PRO (1<<9) /* S/PDIF out: 0=consumer, 1=professional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RME9652_EMP (1<<10) /* Emphasis 0=None, 1=ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RME9652_Dolby (1<<11) /* Non-audio bit 1=set, 0=unset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RME9652_opt_out (1<<12) /* Use 1st optical OUT as SPDIF: 1=yes,0=no */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define RME9652_wsel (1<<13) /* use Wordclock as sync (overwrites master) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RME9652_inp_0 (1<<14) /* SPDIF-IN: 00=optical (ADAT1), */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RME9652_inp_1 (1<<15) /* 01=koaxial (Cinch), 10=Internal CDROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RME9652_SyncPref_ADAT2 (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define RME9652_SyncPref_ADAT3 (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RME9652_SPDIF_RESET (1<<18) /* Rev 1.5+: h/w S/PDIF receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define RME9652_SPDIF_SELECT (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RME9652_SPDIF_CLOCK (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RME9652_SPDIF_WRITE (1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define RME9652_ADAT1_INTERNAL (1<<22) /* Rev 1.5+: if set, internal CD connector carries ADAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* buffersize = 512Bytes * 2^n, where n is made from Bit2 ... Bit0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define RME9652_latency 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define rme9652_encode_latency(x) (((x)&0x7)<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define rme9652_decode_latency(x) (((x)>>1)&0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define rme9652_running_double_speed(s) ((s)->control_register & RME9652_DS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define RME9652_inp (RME9652_inp_0|RME9652_inp_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define rme9652_encode_spdif_in(x) (((x)&0x3)<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define rme9652_decode_spdif_in(x) (((x)>>14)&0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define RME9652_SyncPref_Mask (RME9652_SyncPref_ADAT2|RME9652_SyncPref_ADAT3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define RME9652_SyncPref_ADAT1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define RME9652_SyncPref_SPDIF (RME9652_SyncPref_ADAT2|RME9652_SyncPref_ADAT3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* the size of a substream (1 mono data stream) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define RME9652_CHANNEL_BUFFER_SAMPLES (16*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define RME9652_CHANNEL_BUFFER_BYTES (4*RME9652_CHANNEL_BUFFER_SAMPLES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* the size of the area we need to allocate for DMA transfers. the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) size is the same regardless of the number of channels - the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 9636 still uses the same memory area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) Note that we allocate 1 more channel than is apparently needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) because the h/w seems to write 1 byte beyond the end of the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) page. Sigh.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define RME9652_DMA_AREA_BYTES ((RME9652_NCHANNELS+1) * RME9652_CHANNEL_BUFFER_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define RME9652_DMA_AREA_KILOBYTES (RME9652_DMA_AREA_BYTES/1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct snd_rme9652 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned long port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) void __iomem *iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int precise_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 control_register; /* cached value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 thru_bits; /* thru 1=on, 0=off channel 1=Bit1... channel 26= Bit26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 creg_spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 creg_spdif_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) char *card_name; /* hammerfall or hammerfall light names */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) size_t hw_offsetmask; /* &-with status register to get real hw_offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) size_t prev_hw_offset; /* previous hw offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) size_t max_jitter; /* maximum jitter in frames for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) hw pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) size_t period_bytes; /* guess what this is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned char ds_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned char ss_channels; /* different for hammerfall/hammerfall-light */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct snd_dma_buffer playback_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct snd_dma_buffer capture_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned char *capture_buffer; /* suitably aligned address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned char *playback_buffer; /* suitably aligned address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pid_t capture_pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pid_t playback_pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct snd_pcm_substream *capture_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct snd_pcm_substream *playback_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int passthru; /* non-zero if doing pass-thru */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int hw_rev; /* h/w rev * 10 (i.e. 1.5 has hw_rev = 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int last_spdif_sample_rate; /* so that we can catch externally ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int last_adat_sample_rate; /* ... induced rate changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) const char *channel_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct snd_kcontrol *spdif_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* These tables map the ALSA channels 1..N to the channels that we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) need to use in order to find the relevant channel buffer. RME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) refer to this kind of mapping as between "the ADAT channel and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) the DMA channel." We index it using the logical audio channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) and the value is the DMA channel (i.e. channel buffer number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) where the data for that channel can be read/written from/to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const char channel_map_9652_ss[26] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 18, 19, 20, 21, 22, 23, 24, 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const char channel_map_9636_ss[26] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* channels 16 and 17 are S/PDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 24, 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* channels 18-25 don't exist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) -1, -1, -1, -1, -1, -1, -1, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const char channel_map_9652_ds[26] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* ADAT channels are remapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* channels 12 and 13 are S/PDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 24, 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* others don't exist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const char channel_map_9636_ds[26] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* ADAT channels are remapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 1, 3, 5, 7, 9, 11, 13, 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* channels 8 and 9 are S/PDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 24, 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* others don't exist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, size, dmab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (dmab->area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) snd_dma_free_pages(dmab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const struct pci_device_id snd_rme9652_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .vendor = 0x10ee,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .device = 0x3fc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }, /* RME Digi9652 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MODULE_DEVICE_TABLE(pci, snd_rme9652_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static inline void rme9652_write(struct snd_rme9652 *rme9652, int reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) writel(val, rme9652->iobase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static inline unsigned int rme9652_read(struct snd_rme9652 *rme9652, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return readl(rme9652->iobase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static inline int snd_rme9652_use_is_exclusive(struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) spin_lock_irqsave(&rme9652->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if ((rme9652->playback_pid != rme9652->capture_pid) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) (rme9652->playback_pid >= 0) && (rme9652->capture_pid >= 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) spin_unlock_irqrestore(&rme9652->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static inline int rme9652_adat_sample_rate(struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (rme9652_running_double_speed(rme9652)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return (rme9652_read(rme9652, RME9652_status_register) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) RME9652_fs48) ? 96000 : 88200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return (rme9652_read(rme9652, RME9652_status_register) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) RME9652_fs48) ? 48000 : 44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static inline void rme9652_compute_period_size(struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) i = rme9652->control_register & RME9652_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) rme9652->period_bytes = 1 << ((rme9652_decode_latency(i) + 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) rme9652->hw_offsetmask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) (rme9652->period_bytes * 2 - 1) & RME9652_buf_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) rme9652->max_jitter = 80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static snd_pcm_uframes_t rme9652_hw_pointer(struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned int offset, frag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) snd_pcm_uframes_t period_size = rme9652->period_bytes / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) snd_pcm_sframes_t delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) status = rme9652_read(rme9652, RME9652_status_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (!rme9652->precise_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return (status & RME9652_buffer_id) ? period_size : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) offset = status & RME9652_buf_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* The hardware may give a backward movement for up to 80 frames
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) Martin Kirst <martin.kirst@freenet.de> knows the details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) delta = rme9652->prev_hw_offset - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) delta &= 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (delta <= (snd_pcm_sframes_t)rme9652->max_jitter * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) offset = rme9652->prev_hw_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) rme9652->prev_hw_offset = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) offset &= rme9652->hw_offsetmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) offset /= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) frag = status & RME9652_buffer_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (offset < period_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (offset > rme9652->max_jitter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (frag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev_err(rme9652->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "Unexpected hw_pointer position (bufid == 0): status: %x offset: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) status, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) } else if (!frag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) offset -= rme9652->max_jitter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if ((int)offset < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) offset += period_size * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (offset > period_size + rme9652->max_jitter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!frag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_err(rme9652->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "Unexpected hw_pointer position (bufid == 1): status: %x offset: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) status, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) } else if (frag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) offset -= rme9652->max_jitter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static inline void rme9652_reset_hw_pointer(struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* reset the FIFO pointer to zero. We do this by writing to 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) registers, each of which is a 32bit wide register, and set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) them all to zero. Note that s->iobase is a pointer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int32, not pointer to char.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) rme9652_write(rme9652, i * 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) rme9652->prev_hw_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static inline void rme9652_start(struct snd_rme9652 *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) s->control_register |= (RME9652_IE | RME9652_start_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) rme9652_write(s, RME9652_control_register, s->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static inline void rme9652_stop(struct snd_rme9652 *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) s->control_register &= ~(RME9652_start_bit | RME9652_IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) rme9652_write(s, RME9652_control_register, s->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int rme9652_set_interrupt_interval(struct snd_rme9652 *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned int frames)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int restart = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) spin_lock_irq(&s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if ((restart = s->running)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) rme9652_stop(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) frames >>= 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) while (frames) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) n++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) frames >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) s->control_register &= ~RME9652_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) s->control_register |= rme9652_encode_latency(n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) rme9652_write(s, RME9652_control_register, s->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) rme9652_compute_period_size(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (restart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) rme9652_start(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) spin_unlock_irq(&s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int rme9652_set_rate(struct snd_rme9652 *rme9652, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int reject_if_open = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int xrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (!snd_rme9652_use_is_exclusive (rme9652)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Changing from a "single speed" to a "double speed" rate is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) not allowed if any substreams are open. This is because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) such a change causes a shift in the location of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) the DMA buffers and a reduction in the number of available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) Note that a similar but essentially insoluble problem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) exists for externally-driven rate changes. All we can do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) is to flag rate changes in the read/write routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) xrate = rme9652_adat_sample_rate(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (xrate > 48000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) reject_if_open = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (xrate > 48000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) reject_if_open = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) rate = RME9652_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (xrate < 48000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) reject_if_open = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) rate = RME9652_DS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (xrate < 48000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) reject_if_open = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) rate = RME9652_DS | RME9652_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (reject_if_open && (rme9652->capture_pid >= 0 || rme9652->playback_pid >= 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if ((restart = rme9652->running)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) rme9652_stop(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) rme9652->control_register &= ~(RME9652_freq | RME9652_DS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) rme9652->control_register |= rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (restart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) rme9652_start(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (rate & RME9652_DS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (rme9652->ss_channels == RME9652_NCHANNELS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) rme9652->channel_map = channel_map_9652_ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) rme9652->channel_map = channel_map_9636_ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (rme9652->ss_channels == RME9652_NCHANNELS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) rme9652->channel_map = channel_map_9652_ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) rme9652->channel_map = channel_map_9636_ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static void rme9652_set_thru(struct snd_rme9652 *rme9652, int channel, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) rme9652->passthru = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (channel < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* set thru for all channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) for (i = 0; i < RME9652_NCHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) rme9652->thru_bits |= (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) rme9652_write(rme9652, RME9652_thru_base + i * 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) for (i = 0; i < RME9652_NCHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) rme9652->thru_bits &= ~(1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) rme9652_write(rme9652, RME9652_thru_base + i * 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) int mapped_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) mapped_channel = rme9652->channel_map[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) rme9652->thru_bits |= (1 << mapped_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) rme9652->thru_bits &= ~(1 << mapped_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) rme9652_write(rme9652,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) RME9652_thru_base + mapped_channel * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) enable ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int rme9652_set_passthru(struct snd_rme9652 *rme9652, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (onoff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) rme9652_set_thru(rme9652, -1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* we don't want interrupts, so do a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) custom version of rme9652_start().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) rme9652->control_register =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) RME9652_inp_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) rme9652_encode_latency(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) RME9652_start_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) rme9652_reset_hw_pointer(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) rme9652_write(rme9652, RME9652_control_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) rme9652->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) rme9652->passthru = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) rme9652_set_thru(rme9652, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) rme9652_stop(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) rme9652->passthru = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static void rme9652_spdif_set_bit (struct snd_rme9652 *rme9652, int mask, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) rme9652->control_register |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) rme9652->control_register &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static void rme9652_spdif_write_byte (struct snd_rme9652 *rme9652, const int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) for (i = 0, mask = 0x80; i < 8; i++, mask >>= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (val & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_WRITE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_WRITE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static int rme9652_spdif_read_byte (struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) for (i = 0, mask = 0x80; i < 8; i++, mask >>= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (rme9652_read (rme9652, RME9652_status_register) & RME9652_SPDIF_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static void rme9652_write_spdif_codec (struct snd_rme9652 *rme9652, const int address, const int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) rme9652_spdif_write_byte (rme9652, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) rme9652_spdif_write_byte (rme9652, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) rme9652_spdif_write_byte (rme9652, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static int rme9652_spdif_read_codec (struct snd_rme9652 *rme9652, const int address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) rme9652_spdif_write_byte (rme9652, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) rme9652_spdif_write_byte (rme9652, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) rme9652_spdif_write_byte (rme9652, 0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ret = rme9652_spdif_read_byte (rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static void rme9652_initialize_spdif_receiver (struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* XXX what unsets this ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) rme9652->control_register |= RME9652_SPDIF_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) rme9652_write_spdif_codec (rme9652, 4, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) rme9652_write_spdif_codec (rme9652, 17, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) rme9652_write_spdif_codec (rme9652, 6, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static inline int rme9652_spdif_sample_rate(struct snd_rme9652 *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) unsigned int rate_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (rme9652_read(s, RME9652_status_register) & RME9652_ERF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return -1; /* error condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (s->hw_rev == 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int x, y, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) x = rme9652_spdif_read_codec (s, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (x != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) y = 48000 * 64 / x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) y = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (y > 30400 && y < 33600) ret = 32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) else if (y > 41900 && y < 46000) ret = 44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) else if (y > 46000 && y < 50400) ret = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) else if (y > 60800 && y < 67200) ret = 64000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) else if (y > 83700 && y < 92000) ret = 88200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) else if (y > 92000 && y < 100000) ret = 96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) else ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) rate_bits = rme9652_read(s, RME9652_status_register) & RME9652_F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) switch (rme9652_decode_spdif_rate(rate_bits)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) case 0x7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return 32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) case 0x6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return 44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) case 0x5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) case 0x4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return 88200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) case 0x3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return 96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) case 0x0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return 64000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dev_err(s->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) "%s: unknown S/PDIF input rate (bits = 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) s->card_name, rate_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /*-----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) Control Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static u32 snd_rme9652_convert_from_aes(struct snd_aes_iec958 *aes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME9652_PRO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME9652_Dolby : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (val & RME9652_PRO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME9652_EMP : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME9652_EMP : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static void snd_rme9652_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) aes->status[0] = ((val & RME9652_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) ((val & RME9652_Dolby) ? IEC958_AES0_NONAUDIO : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (val & RME9652_PRO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) aes->status[0] |= (val & RME9652_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) aes->status[0] |= (val & RME9652_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static int snd_rme9652_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int snd_rme9652_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) snd_rme9652_convert_to_aes(&ucontrol->value.iec958, rme9652->creg_spdif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static int snd_rme9652_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) val = snd_rme9652_convert_from_aes(&ucontrol->value.iec958);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) change = val != rme9652->creg_spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) rme9652->creg_spdif = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static int snd_rme9652_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static int snd_rme9652_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) snd_rme9652_convert_to_aes(&ucontrol->value.iec958, rme9652->creg_spdif_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static int snd_rme9652_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) val = snd_rme9652_convert_from_aes(&ucontrol->value.iec958);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) change = val != rme9652->creg_spdif_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) rme9652->creg_spdif_stream = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) rme9652->control_register &= ~(RME9652_PRO | RME9652_Dolby | RME9652_EMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) rme9652_write(rme9652, RME9652_control_register, rme9652->control_register |= val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static int snd_rme9652_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int snd_rme9652_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ucontrol->value.iec958.status[0] = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define RME9652_ADAT1_IN(xname, xindex) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .info = snd_rme9652_info_adat1_in, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .get = snd_rme9652_get_adat1_in, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .put = snd_rme9652_put_adat1_in }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static unsigned int rme9652_adat1_in(struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (rme9652->control_register & RME9652_ADAT1_INTERNAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static int rme9652_set_adat1_input(struct snd_rme9652 *rme9652, int internal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) int restart = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (internal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) rme9652->control_register |= RME9652_ADAT1_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) rme9652->control_register &= ~RME9652_ADAT1_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* XXX do we actually need to stop the card when we do this ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if ((restart = rme9652->running)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) rme9652_stop(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (restart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) rme9652_start(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static int snd_rme9652_info_adat1_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static const char * const texts[2] = {"ADAT1", "Internal"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return snd_ctl_enum_info(uinfo, 1, 2, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static int snd_rme9652_get_adat1_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ucontrol->value.enumerated.item[0] = rme9652_adat1_in(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static int snd_rme9652_put_adat1_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (!snd_rme9652_use_is_exclusive(rme9652))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) val = ucontrol->value.enumerated.item[0] % 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) change = val != rme9652_adat1_in(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) rme9652_set_adat1_input(rme9652, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define RME9652_SPDIF_IN(xname, xindex) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .info = snd_rme9652_info_spdif_in, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .get = snd_rme9652_get_spdif_in, .put = snd_rme9652_put_spdif_in }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static unsigned int rme9652_spdif_in(struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return rme9652_decode_spdif_in(rme9652->control_register &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) RME9652_inp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static int rme9652_set_spdif_input(struct snd_rme9652 *rme9652, int in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) int restart = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) rme9652->control_register &= ~RME9652_inp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) rme9652->control_register |= rme9652_encode_spdif_in(in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if ((restart = rme9652->running)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) rme9652_stop(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (restart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) rme9652_start(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static int snd_rme9652_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static const char * const texts[3] = {"ADAT1", "Coaxial", "Internal"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return snd_ctl_enum_info(uinfo, 1, 3, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static int snd_rme9652_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) ucontrol->value.enumerated.item[0] = rme9652_spdif_in(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static int snd_rme9652_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (!snd_rme9652_use_is_exclusive(rme9652))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) val = ucontrol->value.enumerated.item[0] % 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) change = val != rme9652_spdif_in(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) rme9652_set_spdif_input(rme9652, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define RME9652_SPDIF_OUT(xname, xindex) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .info = snd_rme9652_info_spdif_out, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .get = snd_rme9652_get_spdif_out, .put = snd_rme9652_put_spdif_out }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static int rme9652_spdif_out(struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return (rme9652->control_register & RME9652_opt_out) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static int rme9652_set_spdif_output(struct snd_rme9652 *rme9652, int out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) int restart = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) rme9652->control_register |= RME9652_opt_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) rme9652->control_register &= ~RME9652_opt_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if ((restart = rme9652->running)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) rme9652_stop(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (restart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) rme9652_start(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define snd_rme9652_info_spdif_out snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static int snd_rme9652_get_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ucontrol->value.integer.value[0] = rme9652_spdif_out(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static int snd_rme9652_put_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (!snd_rme9652_use_is_exclusive(rme9652))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) val = ucontrol->value.integer.value[0] & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) change = (int)val != rme9652_spdif_out(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) rme9652_set_spdif_output(rme9652, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define RME9652_SYNC_MODE(xname, xindex) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .info = snd_rme9652_info_sync_mode, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .get = snd_rme9652_get_sync_mode, .put = snd_rme9652_put_sync_mode }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static int rme9652_sync_mode(struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (rme9652->control_register & RME9652_wsel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) } else if (rme9652->control_register & RME9652_Master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static int rme9652_set_sync_mode(struct snd_rme9652 *rme9652, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) int restart = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) rme9652->control_register &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) ~(RME9652_Master | RME9652_wsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) rme9652->control_register =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) (rme9652->control_register & ~RME9652_wsel) | RME9652_Master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) rme9652->control_register |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) (RME9652_Master | RME9652_wsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if ((restart = rme9652->running)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) rme9652_stop(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (restart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) rme9652_start(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) static int snd_rme9652_info_sync_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static const char * const texts[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) "AutoSync", "Master", "Word Clock"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return snd_ctl_enum_info(uinfo, 1, 3, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static int snd_rme9652_get_sync_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ucontrol->value.enumerated.item[0] = rme9652_sync_mode(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static int snd_rme9652_put_sync_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) val = ucontrol->value.enumerated.item[0] % 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) change = (int)val != rme9652_sync_mode(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) rme9652_set_sync_mode(rme9652, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define RME9652_SYNC_PREF(xname, xindex) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .info = snd_rme9652_info_sync_pref, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .get = snd_rme9652_get_sync_pref, .put = snd_rme9652_put_sync_pref }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static int rme9652_sync_pref(struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) switch (rme9652->control_register & RME9652_SyncPref_Mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) case RME9652_SyncPref_ADAT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return RME9652_SYNC_FROM_ADAT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) case RME9652_SyncPref_ADAT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return RME9652_SYNC_FROM_ADAT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) case RME9652_SyncPref_ADAT3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) return RME9652_SYNC_FROM_ADAT3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) case RME9652_SyncPref_SPDIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return RME9652_SYNC_FROM_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /* Not reachable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static int rme9652_set_sync_pref(struct snd_rme9652 *rme9652, int pref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) int restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) rme9652->control_register &= ~RME9652_SyncPref_Mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) switch (pref) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) case RME9652_SYNC_FROM_ADAT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) rme9652->control_register |= RME9652_SyncPref_ADAT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) case RME9652_SYNC_FROM_ADAT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) rme9652->control_register |= RME9652_SyncPref_ADAT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) case RME9652_SYNC_FROM_ADAT3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) rme9652->control_register |= RME9652_SyncPref_ADAT3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) case RME9652_SYNC_FROM_SPDIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) rme9652->control_register |= RME9652_SyncPref_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if ((restart = rme9652->running)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) rme9652_stop(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (restart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) rme9652_start(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static int snd_rme9652_info_sync_pref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static const char * const texts[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) "IEC958 In", "ADAT1 In", "ADAT2 In", "ADAT3 In"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) return snd_ctl_enum_info(uinfo, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) rme9652->ss_channels == RME9652_NCHANNELS ? 4 : 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static int snd_rme9652_get_sync_pref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) ucontrol->value.enumerated.item[0] = rme9652_sync_pref(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static int snd_rme9652_put_sync_pref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) int change, max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (!snd_rme9652_use_is_exclusive(rme9652))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) max = rme9652->ss_channels == RME9652_NCHANNELS ? 4 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) val = ucontrol->value.enumerated.item[0] % max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) change = (int)val != rme9652_sync_pref(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) rme9652_set_sync_pref(rme9652, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static int snd_rme9652_info_thru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) uinfo->count = rme9652->ss_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) uinfo->value.integer.max = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static int snd_rme9652_get_thru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) unsigned int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) u32 thru_bits = rme9652->thru_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) for (k = 0; k < rme9652->ss_channels; ++k) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) ucontrol->value.integer.value[k] = !!(thru_bits & (1 << k));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static int snd_rme9652_put_thru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) unsigned int chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) u32 thru_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (!snd_rme9652_use_is_exclusive(rme9652))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) for (chn = 0; chn < rme9652->ss_channels; ++chn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (ucontrol->value.integer.value[chn])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) thru_bits |= 1 << chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) change = thru_bits ^ rme9652->thru_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if (change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) for (chn = 0; chn < rme9652->ss_channels; ++chn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (!(change & (1 << chn)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) rme9652_set_thru(rme9652,chn,thru_bits&(1<<chn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return !!change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define RME9652_PASSTHRU(xname, xindex) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .info = snd_rme9652_info_passthru, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .put = snd_rme9652_put_passthru, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .get = snd_rme9652_get_passthru }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define snd_rme9652_info_passthru snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static int snd_rme9652_get_passthru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) ucontrol->value.integer.value[0] = rme9652->passthru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static int snd_rme9652_put_passthru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (!snd_rme9652_use_is_exclusive(rme9652))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) val = ucontrol->value.integer.value[0] & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) change = (ucontrol->value.integer.value[0] != rme9652->passthru);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) err = rme9652_set_passthru(rme9652, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) return err ? err : change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) /* Read-only switches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define RME9652_SPDIF_RATE(xname, xindex) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .info = snd_rme9652_info_spdif_rate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .get = snd_rme9652_get_spdif_rate }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static int snd_rme9652_info_spdif_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) uinfo->value.integer.max = 96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) static int snd_rme9652_get_spdif_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ucontrol->value.integer.value[0] = rme9652_spdif_sample_rate(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #define RME9652_ADAT_SYNC(xname, xindex, xidx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .info = snd_rme9652_info_adat_sync, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .get = snd_rme9652_get_adat_sync, .private_value = xidx }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) static int snd_rme9652_info_adat_sync(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static const char * const texts[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) "No Lock", "Lock", "No Lock Sync", "Lock Sync"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return snd_ctl_enum_info(uinfo, 1, 4, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) static int snd_rme9652_get_adat_sync(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) unsigned int mask1, mask2, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) switch (kcontrol->private_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) case 0: mask1 = RME9652_lock_0; mask2 = RME9652_sync_0; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) case 1: mask1 = RME9652_lock_1; mask2 = RME9652_sync_1; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) case 2: mask1 = RME9652_lock_2; mask2 = RME9652_sync_2; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) default: return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) val = rme9652_read(rme9652, RME9652_status_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) ucontrol->value.enumerated.item[0] = (val & mask1) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) ucontrol->value.enumerated.item[0] |= (val & mask2) ? 2 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define RME9652_TC_VALID(xname, xindex) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .info = snd_rme9652_info_tc_valid, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .get = snd_rme9652_get_tc_valid }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #define snd_rme9652_info_tc_valid snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) static int snd_rme9652_get_tc_valid(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) ucontrol->value.integer.value[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) (rme9652_read(rme9652, RME9652_status_register) & RME9652_tc_valid) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) #ifdef ALSA_HAS_STANDARD_WAY_OF_RETURNING_TIMECODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) /* FIXME: this routine needs a port to the new control API --jk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static int snd_rme9652_get_tc_value(void *private_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) snd_kswitch_t *kswitch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) snd_switch_t *uswitch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) struct snd_rme9652 *s = (struct snd_rme9652 *) private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) uswitch->type = SNDRV_SW_TYPE_DWORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if ((rme9652_read(s, RME9652_status_register) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) RME9652_tc_valid) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) uswitch->value.data32[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /* timecode request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) rme9652_write(s, RME9652_time_code, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) /* XXX bug alert: loop-based timing !!!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) for (i = 0; i < 50; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (!(rme9652_read(s, i * 4) & RME9652_tc_busy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (!(rme9652_read(s, i * 4) & RME9652_tc_busy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) for (i = 0; i < 32; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) value >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) if (rme9652_read(s, i * 4) & RME9652_tc_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) value |= 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (value > 2 * 60 * 48000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) value -= 2 * 60 * 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) uswitch->value.data32[0] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) #endif /* ALSA_HAS_STANDARD_WAY_OF_RETURNING_TIMECODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) static const struct snd_kcontrol_new snd_rme9652_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .info = snd_rme9652_control_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .get = snd_rme9652_control_spdif_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .put = snd_rme9652_control_spdif_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .info = snd_rme9652_control_spdif_stream_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .get = snd_rme9652_control_spdif_stream_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .put = snd_rme9652_control_spdif_stream_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .info = snd_rme9652_control_spdif_mask_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .get = snd_rme9652_control_spdif_mask_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .private_value = IEC958_AES0_NONAUDIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) IEC958_AES0_PROFESSIONAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) IEC958_AES0_CON_EMPHASIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .info = snd_rme9652_control_spdif_mask_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .get = snd_rme9652_control_spdif_mask_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .private_value = IEC958_AES0_NONAUDIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) IEC958_AES0_PROFESSIONAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) IEC958_AES0_PRO_EMPHASIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) RME9652_SPDIF_IN("IEC958 Input Connector", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) RME9652_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) RME9652_SYNC_MODE("Sync Mode", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) RME9652_SYNC_PREF("Preferred Sync Source", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .name = "Channels Thru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .info = snd_rme9652_info_thru,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .get = snd_rme9652_get_thru,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .put = snd_rme9652_put_thru,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) RME9652_SPDIF_RATE("IEC958 Sample Rate", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) RME9652_ADAT_SYNC("ADAT1 Sync Check", 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) RME9652_ADAT_SYNC("ADAT2 Sync Check", 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) RME9652_TC_VALID("Timecode Valid", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) RME9652_PASSTHRU("Passthru", 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static const struct snd_kcontrol_new snd_rme9652_adat3_check =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) RME9652_ADAT_SYNC("ADAT3 Sync Check", 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static const struct snd_kcontrol_new snd_rme9652_adat1_input =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) RME9652_ADAT1_IN("ADAT1 Input Source", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static int snd_rme9652_create_controls(struct snd_card *card, struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) for (idx = 0; idx < ARRAY_SIZE(snd_rme9652_controls); idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme9652_controls[idx], rme9652))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (idx == 1) /* IEC958 (S/PDIF) Stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) rme9652->spdif_ctl = kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (rme9652->ss_channels == RME9652_NCHANNELS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme9652_adat3_check, rme9652))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) if (rme9652->hw_rev >= 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme9652_adat1_input, rme9652))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) /*------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) /proc interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) ------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) snd_rme9652_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) struct snd_rme9652 *rme9652 = (struct snd_rme9652 *) entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) u32 thru_bits = rme9652->thru_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) int show_auto_sync_source = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) int x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) status = rme9652_read(rme9652, RME9652_status_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) snd_iprintf(buffer, "%s (Card #%d)\n", rme9652->card_name, rme9652->card->number + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) rme9652->capture_buffer, rme9652->playback_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) rme9652->irq, rme9652->port, (unsigned long)rme9652->iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) snd_iprintf(buffer, "Control register: %x\n", rme9652->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) snd_iprintf(buffer, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) x = 1 << (6 + rme9652_decode_latency(rme9652->control_register &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) RME9652_latency));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) snd_iprintf(buffer, "Latency: %d samples (2 periods of %lu bytes)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) x, (unsigned long) rme9652->period_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) snd_iprintf(buffer, "Hardware pointer (frames): %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) rme9652_hw_pointer(rme9652));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) snd_iprintf(buffer, "Passthru: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) rme9652->passthru ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if ((rme9652->control_register & (RME9652_Master | RME9652_wsel)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) snd_iprintf(buffer, "Clock mode: autosync\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) show_auto_sync_source = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) } else if (rme9652->control_register & RME9652_wsel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) if (status & RME9652_wsel_rd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) snd_iprintf(buffer, "Clock mode: word clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) snd_iprintf(buffer, "Clock mode: word clock (no signal)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) snd_iprintf(buffer, "Clock mode: master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (show_auto_sync_source) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) switch (rme9652->control_register & RME9652_SyncPref_Mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) case RME9652_SyncPref_ADAT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) snd_iprintf(buffer, "Pref. sync source: ADAT1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) case RME9652_SyncPref_ADAT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) snd_iprintf(buffer, "Pref. sync source: ADAT2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) case RME9652_SyncPref_ADAT3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) snd_iprintf(buffer, "Pref. sync source: ADAT3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) case RME9652_SyncPref_SPDIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) snd_iprintf(buffer, "Pref. sync source: IEC958\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) snd_iprintf(buffer, "Pref. sync source: ???\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) if (rme9652->hw_rev >= 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) snd_iprintf(buffer, "\nADAT1 Input source: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) (rme9652->control_register & RME9652_ADAT1_INTERNAL) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) "Internal" : "ADAT1 optical");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) snd_iprintf(buffer, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) switch (rme9652_decode_spdif_in(rme9652->control_register &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) RME9652_inp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) case RME9652_SPDIFIN_OPTICAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) snd_iprintf(buffer, "IEC958 input: ADAT1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) case RME9652_SPDIFIN_COAXIAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) snd_iprintf(buffer, "IEC958 input: Coaxial\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) case RME9652_SPDIFIN_INTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) snd_iprintf(buffer, "IEC958 input: Internal\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) snd_iprintf(buffer, "IEC958 input: ???\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (rme9652->control_register & RME9652_opt_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if (rme9652->control_register & RME9652_PRO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) snd_iprintf(buffer, "IEC958 quality: Professional\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) snd_iprintf(buffer, "IEC958 quality: Consumer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) if (rme9652->control_register & RME9652_EMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) snd_iprintf(buffer, "IEC958 emphasis: on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) snd_iprintf(buffer, "IEC958 emphasis: off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) if (rme9652->control_register & RME9652_Dolby) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) snd_iprintf(buffer, "IEC958 Dolby: on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) snd_iprintf(buffer, "IEC958 Dolby: off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) i = rme9652_spdif_sample_rate(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) if (i < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) snd_iprintf(buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) "IEC958 sample rate: error flag set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) } else if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) snd_iprintf(buffer, "IEC958 sample rate: undetermined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) snd_iprintf(buffer, "IEC958 sample rate: %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) snd_iprintf(buffer, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) snd_iprintf(buffer, "ADAT Sample rate: %dHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) rme9652_adat_sample_rate(rme9652));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) /* Sync Check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) x = status & RME9652_sync_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (status & RME9652_lock_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) snd_iprintf(buffer, "ADAT1: No Lock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) x = status & RME9652_sync_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (status & RME9652_lock_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) snd_iprintf(buffer, "ADAT2: No Lock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) x = status & RME9652_sync_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) if (status & RME9652_lock_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) snd_iprintf(buffer, "ADAT3: No Lock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) snd_iprintf(buffer, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) snd_iprintf(buffer, "Timecode signal: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) (status & RME9652_tc_valid) ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) /* thru modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) snd_iprintf(buffer, "Punch Status:\n\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) for (i = 0; i < rme9652->ss_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (thru_bits & (1 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) snd_iprintf(buffer, "%2d: on ", i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) snd_iprintf(buffer, "%2d: off ", i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if (((i + 1) % 8) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) snd_iprintf(buffer, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) snd_iprintf(buffer, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) static void snd_rme9652_proc_init(struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) snd_card_ro_proc_new(rme9652->card, "rme9652", rme9652,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) snd_rme9652_proc_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) static void snd_rme9652_free_buffers(struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) snd_hammerfall_free_buffer(&rme9652->capture_dma_buf, rme9652->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) snd_hammerfall_free_buffer(&rme9652->playback_dma_buf, rme9652->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) static int snd_rme9652_free(struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if (rme9652->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) rme9652_stop(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) snd_rme9652_free_buffers(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) if (rme9652->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) free_irq(rme9652->irq, (void *)rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) iounmap(rme9652->iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (rme9652->port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) pci_release_regions(rme9652->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) if (pci_is_enabled(rme9652->pci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) pci_disable_device(rme9652->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) static int snd_rme9652_initialize_memory(struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) unsigned long pb_bus, cb_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (snd_hammerfall_get_buffer(rme9652->pci, &rme9652->capture_dma_buf, RME9652_DMA_AREA_BYTES) < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) snd_hammerfall_get_buffer(rme9652->pci, &rme9652->playback_dma_buf, RME9652_DMA_AREA_BYTES) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) if (rme9652->capture_dma_buf.area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) snd_dma_free_pages(&rme9652->capture_dma_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) dev_err(rme9652->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) "%s: no buffers available\n", rme9652->card_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) /* Align to bus-space 64K boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) cb_bus = ALIGN(rme9652->capture_dma_buf.addr, 0x10000ul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) pb_bus = ALIGN(rme9652->playback_dma_buf.addr, 0x10000ul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) /* Tell the card where it is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) rme9652_write(rme9652, RME9652_rec_buffer, cb_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) rme9652_write(rme9652, RME9652_play_buffer, pb_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) rme9652->capture_buffer = rme9652->capture_dma_buf.area + (cb_bus - rme9652->capture_dma_buf.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) rme9652->playback_buffer = rme9652->playback_dma_buf.area + (pb_bus - rme9652->playback_dma_buf.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) static void snd_rme9652_set_defaults(struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) unsigned int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) /* ASSUMPTION: rme9652->lock is either held, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) there is no need to hold it (e.g. during module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) initialization).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /* set defaults:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) SPDIF Input via Coax
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) autosync clock mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) maximum latency (7 = 8192 samples, 64Kbyte buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) which implies 2 4096 sample, 32Kbyte periods).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) if rev 1.5, initialize the S/PDIF receiver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) rme9652->control_register =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) RME9652_inp_0 | rme9652_encode_latency(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) rme9652_reset_hw_pointer(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) rme9652_compute_period_size(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) /* default: thru off for all channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) for (k = 0; k < RME9652_NCHANNELS; ++k)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) rme9652_write(rme9652, RME9652_thru_base + k * 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) rme9652->thru_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) rme9652->passthru = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) /* set a default rate so that the channel map is set up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) rme9652_set_rate(rme9652, 48000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) static irqreturn_t snd_rme9652_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) struct snd_rme9652 *rme9652 = (struct snd_rme9652 *) dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (!(rme9652_read(rme9652, RME9652_status_register) & RME9652_IRQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) rme9652_write(rme9652, RME9652_irq_clear, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) if (rme9652->capture_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) snd_pcm_period_elapsed(rme9652->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (rme9652->playback_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) snd_pcm_period_elapsed(rme9652->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) static snd_pcm_uframes_t snd_rme9652_hw_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) return rme9652_hw_pointer(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) static char *rme9652_channel_buffer_location(struct snd_rme9652 *rme9652,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) int stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) int mapped_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) if (snd_BUG_ON(channel < 0 || channel >= RME9652_NCHANNELS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) if ((mapped_channel = rme9652->channel_map[channel]) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) if (stream == SNDRV_PCM_STREAM_CAPTURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) return rme9652->capture_buffer +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) (mapped_channel * RME9652_CHANNEL_BUFFER_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) return rme9652->playback_buffer +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) (mapped_channel * RME9652_CHANNEL_BUFFER_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) static int snd_rme9652_playback_copy(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) int channel, unsigned long pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) void __user *src, unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) char *channel_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) if (snd_BUG_ON(pos + count > RME9652_CHANNEL_BUFFER_BYTES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) channel_buf = rme9652_channel_buffer_location (rme9652,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) substream->pstr->stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) if (snd_BUG_ON(!channel_buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (copy_from_user(channel_buf + pos, src, count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) static int snd_rme9652_playback_copy_kernel(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) int channel, unsigned long pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) void *src, unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) char *channel_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) channel_buf = rme9652_channel_buffer_location(rme9652,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) substream->pstr->stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) if (snd_BUG_ON(!channel_buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) memcpy(channel_buf + pos, src, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) static int snd_rme9652_capture_copy(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) int channel, unsigned long pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) void __user *dst, unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) char *channel_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) if (snd_BUG_ON(pos + count > RME9652_CHANNEL_BUFFER_BYTES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) channel_buf = rme9652_channel_buffer_location (rme9652,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) substream->pstr->stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) if (snd_BUG_ON(!channel_buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) if (copy_to_user(dst, channel_buf + pos, count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) static int snd_rme9652_capture_copy_kernel(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) int channel, unsigned long pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) void *dst, unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) char *channel_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) channel_buf = rme9652_channel_buffer_location(rme9652,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) substream->pstr->stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) if (snd_BUG_ON(!channel_buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) memcpy(dst, channel_buf + pos, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) static int snd_rme9652_hw_silence(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) int channel, unsigned long pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) char *channel_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) channel_buf = rme9652_channel_buffer_location (rme9652,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) substream->pstr->stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) if (snd_BUG_ON(!channel_buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) memset(channel_buf + pos, 0, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) static int snd_rme9652_reset(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) struct snd_pcm_substream *other;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) other = rme9652->capture_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) other = rme9652->playback_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) if (rme9652->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) runtime->status->hw_ptr = rme9652_hw_pointer(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) runtime->status->hw_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) if (other) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) struct snd_pcm_substream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) struct snd_pcm_runtime *oruntime = other->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) snd_pcm_group_for_each_entry(s, substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) if (s == other) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) oruntime->status->hw_ptr = runtime->status->hw_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) static int snd_rme9652_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) pid_t this_pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) pid_t other_pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) rme9652->control_register &= ~(RME9652_PRO | RME9652_Dolby | RME9652_EMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) rme9652_write(rme9652, RME9652_control_register, rme9652->control_register |= rme9652->creg_spdif_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) this_pid = rme9652->playback_pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) other_pid = rme9652->capture_pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) this_pid = rme9652->capture_pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) other_pid = rme9652->playback_pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if ((other_pid > 0) && (this_pid != other_pid)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) /* The other stream is open, and not by the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) task as this one. Make sure that the parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) that matter are the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) if ((int)params_rate(params) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) rme9652_adat_sample_rate(rme9652)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) if (params_period_size(params) != rme9652->period_bytes / 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) /* We're fine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) /* how to make sure that the rate matches an externally-set one ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if ((err = rme9652_set_rate(rme9652, params_rate(params))) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) if ((err = rme9652_set_interrupt_interval(rme9652, params_period_size(params))) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) static int snd_rme9652_channel_info(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) struct snd_pcm_channel_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) int chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) if (snd_BUG_ON(info->channel >= RME9652_NCHANNELS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) chn = rme9652->channel_map[array_index_nospec(info->channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) RME9652_NCHANNELS)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) if (chn < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) info->offset = chn * RME9652_CHANNEL_BUFFER_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) info->first = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) info->step = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) static int snd_rme9652_ioctl(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) case SNDRV_PCM_IOCTL1_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) return snd_rme9652_reset(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) struct snd_pcm_channel_info *info = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) return snd_rme9652_channel_info(substream, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) return snd_pcm_lib_ioctl(substream, cmd, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) static void rme9652_silence_playback(struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) memset(rme9652->playback_buffer, 0, RME9652_DMA_AREA_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) static int snd_rme9652_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) struct snd_pcm_substream *other;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) int running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) spin_lock(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) running = rme9652->running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) running |= 1 << substream->stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) running &= ~(1 << substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) spin_unlock(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) other = rme9652->capture_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) other = rme9652->playback_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) if (other) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) struct snd_pcm_substream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) snd_pcm_group_for_each_entry(s, substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) if (s == other) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) snd_pcm_trigger_done(s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) if (cmd == SNDRV_PCM_TRIGGER_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) running |= 1 << s->stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) running &= ~(1 << s->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) goto _ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) if (cmd == SNDRV_PCM_TRIGGER_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) rme9652_silence_playback(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) if (running &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) rme9652_silence_playback(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) rme9652_silence_playback(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) _ok:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) snd_pcm_trigger_done(substream, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) if (!rme9652->running && running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) rme9652_start(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) else if (rme9652->running && !running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) rme9652_stop(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) rme9652->running = running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) spin_unlock(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) static int snd_rme9652_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) spin_lock_irqsave(&rme9652->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) if (!rme9652->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) rme9652_reset_hw_pointer(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) spin_unlock_irqrestore(&rme9652->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) static const struct snd_pcm_hardware snd_rme9652_playback_subinfo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .info = (SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) SNDRV_PCM_INFO_NONINTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) SNDRV_PCM_INFO_SYNC_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) SNDRV_PCM_INFO_DOUBLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .formats = SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .rates = (SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) SNDRV_PCM_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) SNDRV_PCM_RATE_88200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) SNDRV_PCM_RATE_96000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .rate_min = 44100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .channels_min = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .channels_max = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .buffer_bytes_max = RME9652_CHANNEL_BUFFER_BYTES * 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .period_bytes_min = (64 * 4) * 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .period_bytes_max = (8192 * 4) * 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .periods_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) static const struct snd_pcm_hardware snd_rme9652_capture_subinfo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .info = (SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) SNDRV_PCM_INFO_NONINTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) SNDRV_PCM_INFO_SYNC_START),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .formats = SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .rates = (SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) SNDRV_PCM_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) SNDRV_PCM_RATE_88200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) SNDRV_PCM_RATE_96000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .rate_min = 44100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .channels_min = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .channels_max = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .buffer_bytes_max = RME9652_CHANNEL_BUFFER_BYTES *26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .period_bytes_min = (64 * 4) * 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .period_bytes_max = (8192 * 4) * 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .periods_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) static const unsigned int period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) static const struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .count = ARRAY_SIZE(period_sizes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .list = period_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .mask = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) static int snd_rme9652_hw_rule_channels(struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) struct snd_pcm_hw_rule *rule)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) struct snd_rme9652 *rme9652 = rule->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) unsigned int list[2] = { rme9652->ds_channels, rme9652->ss_channels };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) return snd_interval_list(c, 2, list, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) static int snd_rme9652_hw_rule_channels_rate(struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) struct snd_pcm_hw_rule *rule)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) struct snd_rme9652 *rme9652 = rule->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) if (r->min > 48000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) struct snd_interval t = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) .min = rme9652->ds_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .max = rme9652->ds_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) .integer = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) return snd_interval_refine(c, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) } else if (r->max < 88200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) struct snd_interval t = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .min = rme9652->ss_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .max = rme9652->ss_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) .integer = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) return snd_interval_refine(c, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) static int snd_rme9652_hw_rule_rate_channels(struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) struct snd_pcm_hw_rule *rule)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) struct snd_rme9652 *rme9652 = rule->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) if (c->min >= rme9652->ss_channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) struct snd_interval t = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .min = 44100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .integer = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) return snd_interval_refine(r, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) } else if (c->max <= rme9652->ds_channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) struct snd_interval t = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .min = 88200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .integer = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) return snd_interval_refine(r, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) static int snd_rme9652_playback_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) runtime->hw = snd_rme9652_playback_subinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) runtime->dma_area = rme9652->playback_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) runtime->dma_bytes = RME9652_DMA_AREA_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) if (rme9652->capture_substream == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) rme9652_stop(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) rme9652_set_thru(rme9652, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) rme9652->playback_pid = current->pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) rme9652->playback_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hw_constraints_period_sizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) snd_rme9652_hw_rule_channels, rme9652,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) SNDRV_PCM_HW_PARAM_CHANNELS, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) snd_rme9652_hw_rule_channels_rate, rme9652,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) SNDRV_PCM_HW_PARAM_RATE, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) snd_rme9652_hw_rule_rate_channels, rme9652,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) SNDRV_PCM_HW_PARAM_CHANNELS, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) rme9652->creg_spdif_stream = rme9652->creg_spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) rme9652->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) snd_ctl_notify(rme9652->card, SNDRV_CTL_EVENT_MASK_VALUE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) SNDRV_CTL_EVENT_MASK_INFO, &rme9652->spdif_ctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) static int snd_rme9652_playback_release(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) rme9652->playback_pid = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) rme9652->playback_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) rme9652->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) snd_ctl_notify(rme9652->card, SNDRV_CTL_EVENT_MASK_VALUE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) SNDRV_CTL_EVENT_MASK_INFO, &rme9652->spdif_ctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) static int snd_rme9652_capture_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) runtime->hw = snd_rme9652_capture_subinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) runtime->dma_area = rme9652->capture_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) runtime->dma_bytes = RME9652_DMA_AREA_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) if (rme9652->playback_substream == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) rme9652_stop(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) rme9652_set_thru(rme9652, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) rme9652->capture_pid = current->pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) rme9652->capture_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hw_constraints_period_sizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) snd_rme9652_hw_rule_channels, rme9652,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) SNDRV_PCM_HW_PARAM_CHANNELS, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) snd_rme9652_hw_rule_channels_rate, rme9652,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) SNDRV_PCM_HW_PARAM_RATE, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) snd_rme9652_hw_rule_rate_channels, rme9652,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) SNDRV_PCM_HW_PARAM_CHANNELS, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) static int snd_rme9652_capture_release(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) spin_lock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) rme9652->capture_pid = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) rme9652->capture_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) spin_unlock_irq(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) static const struct snd_pcm_ops snd_rme9652_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .open = snd_rme9652_playback_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .close = snd_rme9652_playback_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) .ioctl = snd_rme9652_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .hw_params = snd_rme9652_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .prepare = snd_rme9652_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .trigger = snd_rme9652_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .pointer = snd_rme9652_hw_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .copy_user = snd_rme9652_playback_copy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .copy_kernel = snd_rme9652_playback_copy_kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .fill_silence = snd_rme9652_hw_silence,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) static const struct snd_pcm_ops snd_rme9652_capture_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) .open = snd_rme9652_capture_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .close = snd_rme9652_capture_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) .ioctl = snd_rme9652_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) .hw_params = snd_rme9652_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .prepare = snd_rme9652_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .trigger = snd_rme9652_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .pointer = snd_rme9652_hw_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .copy_user = snd_rme9652_capture_copy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .copy_kernel = snd_rme9652_capture_copy_kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) static int snd_rme9652_create_pcm(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) struct snd_rme9652 *rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) if ((err = snd_pcm_new(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) rme9652->card_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) 0, 1, 1, &pcm)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) rme9652->pcm = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) pcm->private_data = rme9652;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) strcpy(pcm->name, rme9652->card_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme9652_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme9652_capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) static int snd_rme9652_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) struct snd_rme9652 *rme9652,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) int precise_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) struct pci_dev *pci = rme9652->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) unsigned short rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) rme9652->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) rme9652->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) pci_read_config_word(rme9652->pci, PCI_CLASS_REVISION, &rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) switch (rev & 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) /* who knows? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) if ((err = pci_enable_device(pci)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) spin_lock_init(&rme9652->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) if ((err = pci_request_regions(pci, "rme9652")) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) rme9652->port = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) rme9652->iobase = ioremap(rme9652->port, RME9652_IO_EXTENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) if (rme9652->iobase == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) dev_err(card->dev, "unable to remap region 0x%lx-0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) rme9652->port, rme9652->port + RME9652_IO_EXTENT - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) if (request_irq(pci->irq, snd_rme9652_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) KBUILD_MODNAME, rme9652)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) dev_err(card->dev, "unable to request IRQ %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) rme9652->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) card->sync_irq = rme9652->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) rme9652->precise_ptr = precise_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) /* Determine the h/w rev level of the card. This seems like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) a particularly kludgy way to encode it, but its what RME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) chose to do, so we follow them ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) status = rme9652_read(rme9652, RME9652_status_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) if (rme9652_decode_spdif_rate(status&RME9652_F) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) rme9652->hw_rev = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) rme9652->hw_rev = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) /* Differentiate between the standard Hammerfall, and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) "Light", which does not have the expansion board. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) method comes from information received from Mathhias
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) Clausen at RME. Display the EEPROM and h/w revID where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) relevant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) case 8: /* original eprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) strcpy(card->driver, "RME9636");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) if (rme9652->hw_rev == 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) rme9652->card_name = "RME Digi9636 (Rev 1.5)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) rme9652->card_name = "RME Digi9636";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) rme9652->ss_channels = RME9636_NCHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) case 9: /* W36_G EPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) strcpy(card->driver, "RME9636");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) rme9652->card_name = "RME Digi9636 (Rev G)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) rme9652->ss_channels = RME9636_NCHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) case 4: /* W52_G EPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) strcpy(card->driver, "RME9652");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) rme9652->card_name = "RME Digi9652 (Rev G)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) rme9652->ss_channels = RME9652_NCHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) case 3: /* original eprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) strcpy(card->driver, "RME9652");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) if (rme9652->hw_rev == 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) rme9652->card_name = "RME Digi9652 (Rev 1.5)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) rme9652->card_name = "RME Digi9652";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) rme9652->ss_channels = RME9652_NCHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) rme9652->ds_channels = (rme9652->ss_channels - 2) / 2 + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) pci_set_master(rme9652->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) if ((err = snd_rme9652_initialize_memory(rme9652)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) if ((err = snd_rme9652_create_pcm(card, rme9652)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) if ((err = snd_rme9652_create_controls(card, rme9652)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) snd_rme9652_proc_init(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) rme9652->last_spdif_sample_rate = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) rme9652->last_adat_sample_rate = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) rme9652->playback_pid = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) rme9652->capture_pid = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) rme9652->capture_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) rme9652->playback_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) snd_rme9652_set_defaults(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) if (rme9652->hw_rev == 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) rme9652_initialize_spdif_receiver (rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) static void snd_rme9652_card_free(struct snd_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) struct snd_rme9652 *rme9652 = (struct snd_rme9652 *) card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) if (rme9652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) snd_rme9652_free(rme9652);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) static int snd_rme9652_probe(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) struct snd_rme9652 *rme9652;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) if (dev >= SNDRV_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) if (!enable[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) sizeof(struct snd_rme9652), &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) rme9652 = (struct snd_rme9652 *) card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) card->private_free = snd_rme9652_card_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) rme9652->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) rme9652->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) err = snd_rme9652_create(card, rme9652, precise_ptr[dev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) goto free_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) strcpy(card->shortname, rme9652->card_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) sprintf(card->longname, "%s at 0x%lx, irq %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) card->shortname, rme9652->port, rme9652->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) err = snd_card_register(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) free_card:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) static void snd_rme9652_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) snd_card_free(pci_get_drvdata(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) static struct pci_driver rme9652_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) .id_table = snd_rme9652_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) .probe = snd_rme9652_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) .remove = snd_rme9652_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) module_pci_driver(rme9652_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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