^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/asoundef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* note, two last pcis should be equal, it is not a bug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) "Digi96/8 PAD");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) "{RME,Digi96/8},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "{RME,Digi96/8 PRO},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) "{RME,Digi96/8 PST},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) "{RME,Digi96/8 PAD}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Defines for RME Digi96 series, from internal RME reference documents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * dated 12.01.00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RME96_SPDIF_NCHANNELS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Playback and capture buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RME96_BUFFER_SIZE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* IO area size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RME96_IO_SIZE 0x60000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* IO area offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RME96_IO_PLAY_BUFFER 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RME96_IO_REC_BUFFER 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RME96_IO_CONTROL_REGISTER 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RME96_IO_ADDITIONAL_REG 0x20004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RME96_IO_CONFIRM_REC_IRQ 0x2000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RME96_IO_SET_PLAY_POS 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RME96_IO_RESET_PLAY_POS 0x4FFFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RME96_IO_SET_REC_POS 0x50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RME96_IO_RESET_REC_POS 0x5FFFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RME96_IO_GET_PLAY_POS 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RME96_IO_GET_REC_POS 0x30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Write control register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RME96_WCR_START (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RME96_WCR_START_2 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RME96_WCR_GAIN_0 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RME96_WCR_GAIN_1 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RME96_WCR_MODE24 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RME96_WCR_MODE24_2 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RME96_WCR_BM (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RME96_WCR_BM_2 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RME96_WCR_ADAT (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RME96_WCR_FREQ_0 (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RME96_WCR_FREQ_1 (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RME96_WCR_DS (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RME96_WCR_PRO (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RME96_WCR_EMP (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RME96_WCR_SEL (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RME96_WCR_MASTER (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RME96_WCR_PD (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RME96_WCR_INP_0 (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RME96_WCR_INP_1 (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RME96_WCR_THRU_0 (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RME96_WCR_THRU_1 (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RME96_WCR_THRU_2 (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RME96_WCR_THRU_3 (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RME96_WCR_THRU_4 (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RME96_WCR_THRU_5 (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RME96_WCR_THRU_6 (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RME96_WCR_THRU_7 (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RME96_WCR_DOLBY (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RME96_WCR_MONITOR_0 (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RME96_WCR_MONITOR_1 (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RME96_WCR_ISEL (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RME96_WCR_IDIS (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RME96_WCR_BITPOS_GAIN_0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RME96_WCR_BITPOS_GAIN_1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RME96_WCR_BITPOS_FREQ_0 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RME96_WCR_BITPOS_FREQ_1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RME96_WCR_BITPOS_INP_0 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RME96_WCR_BITPOS_INP_1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RME96_WCR_BITPOS_MONITOR_0 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RME96_WCR_BITPOS_MONITOR_1 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Read control register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RME96_RCR_IRQ_2 (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RME96_RCR_T_OUT (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RME96_RCR_DEV_ID_0 (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RME96_RCR_DEV_ID_1 (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RME96_RCR_LOCK (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RME96_RCR_VERF (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RME96_RCR_F0 (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RME96_RCR_F1 (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RME96_RCR_F2 (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RME96_RCR_AUTOSYNC (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RME96_RCR_IRQ (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RME96_RCR_BITPOS_F0 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RME96_RCR_BITPOS_F1 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RME96_RCR_BITPOS_F2 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Additional register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RME96_AR_WSEL (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RME96_AR_ANALOG (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RME96_AR_FREQPAD_0 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RME96_AR_FREQPAD_1 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define RME96_AR_FREQPAD_2 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RME96_AR_PD2 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RME96_AR_DAC_EN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RME96_AR_CLATCH (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define RME96_AR_CCLK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RME96_AR_CDATA (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RME96_AR_BITPOS_F0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RME96_AR_BITPOS_F1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define RME96_AR_BITPOS_F2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Monitor tracks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define RME96_MONITOR_TRACKS_1_2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define RME96_MONITOR_TRACKS_3_4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define RME96_MONITOR_TRACKS_5_6 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define RME96_MONITOR_TRACKS_7_8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Attenuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define RME96_ATTENUATION_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RME96_ATTENUATION_6 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define RME96_ATTENUATION_12 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define RME96_ATTENUATION_18 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Input types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define RME96_INPUT_OPTICAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define RME96_INPUT_COAXIAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define RME96_INPUT_INTERNAL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define RME96_INPUT_XLR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define RME96_INPUT_ANALOG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Clock modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define RME96_CLOCKMODE_SLAVE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define RME96_CLOCKMODE_MASTER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define RME96_CLOCKMODE_WORDCLOCK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Block sizes in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define RME96_SMALL_BLOCK_SIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RME96_LARGE_BLOCK_SIZE 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define RME96_AD1852_VOL_BITS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define RME96_AD1855_VOL_BITS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Defines for snd_rme96_trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define RME96_TB_START_PLAYBACK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define RME96_TB_START_CAPTURE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define RME96_TB_STOP_PLAYBACK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define RME96_TB_STOP_CAPTURE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define RME96_TB_RESET_PLAYPOS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define RME96_TB_RESET_CAPTUREPOS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define RME96_TB_CLEAR_PLAYBACK_IRQ 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define RME96_TB_CLEAR_CAPTURE_IRQ 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define RME96_RESUME_PLAYBACK (RME96_TB_START_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define RME96_RESUME_CAPTURE (RME96_TB_START_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define RME96_RESUME_BOTH (RME96_RESUME_PLAYBACK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) | RME96_RESUME_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define RME96_START_PLAYBACK (RME96_TB_START_PLAYBACK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) | RME96_TB_RESET_PLAYPOS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define RME96_START_CAPTURE (RME96_TB_START_CAPTURE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) | RME96_TB_RESET_CAPTUREPOS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define RME96_START_BOTH (RME96_START_PLAYBACK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) | RME96_START_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define RME96_STOP_PLAYBACK (RME96_TB_STOP_PLAYBACK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) | RME96_TB_CLEAR_PLAYBACK_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define RME96_STOP_CAPTURE (RME96_TB_STOP_CAPTURE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) | RME96_TB_CLEAR_CAPTURE_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define RME96_STOP_BOTH (RME96_STOP_PLAYBACK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) | RME96_STOP_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct rme96 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned long port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) void __iomem *iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 wcreg; /* cached write control register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 wcreg_spdif; /* S/PDIF setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 rcreg; /* cached read control register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 areg; /* cached additional register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u16 vol[2]; /* cached volume of analog output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u8 rev; /* card revision number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 playback_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 capture_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) void *playback_suspend_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void *capture_suspend_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct snd_pcm_substream *playback_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct snd_pcm_substream *capture_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int playback_frlog; /* log2 of framesize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int capture_frlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) size_t playback_periodsize; /* in bytes, zero if not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) size_t capture_periodsize; /* in bytes, zero if not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct snd_pcm *spdif_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct snd_pcm *adat_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct snd_kcontrol *spdif_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const struct pci_device_id snd_rme96_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static void snd_rme96_proc_init(struct rme96 *rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) snd_rme96_create_switches(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct rme96 *rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) snd_rme96_getinputtype(struct rme96 *rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static inline unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) snd_rme96_playback_ptr(struct rme96 *rme96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static inline unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) snd_rme96_capture_ptr(struct rme96 *rme96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) snd_rme96_playback_silence(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int channel, unsigned long pos, unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct rme96 *rme96 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 0, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) snd_rme96_playback_copy(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int channel, unsigned long pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) void __user *src, unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct rme96 *rme96 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) src, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) snd_rme96_playback_copy_kernel(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int channel, unsigned long pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) void *src, unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct rme96 *rme96 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) snd_rme96_capture_copy(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int channel, unsigned long pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) void __user *dst, unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct rme96 *rme96 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return copy_to_user_fromio(dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) rme96->iobase + RME96_IO_REC_BUFFER + pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) snd_rme96_capture_copy_kernel(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int channel, unsigned long pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) void *dst, unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct rme96 *rme96 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) memcpy_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * Digital output capabilities (S/PDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const struct snd_pcm_hardware snd_rme96_playback_spdif_info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) SNDRV_PCM_INFO_SYNC_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) SNDRV_PCM_INFO_RESUME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) SNDRV_PCM_INFO_PAUSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .formats = (SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) SNDRV_PCM_FMTBIT_S32_LE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .rates = (SNDRV_PCM_RATE_32000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) SNDRV_PCM_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) SNDRV_PCM_RATE_64000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) SNDRV_PCM_RATE_88200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) SNDRV_PCM_RATE_96000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .rate_min = 32000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .buffer_bytes_max = RME96_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * Digital input capabilities (S/PDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const struct snd_pcm_hardware snd_rme96_capture_spdif_info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) SNDRV_PCM_INFO_SYNC_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) SNDRV_PCM_INFO_RESUME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) SNDRV_PCM_INFO_PAUSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .formats = (SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) SNDRV_PCM_FMTBIT_S32_LE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .rates = (SNDRV_PCM_RATE_32000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) SNDRV_PCM_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) SNDRV_PCM_RATE_64000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) SNDRV_PCM_RATE_88200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) SNDRV_PCM_RATE_96000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .rate_min = 32000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .buffer_bytes_max = RME96_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * Digital output capabilities (ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const struct snd_pcm_hardware snd_rme96_playback_adat_info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) SNDRV_PCM_INFO_SYNC_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) SNDRV_PCM_INFO_RESUME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) SNDRV_PCM_INFO_PAUSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .formats = (SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) SNDRV_PCM_FMTBIT_S32_LE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .rates = (SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) SNDRV_PCM_RATE_48000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .rate_min = 44100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .channels_min = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .buffer_bytes_max = RME96_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * Digital input capabilities (ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const struct snd_pcm_hardware snd_rme96_capture_adat_info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) SNDRV_PCM_INFO_SYNC_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) SNDRV_PCM_INFO_RESUME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) SNDRV_PCM_INFO_PAUSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .formats = (SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) SNDRV_PCM_FMTBIT_S32_LE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .rates = (SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) SNDRV_PCM_RATE_48000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .rate_min = 44100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .channels_min = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .buffer_bytes_max = RME96_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * on the falling edge of CCLK and be stable on the rising edge. The rising
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * edge of CLATCH after the last data bit clocks in the whole data word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * A fast processor could probably drive the SPI interface faster than the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * NOTE: increased delay from 1 to 10, since there where problems setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * the volume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (val & 0x8000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) rme96->areg |= RME96_AR_CDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) rme96->areg &= ~RME96_AR_CDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) rme96->areg |= RME96_AR_CCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) val <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) rme96->areg |= RME96_AR_CLATCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) rme96->areg &= ~RME96_AR_CLATCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) snd_rme96_apply_dac_volume(struct rme96 *rme96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (RME96_DAC_IS_1852(rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) } else if (RME96_DAC_IS_1855(rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) snd_rme96_reset_dac(struct rme96 *rme96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) writel(rme96->wcreg | RME96_WCR_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) snd_rme96_getmontracks(struct rme96 *rme96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) snd_rme96_setmontracks(struct rme96 *rme96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int montracks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (montracks & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) rme96->wcreg |= RME96_WCR_MONITOR_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) rme96->wcreg &= ~RME96_WCR_MONITOR_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (montracks & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) rme96->wcreg |= RME96_WCR_MONITOR_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) rme96->wcreg &= ~RME96_WCR_MONITOR_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) snd_rme96_getattenuation(struct rme96 *rme96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) snd_rme96_setattenuation(struct rme96 *rme96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int attenuation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) switch (attenuation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ~RME96_WCR_GAIN_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ~RME96_WCR_GAIN_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) RME96_WCR_GAIN_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) RME96_WCR_GAIN_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) snd_rme96_capture_getrate(struct rme96 *rme96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) int *is_adat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int n, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) *is_adat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (rme96->areg & RME96_AR_ANALOG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* Analog input, overrides S/PDIF setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) switch (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) rate = 32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) rate = 44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) rate = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (rme96->rcreg & RME96_RCR_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* ADAT rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) *is_adat = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (rme96->rcreg & RME96_RCR_T_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return 44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (rme96->rcreg & RME96_RCR_VERF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* S/PDIF rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) switch (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (rme96->rcreg & RME96_RCR_T_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return 64000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) case 3: return 96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) case 4: return 88200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) case 5: return 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) case 6: return 44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) case 7: return 32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) snd_rme96_playback_getrate(struct rme96 *rme96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) int rate, dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (!(rme96->wcreg & RME96_WCR_MASTER) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* slave clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) rate = 32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) rate = 44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) rate = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) snd_rme96_playback_setrate(struct rme96 *rme96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) int ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ds = rme96->wcreg & RME96_WCR_DS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) rme96->wcreg &= ~RME96_WCR_DS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ~RME96_WCR_FREQ_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) rme96->wcreg &= ~RME96_WCR_DS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ~RME96_WCR_FREQ_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) rme96->wcreg &= ~RME96_WCR_DS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) RME96_WCR_FREQ_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case 64000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) rme96->wcreg |= RME96_WCR_DS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ~RME96_WCR_FREQ_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) rme96->wcreg |= RME96_WCR_DS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ~RME96_WCR_FREQ_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) rme96->wcreg |= RME96_WCR_DS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) RME96_WCR_FREQ_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) (ds && !(rme96->wcreg & RME96_WCR_DS)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* change to/from double-speed: reset the DAC (if available) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) snd_rme96_reset_dac(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return 1; /* need to restore volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) snd_rme96_capture_analog_setrate(struct rme96 *rme96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) case 64000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (rme96->rev < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (rme96->rev < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) snd_rme96_setclockmode(struct rme96 *rme96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) case RME96_CLOCKMODE_SLAVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* AutoSync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) rme96->wcreg &= ~RME96_WCR_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) rme96->areg &= ~RME96_AR_WSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) case RME96_CLOCKMODE_MASTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) rme96->wcreg |= RME96_WCR_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) rme96->areg &= ~RME96_AR_WSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) case RME96_CLOCKMODE_WORDCLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* Word clock is a master mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) rme96->wcreg |= RME96_WCR_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) rme96->areg |= RME96_AR_WSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) snd_rme96_getclockmode(struct rme96 *rme96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (rme96->areg & RME96_AR_WSEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return RME96_CLOCKMODE_WORDCLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) RME96_CLOCKMODE_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) snd_rme96_setinputtype(struct rme96 *rme96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) case RME96_INPUT_OPTICAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) ~RME96_WCR_INP_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) case RME96_INPUT_COAXIAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ~RME96_WCR_INP_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) case RME96_INPUT_INTERNAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) RME96_WCR_INP_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) case RME96_INPUT_XLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) rme96->rev > 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) RME96_WCR_INP_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) case RME96_INPUT_ANALOG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (!RME96_HAS_ANALOG_IN(rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) rme96->areg |= RME96_AR_ANALOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (rme96->rev < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * Revision less than 004 does not support 64 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * 88.2 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) snd_rme96_capture_analog_setrate(rme96, 44100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) snd_rme96_capture_analog_setrate(rme96, 32000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) rme96->areg &= ~RME96_AR_ANALOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) snd_rme96_getinputtype(struct rme96 *rme96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (rme96->areg & RME96_AR_ANALOG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return RME96_INPUT_ANALOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) snd_rme96_setframelog(struct rme96 *rme96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) int n_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) int is_playback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) int frlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (n_channels == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) frlog = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* assume 8 channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) frlog = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (is_playback) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) rme96->playback_frlog = frlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) rme96->capture_frlog = frlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) snd_rme96_playback_setformat(struct rme96 *rme96, snd_pcm_format_t format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) switch (format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) rme96->wcreg &= ~RME96_WCR_MODE24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) case SNDRV_PCM_FORMAT_S32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) rme96->wcreg |= RME96_WCR_MODE24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) snd_rme96_capture_setformat(struct rme96 *rme96, snd_pcm_format_t format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) switch (format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) rme96->wcreg &= ~RME96_WCR_MODE24_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) case SNDRV_PCM_FORMAT_S32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) rme96->wcreg |= RME96_WCR_MODE24_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) snd_rme96_set_period_properties(struct rme96 *rme96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) size_t period_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) switch (period_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) case RME96_LARGE_BLOCK_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) rme96->wcreg &= ~RME96_WCR_ISEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) case RME96_SMALL_BLOCK_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) rme96->wcreg |= RME96_WCR_ISEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) rme96->wcreg &= ~RME96_WCR_IDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct rme96 *rme96 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) int err, rate, dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) bool apply_dac_volume = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) runtime->dma_area = (void __force *)(rme96->iobase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) RME96_IO_PLAY_BUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) runtime->dma_bytes = RME96_BUFFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (!(rme96->wcreg & RME96_WCR_MASTER) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /* slave clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if ((int)params_rate(params) != rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) err = snd_rme96_playback_setrate(rme96, params_rate(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) apply_dac_volume = err > 0; /* need to restore volume later? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) err = snd_rme96_playback_setformat(rme96, params_format(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) snd_rme96_setframelog(rme96, params_channels(params), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (rme96->capture_periodsize != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (params_period_size(params) << rme96->playback_frlog !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) rme96->capture_periodsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) rme96->playback_periodsize =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) params_period_size(params) << rme96->playback_frlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* S/PDIF setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (apply_dac_volume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) usleep_range(3000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) snd_rme96_apply_dac_volume(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct rme96 *rme96 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) int err, isadat, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) runtime->dma_area = (void __force *)(rme96->iobase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) RME96_IO_REC_BUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) runtime->dma_bytes = RME96_BUFFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if ((err = snd_rme96_capture_analog_setrate(rme96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) params_rate(params))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if ((int)params_rate(params) != rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if ((isadat && runtime->hw.channels_min == 2) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) (!isadat && runtime->hw.channels_min == 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) snd_rme96_setframelog(rme96, params_channels(params), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (rme96->playback_periodsize != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (params_period_size(params) << rme96->capture_frlog !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) rme96->playback_periodsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) rme96->capture_periodsize =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) params_period_size(params) << rme96->capture_frlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) snd_rme96_trigger(struct rme96 *rme96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) int op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (op & RME96_TB_RESET_PLAYPOS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (op & RME96_TB_RESET_CAPTUREPOS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (op & RME96_TB_CLEAR_PLAYBACK_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (rme96->rcreg & RME96_RCR_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (op & RME96_TB_CLEAR_CAPTURE_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (rme96->rcreg & RME96_RCR_IRQ_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (op & RME96_TB_START_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) rme96->wcreg |= RME96_WCR_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (op & RME96_TB_STOP_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) rme96->wcreg &= ~RME96_WCR_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (op & RME96_TB_START_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) rme96->wcreg |= RME96_WCR_START_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (op & RME96_TB_STOP_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) rme96->wcreg &= ~RME96_WCR_START_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) snd_rme96_interrupt(int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) struct rme96 *rme96 = (struct rme96 *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* fastpath out, to ease interrupt sharing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (!((rme96->rcreg & RME96_RCR_IRQ) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) (rme96->rcreg & RME96_RCR_IRQ_2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if (rme96->rcreg & RME96_RCR_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /* playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) snd_pcm_period_elapsed(rme96->playback_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (rme96->rcreg & RME96_RCR_IRQ_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /* capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) snd_pcm_period_elapsed(rme96->capture_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static const unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .count = ARRAY_SIZE(period_bytes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .list = period_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .mask = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) rme96_set_buffer_size_constraint(struct rme96 *rme96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) struct snd_pcm_runtime *runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) snd_pcm_hw_constraint_single(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) RME96_BUFFER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if ((size = rme96->playback_periodsize) != 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) (size = rme96->capture_periodsize) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) snd_pcm_hw_constraint_single(runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) snd_pcm_hw_constraint_list(runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) &hw_constraints_period_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) int rate, dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) struct rme96 *rme96 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (rme96->playback_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) rme96->wcreg &= ~RME96_WCR_ADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) rme96->playback_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) runtime->hw = snd_rme96_playback_spdif_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (!(rme96->wcreg & RME96_WCR_MASTER) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) /* slave clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) runtime->hw.rate_min = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) runtime->hw.rate_max = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) rme96_set_buffer_size_constraint(rme96, runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) int isadat, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct rme96 *rme96 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) runtime->hw = snd_rme96_capture_spdif_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (isadat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) runtime->hw.rate_min = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) runtime->hw.rate_max = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (rme96->capture_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) rme96->capture_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) rme96_set_buffer_size_constraint(rme96, runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) int rate, dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) struct rme96 *rme96 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (rme96->playback_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) rme96->wcreg |= RME96_WCR_ADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) rme96->playback_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) runtime->hw = snd_rme96_playback_adat_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (!(rme96->wcreg & RME96_WCR_MASTER) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) /* slave clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) runtime->hw.rate_min = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) runtime->hw.rate_max = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) rme96_set_buffer_size_constraint(rme96, runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) int isadat, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) struct rme96 *rme96 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) runtime->hw = snd_rme96_capture_adat_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /* makes no sense to use analog input. Note that analog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (!isadat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) runtime->hw.rate_min = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) runtime->hw.rate_max = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (rme96->capture_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) rme96->capture_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) rme96_set_buffer_size_constraint(rme96, runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) snd_rme96_playback_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) struct rme96 *rme96 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) int spdif = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (RME96_ISPLAYING(rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) rme96->playback_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) rme96->playback_periodsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (spdif) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) snd_rme96_capture_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) struct rme96 *rme96 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (RME96_ISRECORDING(rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) rme96->capture_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) rme96->capture_periodsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) struct rme96 *rme96 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (RME96_ISPLAYING(rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) struct rme96 *rme96 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (RME96_ISRECORDING(rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) struct rme96 *rme96 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) struct snd_pcm_substream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) bool sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) snd_pcm_group_for_each_entry(s, substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (snd_pcm_substream_chip(s) == rme96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) snd_pcm_trigger_done(s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) sync = (rme96->playback_substream && rme96->capture_substream) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) (rme96->playback_substream->group ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) rme96->capture_substream->group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (!RME96_ISPLAYING(rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (substream != rme96->playback_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) : RME96_START_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (RME96_ISPLAYING(rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (substream != rme96->playback_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) : RME96_STOP_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (RME96_ISPLAYING(rme96))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) : RME96_STOP_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (!RME96_ISPLAYING(rme96))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) : RME96_RESUME_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) struct rme96 *rme96 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) struct snd_pcm_substream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) bool sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) snd_pcm_group_for_each_entry(s, substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (snd_pcm_substream_chip(s) == rme96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) snd_pcm_trigger_done(s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) sync = (rme96->playback_substream && rme96->capture_substream) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) (rme96->playback_substream->group ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) rme96->capture_substream->group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (!RME96_ISRECORDING(rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (substream != rme96->capture_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) : RME96_START_CAPTURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (RME96_ISRECORDING(rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (substream != rme96->capture_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) : RME96_STOP_CAPTURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if (RME96_ISRECORDING(rme96))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) : RME96_STOP_CAPTURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (!RME96_ISRECORDING(rme96))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) : RME96_RESUME_CAPTURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) struct rme96 *rme96 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) return snd_rme96_playback_ptr(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) struct rme96 *rme96 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) return snd_rme96_capture_ptr(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static const struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .open = snd_rme96_playback_spdif_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .close = snd_rme96_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .hw_params = snd_rme96_playback_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .prepare = snd_rme96_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .trigger = snd_rme96_playback_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .pointer = snd_rme96_playback_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .copy_user = snd_rme96_playback_copy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .copy_kernel = snd_rme96_playback_copy_kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .fill_silence = snd_rme96_playback_silence,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .mmap = snd_pcm_lib_mmap_iomem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static const struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .open = snd_rme96_capture_spdif_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .close = snd_rme96_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .hw_params = snd_rme96_capture_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .prepare = snd_rme96_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .trigger = snd_rme96_capture_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .pointer = snd_rme96_capture_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .copy_user = snd_rme96_capture_copy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .copy_kernel = snd_rme96_capture_copy_kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .mmap = snd_pcm_lib_mmap_iomem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) static const struct snd_pcm_ops snd_rme96_playback_adat_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .open = snd_rme96_playback_adat_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .close = snd_rme96_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .hw_params = snd_rme96_playback_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .prepare = snd_rme96_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .trigger = snd_rme96_playback_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .pointer = snd_rme96_playback_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .copy_user = snd_rme96_playback_copy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .copy_kernel = snd_rme96_playback_copy_kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .fill_silence = snd_rme96_playback_silence,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .mmap = snd_pcm_lib_mmap_iomem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) static const struct snd_pcm_ops snd_rme96_capture_adat_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .open = snd_rme96_capture_adat_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .close = snd_rme96_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .hw_params = snd_rme96_capture_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .prepare = snd_rme96_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .trigger = snd_rme96_capture_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .pointer = snd_rme96_capture_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .copy_user = snd_rme96_capture_copy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .copy_kernel = snd_rme96_capture_copy_kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .mmap = snd_pcm_lib_mmap_iomem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) snd_rme96_free(void *private_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) struct rme96 *rme96 = (struct rme96 *)private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (!rme96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (rme96->irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) snd_rme96_trigger(rme96, RME96_STOP_BOTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) rme96->areg &= ~RME96_AR_DAC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) free_irq(rme96->irq, (void *)rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) rme96->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) if (rme96->iobase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) iounmap(rme96->iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) rme96->iobase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (rme96->port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) pci_release_regions(rme96->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) rme96->port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) vfree(rme96->playback_suspend_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) vfree(rme96->capture_suspend_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) pci_disable_device(rme96->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) struct rme96 *rme96 = pcm->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) rme96->spdif_pcm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) struct rme96 *rme96 = pcm->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) rme96->adat_pcm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) snd_rme96_create(struct rme96 *rme96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) struct pci_dev *pci = rme96->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) rme96->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) spin_lock_init(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if ((err = pci_enable_device(pci)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) if ((err = pci_request_regions(pci, "RME96")) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) rme96->port = pci_resource_start(rme96->pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) rme96->iobase = ioremap(rme96->port, RME96_IO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (!rme96->iobase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) dev_err(rme96->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) "unable to remap memory region 0x%lx-0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) rme96->port, rme96->port + RME96_IO_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) KBUILD_MODNAME, rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) dev_err(rme96->card->dev, "unable to grab IRQ %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) rme96->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) rme96->card->sync_irq = rme96->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) /* read the card's revision number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) pci_read_config_byte(pci, 8, &rme96->rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) /* set up ALSA pcm device for S/PDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) 1, 1, &rme96->spdif_pcm)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) rme96->spdif_pcm->private_data = rme96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) rme96->spdif_pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) /* set up ALSA pcm device for ADAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) /* ADAT is not available on the base model */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) rme96->adat_pcm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) 1, 1, &rme96->adat_pcm)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) rme96->adat_pcm->private_data = rme96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) rme96->adat_pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) rme96->playback_periodsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) rme96->capture_periodsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) /* make sure playback/capture is stopped, if by some reason active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) snd_rme96_trigger(rme96, RME96_STOP_BOTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) /* set default values in registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) rme96->wcreg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) RME96_WCR_SEL | /* normal playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) RME96_WCR_MASTER | /* set to master clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) RME96_WCR_INP_0; /* set coaxial input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) /* reset the ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) writel(rme96->areg | RME96_AR_PD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) rme96->iobase + RME96_IO_ADDITIONAL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) /* reset and enable the DAC (order is important). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) snd_rme96_reset_dac(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) rme96->areg |= RME96_AR_DAC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) /* reset playback and record buffer pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) /* reset volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) rme96->vol[0] = rme96->vol[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) if (RME96_HAS_ANALOG_OUT(rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) snd_rme96_apply_dac_volume(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) /* init switch interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) /* init proc interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) snd_rme96_proc_init(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) * proc interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) struct rme96 *rme96 = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) snd_iprintf(buffer, rme96->card->longname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) snd_iprintf(buffer, "\nGeneral settings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) if (rme96->wcreg & RME96_WCR_IDIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) snd_iprintf(buffer, " period size: N/A (interrupts "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) "disabled)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) } else if (rme96->wcreg & RME96_WCR_ISEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) snd_iprintf(buffer, " period size: 2048 bytes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) snd_iprintf(buffer, " period size: 8192 bytes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) snd_iprintf(buffer, "\nInput settings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) switch (snd_rme96_getinputtype(rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) case RME96_INPUT_OPTICAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) snd_iprintf(buffer, " input: optical");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) case RME96_INPUT_COAXIAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) snd_iprintf(buffer, " input: coaxial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) case RME96_INPUT_INTERNAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) snd_iprintf(buffer, " input: internal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) case RME96_INPUT_XLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) snd_iprintf(buffer, " input: XLR");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) case RME96_INPUT_ANALOG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) snd_iprintf(buffer, " input: analog");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) if (snd_rme96_capture_getrate(rme96, &n) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) snd_iprintf(buffer, "\n sample rate: no valid signal\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) if (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) snd_iprintf(buffer, " (8 channels)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) snd_iprintf(buffer, " (2 channels)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) snd_iprintf(buffer, " sample rate: %d Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) snd_rme96_capture_getrate(rme96, &n));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) if (rme96->wcreg & RME96_WCR_MODE24_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) snd_iprintf(buffer, " sample format: 24 bit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) snd_iprintf(buffer, " sample format: 16 bit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) snd_iprintf(buffer, "\nOutput settings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) if (rme96->wcreg & RME96_WCR_SEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) snd_iprintf(buffer, " output signal: normal playback\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) snd_iprintf(buffer, " output signal: same as input\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) snd_iprintf(buffer, " sample rate: %d Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) snd_rme96_playback_getrate(rme96));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) if (rme96->wcreg & RME96_WCR_MODE24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) snd_iprintf(buffer, " sample format: 24 bit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) snd_iprintf(buffer, " sample format: 16 bit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) if (rme96->areg & RME96_AR_WSEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) snd_iprintf(buffer, " sample clock source: word clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) } else if (rme96->wcreg & RME96_WCR_MASTER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) snd_iprintf(buffer, " sample clock source: internal\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) snd_iprintf(buffer, " sample clock source: autosync\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) if (rme96->wcreg & RME96_WCR_PRO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) snd_iprintf(buffer, " format: AES/EBU (professional)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) snd_iprintf(buffer, " format: IEC958 (consumer)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) if (rme96->wcreg & RME96_WCR_EMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) snd_iprintf(buffer, " emphasis: on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) snd_iprintf(buffer, " emphasis: off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) if (rme96->wcreg & RME96_WCR_DOLBY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) snd_iprintf(buffer, " non-audio (dolby): on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) snd_iprintf(buffer, " non-audio (dolby): off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) if (RME96_HAS_ANALOG_IN(rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) snd_iprintf(buffer, "\nAnalog output settings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) switch (snd_rme96_getmontracks(rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) case RME96_MONITOR_TRACKS_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) case RME96_MONITOR_TRACKS_3_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) case RME96_MONITOR_TRACKS_5_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) case RME96_MONITOR_TRACKS_7_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) switch (snd_rme96_getattenuation(rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) case RME96_ATTENUATION_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) snd_iprintf(buffer, " attenuation: 0 dB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) case RME96_ATTENUATION_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) snd_iprintf(buffer, " attenuation: -6 dB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) case RME96_ATTENUATION_12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) snd_iprintf(buffer, " attenuation: -12 dB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) case RME96_ATTENUATION_18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) snd_iprintf(buffer, " attenuation: -18 dB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) static void snd_rme96_proc_init(struct rme96 *rme96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) snd_card_ro_proc_new(rme96->card, "rme96", rme96, snd_rme96_proc_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) * control interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) #define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) change = val != rme96->wcreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) rme96->wcreg = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) static const char * const _texts[5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) "Optical", "Coaxial", "Internal", "XLR", "Analog"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) const char *texts[5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) _texts[0], _texts[1], _texts[2], _texts[3], _texts[4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) int num_items;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) switch (rme96->pci->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) case PCI_DEVICE_ID_RME_DIGI96:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) case PCI_DEVICE_ID_RME_DIGI96_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) num_items = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) num_items = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) if (rme96->rev > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) /* PST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) num_items = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) texts[3] = _texts[4]; /* Analog instead of XLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) /* PAD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) num_items = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) return snd_ctl_enum_info(uinfo, 1, num_items, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) unsigned int items = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) switch (rme96->pci->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) case PCI_DEVICE_ID_RME_DIGI96:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) case PCI_DEVICE_ID_RME_DIGI96_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) items = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) items = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) if (rme96->rev > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) items = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) items = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) if (ucontrol->value.enumerated.item[0] >= items) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) ucontrol->value.enumerated.item[0] = items - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) int change, items = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) switch (rme96->pci->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) case PCI_DEVICE_ID_RME_DIGI96:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) case PCI_DEVICE_ID_RME_DIGI96_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) items = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) items = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) if (rme96->rev > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) items = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) items = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) val = ucontrol->value.enumerated.item[0] % items;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) /* special case for PST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) if (val == RME96_INPUT_XLR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) val = RME96_INPUT_ANALOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) change = (int)val != snd_rme96_getinputtype(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) snd_rme96_setinputtype(rme96, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) static const char * const texts[3] = { "AutoSync", "Internal", "Word" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) return snd_ctl_enum_info(uinfo, 1, 3, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) val = ucontrol->value.enumerated.item[0] % 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) change = (int)val != snd_rme96_getclockmode(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) snd_rme96_setclockmode(rme96, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) static const char * const texts[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) "0 dB", "-6 dB", "-12 dB", "-18 dB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) return snd_ctl_enum_info(uinfo, 1, 4, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) val = ucontrol->value.enumerated.item[0] % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) change = (int)val != snd_rme96_getattenuation(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) snd_rme96_setattenuation(rme96, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) static const char * const texts[4] = { "1+2", "3+4", "5+6", "7+8" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) return snd_ctl_enum_info(uinfo, 1, 4, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) val = ucontrol->value.enumerated.item[0] % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) change = (int)val != snd_rme96_getmontracks(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) snd_rme96_setmontracks(rme96, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) if (val & RME96_WCR_PRO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) if (val & RME96_WCR_PRO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) change = val != rme96->wcreg_spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) rme96->wcreg_spdif = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) change = val != rme96->wcreg_spdif_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) rme96->wcreg_spdif_stream = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) rme96->wcreg |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) ucontrol->value.iec958.status[0] = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) uinfo->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) u->value.integer.value[0] = rme96->vol[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) u->value.integer.value[1] = rme96->vol[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) int change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) unsigned int vol, maxvol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) if (!RME96_HAS_ANALOG_OUT(rme96))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) maxvol = RME96_185X_MAX_OUT(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) spin_lock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) vol = u->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) if (vol != rme96->vol[0] && vol <= maxvol) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) rme96->vol[0] = vol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) vol = u->value.integer.value[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) if (vol != rme96->vol[1] && vol <= maxvol) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) rme96->vol[1] = vol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) if (change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) snd_rme96_apply_dac_volume(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) spin_unlock_irq(&rme96->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) static const struct snd_kcontrol_new snd_rme96_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .info = snd_rme96_control_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .get = snd_rme96_control_spdif_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .put = snd_rme96_control_spdif_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .info = snd_rme96_control_spdif_stream_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .get = snd_rme96_control_spdif_stream_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .put = snd_rme96_control_spdif_stream_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .info = snd_rme96_control_spdif_mask_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) .get = snd_rme96_control_spdif_mask_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) .private_value = IEC958_AES0_NONAUDIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) IEC958_AES0_PROFESSIONAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) IEC958_AES0_CON_EMPHASIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .info = snd_rme96_control_spdif_mask_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .get = snd_rme96_control_spdif_mask_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .private_value = IEC958_AES0_NONAUDIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) IEC958_AES0_PROFESSIONAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) IEC958_AES0_PRO_EMPHASIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .name = "Input Connector",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .info = snd_rme96_info_inputtype_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .get = snd_rme96_get_inputtype_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .put = snd_rme96_put_inputtype_control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .name = "Loopback Input",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .info = snd_rme96_info_loopback_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .get = snd_rme96_get_loopback_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .put = snd_rme96_put_loopback_control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .name = "Sample Clock Source",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .info = snd_rme96_info_clockmode_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .get = snd_rme96_get_clockmode_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .put = snd_rme96_put_clockmode_control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .name = "Monitor Tracks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .info = snd_rme96_info_montracks_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .get = snd_rme96_get_montracks_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .put = snd_rme96_put_montracks_control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .name = "Attenuation",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .info = snd_rme96_info_attenuation_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .get = snd_rme96_get_attenuation_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .put = snd_rme96_put_attenuation_control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .name = "DAC Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .info = snd_rme96_dac_volume_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .get = snd_rme96_dac_volume_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .put = snd_rme96_dac_volume_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) snd_rme96_create_switches(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) struct rme96 *rme96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) int idx, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) for (idx = 0; idx < 7; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) if (idx == 1) /* IEC958 (S/PDIF) Stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) rme96->spdif_ctl = kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) if (RME96_HAS_ANALOG_OUT(rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) for (idx = 7; idx < 10; idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) * Card initialisation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) static int rme96_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) struct rme96 *rme96 = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) /* save capture & playback pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) rme96->playback_pointer = readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) & RME96_RCR_AUDIO_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) rme96->capture_pointer = readl(rme96->iobase + RME96_IO_GET_REC_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) & RME96_RCR_AUDIO_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) /* save playback and capture buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) memcpy_fromio(rme96->playback_suspend_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) rme96->iobase + RME96_IO_PLAY_BUFFER, RME96_BUFFER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) memcpy_fromio(rme96->capture_suspend_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) rme96->iobase + RME96_IO_REC_BUFFER, RME96_BUFFER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) /* disable the DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) rme96->areg &= ~RME96_AR_DAC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) static int rme96_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) struct rme96 *rme96 = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) /* reset playback and record buffer pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) writel(0, rme96->iobase + RME96_IO_SET_PLAY_POS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) + rme96->playback_pointer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) writel(0, rme96->iobase + RME96_IO_SET_REC_POS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) + rme96->capture_pointer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) /* restore playback and capture buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) rme96->playback_suspend_buffer, RME96_BUFFER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) memcpy_toio(rme96->iobase + RME96_IO_REC_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) rme96->capture_suspend_buffer, RME96_BUFFER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) /* reset the ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) writel(rme96->areg | RME96_AR_PD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) rme96->iobase + RME96_IO_ADDITIONAL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) /* reset and enable DAC, restore analog volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) snd_rme96_reset_dac(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) rme96->areg |= RME96_AR_DAC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) if (RME96_HAS_ANALOG_OUT(rme96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) usleep_range(3000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) snd_rme96_apply_dac_volume(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) static SIMPLE_DEV_PM_OPS(rme96_pm, rme96_suspend, rme96_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) #define RME96_PM_OPS &rme96_pm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) #define RME96_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) static void snd_rme96_card_free(struct snd_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) snd_rme96_free(card->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) snd_rme96_probe(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) struct rme96 *rme96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) if (dev >= SNDRV_CARDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) if (!enable[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) sizeof(struct rme96), &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) card->private_free = snd_rme96_card_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) rme96 = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) rme96->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) rme96->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) err = snd_rme96_create(rme96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) goto free_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) rme96->playback_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) if (!rme96->playback_suspend_buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) goto free_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) rme96->capture_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) if (!rme96->capture_suspend_buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) goto free_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) strcpy(card->driver, "Digi96");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) switch (rme96->pci->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) case PCI_DEVICE_ID_RME_DIGI96:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) strcpy(card->shortname, "RME Digi96");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) case PCI_DEVICE_ID_RME_DIGI96_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) strcpy(card->shortname, "RME Digi96/8");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) strcpy(card->shortname, "RME Digi96/8 PRO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) pci_read_config_byte(rme96->pci, 8, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) if (val < 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) strcpy(card->shortname, "RME Digi96/8 PAD");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) strcpy(card->shortname, "RME Digi96/8 PST");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) rme96->port, rme96->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) err = snd_card_register(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) goto free_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) free_card:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) static void snd_rme96_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) snd_card_free(pci_get_drvdata(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) static struct pci_driver rme96_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .id_table = snd_rme96_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .probe = snd_rme96_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .remove = snd_rme96_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) .pm = RME96_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) module_pci_driver(rme96_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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