^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Pilo Chambert <pilo.c@wanadoo.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Thanks to : Anders Torger <torger@ludd.luth.se>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Henk Hesselink <henk@anda.nl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * for writing the digi96-driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * and RME for all informations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * ****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Note #1 "Sek'd models" ................................... martin 2002-12-07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Identical soundcards by Sek'd were labeled:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * RME Digi 32 = Sek'd Prodif 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * RME Digi 32 Pro = Sek'd Prodif 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * RME Digi 32/8 = Sek'd Prodif Gold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * ****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Note #2 "full duplex mode" ............................... martin 2002-12-07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * in this mode. Rec data and play data are using the same buffer therefore. At
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * first you have got the playing bits in the buffer and then (after playing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * them) they were overwitten by the captured sound of the CS8412/14. Both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * modes (play/record) are running harmonically hand in hand in the same buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * and you have only one start bit plus one interrupt bit to control this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * paired action.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * This is opposite to the latter rme96 where playing and capturing is totally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * separated and so their full duplex mode is supported by alsa (using two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * start bits and two interrupts for two different buffers).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * But due to the wrong sequence of playing and capturing ALSA shows no solved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * full duplex support for the rme32 at the moment. That's bad, but I'm not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * able to solve it. Are you motivated enough to solve this problem now? Your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * patch would be welcome!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * ****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * "The story after the long seeking" -- tiwai
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Ok, the situation regarding the full duplex is now improved a bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * In the fullduplex mode (given by the module parameter), the hardware buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * is split to halves for read and write directions at the DMA pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * That is, the half above the current DMA pointer is used for write, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * the half below is used for read. To mangle this strange behavior, an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * software intermediate buffer is introduced. This is, of course, not good
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * from the viewpoint of the data transfer efficiency. However, this allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * ****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <sound/pcm-indirect.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include <sound/asoundef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static bool fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) module_param_array(fullduplex, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MODULE_PARM_DESC(fullduplex, "Support full-duplex mode.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MODULE_SUPPORTED_DEVICE("{{RME,Digi32}," "{RME,Digi32/8}," "{RME,Digi32 PRO}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Defines for RME Digi32 series */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RME32_SPDIF_NCHANNELS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Playback and capture buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RME32_BUFFER_SIZE 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* IO area size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RME32_IO_SIZE 0x30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* IO area offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RME32_IO_DATA_BUFFER 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RME32_IO_CONTROL_REGISTER 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RME32_IO_GET_POS 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RME32_IO_CONFIRM_ACTION_IRQ 0x20004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RME32_IO_RESET_POS 0x20100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Write control register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RME32_WCR_START (1 << 0) /* startbit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) Setting the whole card to mono
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) doesn't seem to be very useful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) A software-solution can handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) full-duplex with one direction in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) stereo and the other way in mono.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) So, the hardware should work all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) the time in stereo! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RME32_WCR_FREQ_1 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RME32_WCR_INP_0 (1 << 6) /* input switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RME32_WCR_INP_1 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RME32_WCR_RESET (1 << 8) /* Reset address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RME32_WCR_MUTE (1 << 9) /* digital mute for output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RME32_WCR_BITPOS_FREQ_0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RME32_WCR_BITPOS_FREQ_1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RME32_WCR_BITPOS_INP_0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RME32_WCR_BITPOS_INP_1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Read control register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define RME32_RCR_FREQ_1 (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RME32_RCR_FREQ_2 (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RME32_RCR_IRQ (1 << 31) /* interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RME32_RCR_BITPOS_F0 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define RME32_RCR_BITPOS_F1 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RME32_RCR_BITPOS_F2 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Input types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define RME32_INPUT_OPTICAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define RME32_INPUT_COAXIAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define RME32_INPUT_INTERNAL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define RME32_INPUT_XLR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Clock modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define RME32_CLOCKMODE_SLAVE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define RME32_CLOCKMODE_MASTER_32 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define RME32_CLOCKMODE_MASTER_44 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RME32_CLOCKMODE_MASTER_48 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Block sizes in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define RME32_BLOCK_SIZE 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Software intermediate buffer (max) size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define RME32_MID_BUFFER_SIZE (1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Hardware revisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define RME32_32_REVISION 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define RME32_328_REVISION_OLD 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define RME32_328_REVISION_NEW 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define RME32_PRO_REVISION_WITH_8412 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define RME32_PRO_REVISION_WITH_8414 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct rme32 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned long port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) void __iomem *iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 wcreg; /* cached write control register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 wcreg_spdif; /* S/PDIF setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 rcreg; /* cached read control register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u8 rev; /* card revision number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct snd_pcm_substream *playback_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct snd_pcm_substream *capture_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int playback_frlog; /* log2 of framesize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int capture_frlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) size_t playback_periodsize; /* in bytes, zero if not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) size_t capture_periodsize; /* in bytes, zero if not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned int fullduplex_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct snd_pcm_indirect playback_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct snd_pcm_indirect capture_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct snd_pcm *spdif_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct snd_pcm *adat_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct snd_kcontrol *spdif_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const struct pci_device_id snd_rme32_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32), 0,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8), 0,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO), 0,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MODULE_DEVICE_TABLE(pci, snd_rme32_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static void snd_rme32_proc_init(struct rme32 * rme32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return (readl(rme32->iobase + RME32_IO_GET_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) & RME32_RCR_AUDIO_ADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* silence callback for halfduplex mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int snd_rme32_playback_silence(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int channel, unsigned long pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* copy callback for halfduplex mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int snd_rme32_playback_copy(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int channel, unsigned long pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) void __user *src, unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) src, count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int snd_rme32_playback_copy_kernel(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int channel, unsigned long pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) void *src, unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos, src, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* copy callback for halfduplex mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int snd_rme32_capture_copy(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int channel, unsigned long pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) void __user *dst, unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (copy_to_user_fromio(dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) rme32->iobase + RME32_IO_DATA_BUFFER + pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int snd_rme32_capture_copy_kernel(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int channel, unsigned long pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) void *dst, unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) memcpy_fromio(dst, rme32->iobase + RME32_IO_DATA_BUFFER + pos, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * SPDIF I/O capabilities (half-duplex mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const struct snd_pcm_hardware snd_rme32_spdif_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) SNDRV_PCM_INFO_SYNC_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) SNDRV_PCM_INFO_SYNC_APPLPTR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .formats = (SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) SNDRV_PCM_FMTBIT_S32_LE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .rates = (SNDRV_PCM_RATE_32000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) SNDRV_PCM_RATE_48000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .rate_min = 32000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .buffer_bytes_max = RME32_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .period_bytes_min = RME32_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .period_bytes_max = RME32_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * ADAT I/O capabilities (half-duplex mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const struct snd_pcm_hardware snd_rme32_adat_info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) SNDRV_PCM_INFO_SYNC_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) SNDRV_PCM_INFO_SYNC_APPLPTR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .formats= SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .rates = (SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) SNDRV_PCM_RATE_48000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .rate_min = 44100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .channels_min = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .buffer_bytes_max = RME32_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .period_bytes_min = RME32_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .period_bytes_max = RME32_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * SPDIF I/O capabilities (full-duplex mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const struct snd_pcm_hardware snd_rme32_spdif_fd_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .info = (SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) SNDRV_PCM_INFO_SYNC_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) SNDRV_PCM_INFO_SYNC_APPLPTR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .formats = (SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) SNDRV_PCM_FMTBIT_S32_LE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .rates = (SNDRV_PCM_RATE_32000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) SNDRV_PCM_RATE_48000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .rate_min = 32000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .period_bytes_min = RME32_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .period_bytes_max = RME32_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * ADAT I/O capabilities (full-duplex mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const struct snd_pcm_hardware snd_rme32_adat_fd_info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .info = (SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) SNDRV_PCM_INFO_SYNC_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) SNDRV_PCM_INFO_SYNC_APPLPTR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .formats= SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .rates = (SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) SNDRV_PCM_RATE_48000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .rate_min = 44100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .channels_min = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .period_bytes_min = RME32_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .period_bytes_max = RME32_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static void snd_rme32_reset_dac(struct rme32 *rme32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) writel(rme32->wcreg | RME32_WCR_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static int snd_rme32_playback_getrate(struct rme32 * rme32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) rate = 32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) rate = 44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) rate = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) *is_adat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (rme32->rcreg & RME32_RCR_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* ADAT rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) *is_adat = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (rme32->rcreg & RME32_RCR_ERF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* S/PDIF rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (RME32_PRO_WITH_8414(rme32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) switch (n) { /* supporting the CS8414 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return 96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return 88200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return 44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return 32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) switch (n) { /* supporting the CS8412 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return 32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return 44056;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return 32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ds = rme32->wcreg & RME32_WCR_DS_BM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) rme32->wcreg &= ~RME32_WCR_DS_BM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ~RME32_WCR_FREQ_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) rme32->wcreg &= ~RME32_WCR_DS_BM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ~RME32_WCR_FREQ_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) rme32->wcreg &= ~RME32_WCR_DS_BM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) RME32_WCR_FREQ_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) case 64000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) rme32->wcreg |= RME32_WCR_DS_BM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ~RME32_WCR_FREQ_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) rme32->wcreg |= RME32_WCR_DS_BM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ~RME32_WCR_FREQ_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) rme32->wcreg |= RME32_WCR_DS_BM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) RME32_WCR_FREQ_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) (ds && !(rme32->wcreg & RME32_WCR_DS_BM)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* change to/from double-speed: reset the DAC (if available) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) snd_rme32_reset_dac(rme32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int snd_rme32_setclockmode(struct rme32 * rme32, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) case RME32_CLOCKMODE_SLAVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* AutoSync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ~RME32_WCR_FREQ_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) case RME32_CLOCKMODE_MASTER_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Internal 32.0kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ~RME32_WCR_FREQ_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case RME32_CLOCKMODE_MASTER_44:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Internal 44.1kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) RME32_WCR_FREQ_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) case RME32_CLOCKMODE_MASTER_48:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* Internal 48.0kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) RME32_WCR_FREQ_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int snd_rme32_getclockmode(struct rme32 * rme32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int snd_rme32_setinputtype(struct rme32 * rme32, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) case RME32_INPUT_OPTICAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ~RME32_WCR_INP_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) case RME32_INPUT_COAXIAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ~RME32_WCR_INP_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case RME32_INPUT_INTERNAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) RME32_WCR_INP_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) case RME32_INPUT_XLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) RME32_WCR_INP_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int snd_rme32_getinputtype(struct rme32 * rme32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) int frlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (n_channels == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) frlog = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* assume 8 channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) frlog = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (is_playback) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) rme32->playback_frlog = frlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) rme32->capture_frlog = frlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static int snd_rme32_setformat(struct rme32 *rme32, snd_pcm_format_t format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) switch (format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) rme32->wcreg &= ~RME32_WCR_MODE24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) case SNDRV_PCM_FORMAT_S32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) rme32->wcreg |= RME32_WCR_MODE24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) snd_rme32_playback_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) int err, rate, dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (!rme32->fullduplex_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) runtime->dma_area = (void __force *)(rme32->iobase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) RME32_IO_DATA_BUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) runtime->dma_bytes = RME32_BUFFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) spin_lock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if ((rme32->rcreg & RME32_RCR_KMODE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* AutoSync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if ((int)params_rate(params) != rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) } else if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) snd_rme32_setframelog(rme32, params_channels(params), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (rme32->capture_periodsize != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* S/PDIF setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if ((rme32->wcreg & RME32_WCR_ADAT) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) rme32->wcreg |= rme32->wcreg_spdif_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) snd_rme32_capture_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) int err, isadat, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (!rme32->fullduplex_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) runtime->dma_area = (void __force *)rme32->iobase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) RME32_IO_DATA_BUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) runtime->dma_bytes = RME32_BUFFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) spin_lock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* enable AutoSync for record-preparing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) rme32->wcreg |= RME32_WCR_AUTOSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if ((int)params_rate(params) != rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if ((isadat && runtime->hw.channels_min == 2) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) (!isadat && runtime->hw.channels_min == 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* AutoSync off for recording */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) rme32->wcreg &= ~RME32_WCR_AUTOSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) snd_rme32_setframelog(rme32, params_channels(params), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (rme32->playback_periodsize != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (params_period_size(params) << rme32->capture_frlog !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) rme32->playback_periodsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) rme32->capture_periodsize =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) params_period_size(params) << rme32->capture_frlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (!from_pause) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) writel(0, rme32->iobase + RME32_IO_RESET_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) rme32->wcreg |= RME32_WCR_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * Check if there is an unconfirmed IRQ, if so confirm it, or else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * the hardware will not stop generating interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (rme32->rcreg & RME32_RCR_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) rme32->wcreg &= ~RME32_WCR_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (rme32->wcreg & RME32_WCR_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) rme32->wcreg |= RME32_WCR_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (! to_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) writel(0, rme32->iobase + RME32_IO_RESET_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct rme32 *rme32 = (struct rme32 *) dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (!(rme32->rcreg & RME32_RCR_IRQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (rme32->capture_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) snd_pcm_period_elapsed(rme32->capture_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (rme32->playback_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) snd_pcm_period_elapsed(rme32->playback_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static const unsigned int period_bytes[] = { RME32_BLOCK_SIZE };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .count = ARRAY_SIZE(period_bytes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .list = period_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .mask = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (! rme32->fullduplex_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) snd_pcm_hw_constraint_single(runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) RME32_BUFFER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) snd_pcm_hw_constraint_list(runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) &hw_constraints_period_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) int rate, dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) spin_lock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (rme32->playback_substream != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) rme32->wcreg &= ~RME32_WCR_ADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) rme32->playback_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (rme32->fullduplex_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) runtime->hw = snd_rme32_spdif_fd_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) runtime->hw = snd_rme32_spdif_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) runtime->hw.rate_max = 96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if ((rme32->rcreg & RME32_RCR_KMODE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* AutoSync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) runtime->hw.rate_min = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) runtime->hw.rate_max = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) snd_rme32_set_buffer_constraint(rme32, runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) rme32->wcreg_spdif_stream = rme32->wcreg_spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) int isadat, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) spin_lock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (rme32->capture_substream != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) rme32->capture_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (rme32->fullduplex_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) runtime->hw = snd_rme32_spdif_fd_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) runtime->hw = snd_rme32_spdif_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (RME32_PRO_WITH_8414(rme32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) runtime->hw.rate_max = 96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (isadat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) runtime->hw.rate_min = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) runtime->hw.rate_max = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) snd_rme32_set_buffer_constraint(rme32, runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) snd_rme32_playback_adat_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) int rate, dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) spin_lock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (rme32->playback_substream != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) rme32->wcreg |= RME32_WCR_ADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) rme32->playback_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (rme32->fullduplex_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) runtime->hw = snd_rme32_adat_fd_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) runtime->hw = snd_rme32_adat_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if ((rme32->rcreg & RME32_RCR_KMODE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* AutoSync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) runtime->hw.rate_min = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) runtime->hw.rate_max = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) snd_rme32_set_buffer_constraint(rme32, runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) snd_rme32_capture_adat_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) int isadat, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (rme32->fullduplex_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) runtime->hw = snd_rme32_adat_fd_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) runtime->hw = snd_rme32_adat_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (!isadat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) runtime->hw.rate_min = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) runtime->hw.rate_max = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) spin_lock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (rme32->capture_substream != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) rme32->capture_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) snd_rme32_set_buffer_constraint(rme32, runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static int snd_rme32_playback_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) int spdif = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) spin_lock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) rme32->playback_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) rme32->playback_periodsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (spdif) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) SNDRV_CTL_EVENT_MASK_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) &rme32->spdif_ctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static int snd_rme32_capture_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) spin_lock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) rme32->capture_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) rme32->capture_periodsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) spin_lock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (rme32->fullduplex_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) writel(0, rme32->iobase + RME32_IO_RESET_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (rme32->wcreg & RME32_WCR_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) rme32->wcreg &= ~RME32_WCR_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) spin_lock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (rme32->fullduplex_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) writel(0, rme32->iobase + RME32_IO_RESET_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct snd_pcm_substream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) spin_lock(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) snd_pcm_group_for_each_entry(s, substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if (s != rme32->playback_substream &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) s != rme32->capture_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) rme32->running |= (1 << s->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (rme32->fullduplex_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* remember the current DMA position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (s == rme32->playback_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) rme32->playback_pcm.hw_io =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) rme32->capture_pcm.hw_io =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) rme32->running &= ~(1 << s->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) snd_pcm_trigger_done(s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if (rme32->running && ! RME32_ISWORKING(rme32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) snd_rme32_pcm_start(rme32, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (! rme32->running && RME32_ISWORKING(rme32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) snd_rme32_pcm_stop(rme32, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (rme32->running && RME32_ISWORKING(rme32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) snd_rme32_pcm_stop(rme32, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (rme32->running && ! RME32_ISWORKING(rme32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) snd_rme32_pcm_start(rme32, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) spin_unlock(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* pointer callback for halfduplex mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) snd_rme32_playback_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) snd_rme32_capture_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /* ack and pointer callbacks for fullduplex mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct snd_pcm_indirect *rec, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) substream->runtime->dma_area + rec->sw_data, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) struct snd_pcm_indirect *rec, *cprec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) rec = &rme32->playback_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) cprec = &rme32->capture_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) spin_lock(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) rec->hw_queue_size = RME32_BUFFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) rec->hw_queue_size -= cprec->hw_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) spin_unlock(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return snd_pcm_indirect_playback_transfer(substream, rec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) snd_rme32_pb_trans_copy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) struct snd_pcm_indirect *rec, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) memcpy_fromio(substream->runtime->dma_area + rec->sw_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) return snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) snd_rme32_cp_trans_copy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) snd_rme32_pcm_byteptr(rme32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct rme32 *rme32 = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) snd_rme32_pcm_byteptr(rme32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /* for halfduplex mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) static const struct snd_pcm_ops snd_rme32_playback_spdif_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .open = snd_rme32_playback_spdif_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .close = snd_rme32_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .hw_params = snd_rme32_playback_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .prepare = snd_rme32_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .trigger = snd_rme32_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .pointer = snd_rme32_playback_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .copy_user = snd_rme32_playback_copy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .copy_kernel = snd_rme32_playback_copy_kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .fill_silence = snd_rme32_playback_silence,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .mmap = snd_pcm_lib_mmap_iomem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) static const struct snd_pcm_ops snd_rme32_capture_spdif_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .open = snd_rme32_capture_spdif_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .close = snd_rme32_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .hw_params = snd_rme32_capture_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .prepare = snd_rme32_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .trigger = snd_rme32_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .pointer = snd_rme32_capture_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .copy_user = snd_rme32_capture_copy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .copy_kernel = snd_rme32_capture_copy_kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .mmap = snd_pcm_lib_mmap_iomem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static const struct snd_pcm_ops snd_rme32_playback_adat_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .open = snd_rme32_playback_adat_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .close = snd_rme32_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .hw_params = snd_rme32_playback_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .prepare = snd_rme32_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .trigger = snd_rme32_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .pointer = snd_rme32_playback_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .copy_user = snd_rme32_playback_copy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .copy_kernel = snd_rme32_playback_copy_kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .fill_silence = snd_rme32_playback_silence,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .mmap = snd_pcm_lib_mmap_iomem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static const struct snd_pcm_ops snd_rme32_capture_adat_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .open = snd_rme32_capture_adat_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .close = snd_rme32_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .hw_params = snd_rme32_capture_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .prepare = snd_rme32_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .trigger = snd_rme32_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .pointer = snd_rme32_capture_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .copy_user = snd_rme32_capture_copy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .copy_kernel = snd_rme32_capture_copy_kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .mmap = snd_pcm_lib_mmap_iomem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /* for fullduplex mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) static const struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .open = snd_rme32_playback_spdif_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .close = snd_rme32_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .hw_params = snd_rme32_playback_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .prepare = snd_rme32_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .trigger = snd_rme32_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .pointer = snd_rme32_playback_fd_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .ack = snd_rme32_playback_fd_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static const struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .open = snd_rme32_capture_spdif_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .close = snd_rme32_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .hw_params = snd_rme32_capture_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .prepare = snd_rme32_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .trigger = snd_rme32_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .pointer = snd_rme32_capture_fd_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .ack = snd_rme32_capture_fd_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static const struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .open = snd_rme32_playback_adat_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .close = snd_rme32_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .hw_params = snd_rme32_playback_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .prepare = snd_rme32_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .trigger = snd_rme32_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .pointer = snd_rme32_playback_fd_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .ack = snd_rme32_playback_fd_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static const struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .open = snd_rme32_capture_adat_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .close = snd_rme32_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .hw_params = snd_rme32_capture_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .prepare = snd_rme32_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .trigger = snd_rme32_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .pointer = snd_rme32_capture_fd_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .ack = snd_rme32_capture_fd_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) static void snd_rme32_free(void *private_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) struct rme32 *rme32 = (struct rme32 *) private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (rme32 == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (rme32->irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) snd_rme32_pcm_stop(rme32, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) free_irq(rme32->irq, (void *) rme32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) rme32->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (rme32->iobase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) iounmap(rme32->iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) rme32->iobase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (rme32->port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) pci_release_regions(rme32->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) rme32->port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) pci_disable_device(rme32->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) rme32->spdif_pcm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) snd_rme32_free_adat_pcm(struct snd_pcm *pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) rme32->adat_pcm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) static int snd_rme32_create(struct rme32 *rme32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) struct pci_dev *pci = rme32->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) rme32->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) spin_lock_init(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if ((err = pci_enable_device(pci)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if ((err = pci_request_regions(pci, "RME32")) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) rme32->port = pci_resource_start(rme32->pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) rme32->iobase = ioremap(rme32->port, RME32_IO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (!rme32->iobase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) dev_err(rme32->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) "unable to remap memory region 0x%lx-0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) rme32->port, rme32->port + RME32_IO_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (request_irq(pci->irq, snd_rme32_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) KBUILD_MODNAME, rme32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) dev_err(rme32->card->dev, "unable to grab IRQ %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) rme32->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) rme32->card->sync_irq = rme32->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* read the card's revision number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) pci_read_config_byte(pci, 8, &rme32->rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /* set up ALSA pcm device for S/PDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if ((err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) rme32->spdif_pcm->private_data = rme32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) strcpy(rme32->spdif_pcm->name, "Digi32 IEC958");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (rme32->fullduplex_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) &snd_rme32_playback_spdif_fd_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) &snd_rme32_capture_spdif_fd_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) snd_pcm_set_managed_buffer_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) NULL, 0, RME32_MID_BUFFER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) &snd_rme32_playback_spdif_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) &snd_rme32_capture_spdif_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) /* set up ALSA pcm device for ADAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /* ADAT is not available on DIGI32 and DIGI32 Pro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) rme32->adat_pcm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if ((err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) 1, 1, &rme32->adat_pcm)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) rme32->adat_pcm->private_data = rme32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) strcpy(rme32->adat_pcm->name, "Digi32 ADAT");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (rme32->fullduplex_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) &snd_rme32_playback_adat_fd_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) &snd_rme32_capture_adat_fd_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) snd_pcm_set_managed_buffer_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) 0, RME32_MID_BUFFER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) &snd_rme32_playback_adat_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) &snd_rme32_capture_adat_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) rme32->playback_periodsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) rme32->capture_periodsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) /* make sure playback/capture is stopped, if by some reason active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) snd_rme32_pcm_stop(rme32, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) /* reset DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) snd_rme32_reset_dac(rme32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) /* reset buffer pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) writel(0, rme32->iobase + RME32_IO_RESET_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) /* set default values in registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) rme32->wcreg = RME32_WCR_SEL | /* normal playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) RME32_WCR_INP_0 | /* input select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) RME32_WCR_MUTE; /* muting on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /* init switch interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if ((err = snd_rme32_create_switches(rme32->card, rme32)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) /* init proc interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) snd_rme32_proc_init(rme32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) rme32->capture_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) rme32->playback_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) * proc interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) struct rme32 *rme32 = (struct rme32 *) entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) snd_iprintf(buffer, rme32->card->longname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) snd_iprintf(buffer, "\nGeneral settings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (rme32->fullduplex_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) snd_iprintf(buffer, " Full-duplex mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) snd_iprintf(buffer, " Half-duplex mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (RME32_PRO_WITH_8414(rme32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) snd_iprintf(buffer, " receiver: CS8414\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) snd_iprintf(buffer, " receiver: CS8412\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (rme32->wcreg & RME32_WCR_MODE24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) snd_iprintf(buffer, " format: 24 bit");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) snd_iprintf(buffer, " format: 16 bit");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (rme32->wcreg & RME32_WCR_MONO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) snd_iprintf(buffer, ", Mono\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) snd_iprintf(buffer, ", Stereo\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) snd_iprintf(buffer, "\nInput settings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) switch (snd_rme32_getinputtype(rme32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) case RME32_INPUT_OPTICAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) snd_iprintf(buffer, " input: optical");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) case RME32_INPUT_COAXIAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) snd_iprintf(buffer, " input: coaxial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) case RME32_INPUT_INTERNAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) snd_iprintf(buffer, " input: internal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) case RME32_INPUT_XLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) snd_iprintf(buffer, " input: XLR");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (snd_rme32_capture_getrate(rme32, &n) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) snd_iprintf(buffer, "\n sample rate: no valid signal\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) snd_iprintf(buffer, " (8 channels)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) snd_iprintf(buffer, " (2 channels)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) snd_iprintf(buffer, " sample rate: %d Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) snd_rme32_capture_getrate(rme32, &n));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) snd_iprintf(buffer, "\nOutput settings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) if (rme32->wcreg & RME32_WCR_SEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) snd_iprintf(buffer, " output signal: normal playback");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) snd_iprintf(buffer, " output signal: same as input");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (rme32->wcreg & RME32_WCR_MUTE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) snd_iprintf(buffer, " (muted)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) snd_iprintf(buffer, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) /* master output frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if (!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) ((!(rme32->wcreg & RME32_WCR_FREQ_0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) snd_iprintf(buffer, " sample rate: %d Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) snd_rme32_playback_getrate(rme32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) if (rme32->rcreg & RME32_RCR_KMODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) snd_iprintf(buffer, " sample clock source: AutoSync\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) snd_iprintf(buffer, " sample clock source: Internal\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (rme32->wcreg & RME32_WCR_PRO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) snd_iprintf(buffer, " format: AES/EBU (professional)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) snd_iprintf(buffer, " format: IEC958 (consumer)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if (rme32->wcreg & RME32_WCR_EMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) snd_iprintf(buffer, " emphasis: on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) snd_iprintf(buffer, " emphasis: off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) static void snd_rme32_proc_init(struct rme32 *rme32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) snd_card_ro_proc_new(rme32->card, "rme32", rme32, snd_rme32_proc_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) * control interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) #define snd_rme32_info_loopback_control snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) spin_lock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) ucontrol->value.integer.value[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) rme32->wcreg & RME32_WCR_SEL ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) spin_lock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) val = (rme32->wcreg & ~RME32_WCR_SEL) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) change = val != rme32->wcreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) if (ucontrol->value.integer.value[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) val &= ~RME32_WCR_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) val |= RME32_WCR_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) rme32->wcreg = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static const char * const texts[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) "Optical", "Coaxial", "Internal", "XLR"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) int num_items;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) switch (rme32->pci->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) case PCI_DEVICE_ID_RME_DIGI32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) case PCI_DEVICE_ID_RME_DIGI32_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) num_items = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) case PCI_DEVICE_ID_RME_DIGI32_PRO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) num_items = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) return snd_ctl_enum_info(uinfo, 1, num_items, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) unsigned int items = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) spin_lock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) switch (rme32->pci->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) case PCI_DEVICE_ID_RME_DIGI32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) case PCI_DEVICE_ID_RME_DIGI32_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) items = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) case PCI_DEVICE_ID_RME_DIGI32_PRO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) items = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (ucontrol->value.enumerated.item[0] >= items) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) ucontrol->value.enumerated.item[0] = items - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) int change, items = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) switch (rme32->pci->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) case PCI_DEVICE_ID_RME_DIGI32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) case PCI_DEVICE_ID_RME_DIGI32_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) items = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) case PCI_DEVICE_ID_RME_DIGI32_PRO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) items = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) val = ucontrol->value.enumerated.item[0] % items;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) spin_lock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) change = val != (unsigned int)snd_rme32_getinputtype(rme32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) snd_rme32_setinputtype(rme32, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) static const char * const texts[4] = { "AutoSync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) "Internal 32.0kHz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) "Internal 44.1kHz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) "Internal 48.0kHz" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) return snd_ctl_enum_info(uinfo, 1, 4, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) spin_lock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) val = ucontrol->value.enumerated.item[0] % 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) spin_lock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) change = val != (unsigned int)snd_rme32_getclockmode(rme32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) snd_rme32_setclockmode(rme32, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (val & RME32_WCR_PRO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) if (val & RME32_WCR_PRO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) snd_rme32_convert_to_aes(&ucontrol->value.iec958,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) rme32->wcreg_spdif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) spin_lock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) change = val != rme32->wcreg_spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) rme32->wcreg_spdif = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) struct snd_ctl_elem_value *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) snd_rme32_convert_to_aes(&ucontrol->value.iec958,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) rme32->wcreg_spdif_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) struct snd_ctl_elem_value *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) spin_lock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) change = val != rme32->wcreg_spdif_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) rme32->wcreg_spdif_stream = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) rme32->wcreg |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) spin_unlock_irq(&rme32->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) struct snd_ctl_elem_value *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) ucontrol->value.iec958.status[0] = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) static const struct snd_kcontrol_new snd_rme32_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .info = snd_rme32_control_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .get = snd_rme32_control_spdif_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .put = snd_rme32_control_spdif_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .info = snd_rme32_control_spdif_stream_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .get = snd_rme32_control_spdif_stream_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .put = snd_rme32_control_spdif_stream_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .info = snd_rme32_control_spdif_mask_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .get = snd_rme32_control_spdif_mask_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .info = snd_rme32_control_spdif_mask_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .get = snd_rme32_control_spdif_mask_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .name = "Input Connector",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .info = snd_rme32_info_inputtype_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .get = snd_rme32_get_inputtype_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .put = snd_rme32_put_inputtype_control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .name = "Loopback Input",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .info = snd_rme32_info_loopback_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .get = snd_rme32_get_loopback_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .put = snd_rme32_put_loopback_control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .name = "Sample Clock Source",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .info = snd_rme32_info_clockmode_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .get = snd_rme32_get_clockmode_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .put = snd_rme32_put_clockmode_control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) int idx, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) if (idx == 1) /* IEC958 (S/PDIF) Stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) rme32->spdif_ctl = kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) * Card initialisation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) static void snd_rme32_card_free(struct snd_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) snd_rme32_free(card->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) struct rme32 *rme32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if (dev >= SNDRV_CARDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (!enable[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) sizeof(struct rme32), &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) card->private_free = snd_rme32_card_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) rme32 = (struct rme32 *) card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) rme32->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) rme32->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) if (fullduplex[dev])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) rme32->fullduplex_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if ((err = snd_rme32_create(rme32)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) strcpy(card->driver, "Digi32");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) switch (rme32->pci->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) case PCI_DEVICE_ID_RME_DIGI32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) strcpy(card->shortname, "RME Digi32");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) case PCI_DEVICE_ID_RME_DIGI32_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) strcpy(card->shortname, "RME Digi32/8");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) case PCI_DEVICE_ID_RME_DIGI32_PRO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) strcpy(card->shortname, "RME Digi32 PRO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) card->shortname, rme32->rev, rme32->port, rme32->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) if ((err = snd_card_register(card)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) static void snd_rme32_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) snd_card_free(pci_get_drvdata(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) static struct pci_driver rme32_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .id_table = snd_rme32_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .probe = snd_rme32_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .remove = snd_rme32_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) module_pci_driver(rme32_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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