^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * card driver for models with WM8776/WM8766 DACs (Xonar DS/HDAV1.3 Slim)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Xonar DS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * --------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * CMI8788:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * SPI 0 -> WM8766 (surround, center/LFE, back)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * SPI 1 -> WM8776 (front, input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * GPIO 4 <- headphone detect, 0 = plugged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * GPIO 6 -> route input jack to mic-in (0) or line-in (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * GPIO 7 -> enable output to front L/R speaker channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * GPIO 8 -> enable output to other speaker channels and front panel headphone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * WM8776:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * input 1 <- line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * input 2 <- mic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * input 3 <- front mic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * input 4 <- aux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Xonar HDAV1.3 Slim
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * ------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * CMI8788:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * I²C <-> WM8776 (addr 0011010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * GPIO 0 -> disable HDMI output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * GPIO 1 -> enable HP output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * GPIO 6 -> firmware EEPROM I²C clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * GPIO 7 <-> firmware EEPROM I²C data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * UART <-> HDMI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * WM8776:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * input 1 <- mic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * input 2 <- aux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <sound/jack.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include "xonar.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include "wm8776.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include "wm8766.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GPIO_DS_HP_DETECT 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GPIO_DS_INPUT_ROUTE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GPIO_DS_OUTPUT_FRONTLR 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GPIO_DS_OUTPUT_ENABLE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GPIO_SLIM_HDMI_DISABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GPIO_SLIM_OUTPUT_ENABLE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GPIO_SLIM_FIRMWARE_CLK 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GPIO_SLIM_FIRMWARE_DATA 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define I2C_DEVICE_WM8776 0x34 /* 001101, 0, /W=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LC_CONTROL_LIMITER 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LC_CONTROL_ALC 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct xonar_wm87x6 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct xonar_generic generic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u16 wm8776_regs[0x17];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u16 wm8766_regs[0x10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct snd_kcontrol *line_adcmux_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct snd_kcontrol *mic_adcmux_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct snd_kcontrol *lc_controls[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct snd_jack *hp_jack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct xonar_hdmi hdmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static void wm8776_write_spi(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int reg, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) OXYGEN_SPI_DATA_LENGTH_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) OXYGEN_SPI_CLOCK_160 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) (1 << OXYGEN_SPI_CODEC_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) OXYGEN_SPI_CEN_LATCH_CLOCK_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) (reg << 9) | value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void wm8776_write_i2c(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int reg, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) oxygen_write_i2c(chip, I2C_DEVICE_WM8776,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) (reg << 1) | (value >> 8), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void wm8776_write(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int reg, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if ((chip->model.function_flags & OXYGEN_FUNCTION_2WIRE_SPI_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) OXYGEN_FUNCTION_SPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) wm8776_write_spi(chip, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) wm8776_write_i2c(chip, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (reg < ARRAY_SIZE(data->wm8776_regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* reg >= WM8776_HPLVOL is always true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (reg <= WM8776_DACMASTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) value &= ~WM8776_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) data->wm8776_regs[reg] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void wm8776_write_cached(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int reg, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (reg >= ARRAY_SIZE(data->wm8776_regs) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) value != data->wm8776_regs[reg])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) wm8776_write(chip, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void wm8766_write(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int reg, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) OXYGEN_SPI_DATA_LENGTH_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) OXYGEN_SPI_CLOCK_160 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) (0 << OXYGEN_SPI_CODEC_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) OXYGEN_SPI_CEN_LATCH_CLOCK_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) (reg << 9) | value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (reg < ARRAY_SIZE(data->wm8766_regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* reg >= WM8766_LDA1 is always true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (reg <= WM8766_RDA1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) (reg >= WM8766_LDA2 && reg <= WM8766_MASTDA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) value &= ~WM8766_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) data->wm8766_regs[reg] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void wm8766_write_cached(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int reg, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (reg >= ARRAY_SIZE(data->wm8766_regs) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) value != data->wm8766_regs[reg])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) wm8766_write(chip, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void wm8776_registers_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) wm8776_write(chip, WM8776_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) wm8776_write(chip, WM8776_PHASESWAP, WM8776_PH_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) wm8776_write(chip, WM8776_DACCTRL1, WM8776_DZCEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) WM8776_PL_LEFT_LEFT | WM8776_PL_RIGHT_RIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) wm8776_write(chip, WM8776_DACMUTE, chip->dac_mute ? WM8776_DMUTE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) wm8776_write(chip, WM8776_DACIFCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) WM8776_DACFMT_LJUST | WM8776_DACWL_24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) wm8776_write(chip, WM8776_ADCIFCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) data->wm8776_regs[WM8776_ADCIFCTRL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) wm8776_write(chip, WM8776_MSTRCTRL, data->wm8776_regs[WM8776_MSTRCTRL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) wm8776_write(chip, WM8776_PWRDOWN, data->wm8776_regs[WM8776_PWRDOWN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) wm8776_write(chip, WM8776_HPLVOL, data->wm8776_regs[WM8776_HPLVOL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) wm8776_write(chip, WM8776_HPRVOL, data->wm8776_regs[WM8776_HPRVOL] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) WM8776_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) wm8776_write(chip, WM8776_ADCLVOL, data->wm8776_regs[WM8776_ADCLVOL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) wm8776_write(chip, WM8776_ADCRVOL, data->wm8776_regs[WM8776_ADCRVOL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) wm8776_write(chip, WM8776_ADCMUX, data->wm8776_regs[WM8776_ADCMUX]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) wm8776_write(chip, WM8776_DACLVOL, chip->dac_volume[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) wm8776_write(chip, WM8776_DACRVOL, chip->dac_volume[1] | WM8776_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void wm8766_registers_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) wm8766_write(chip, WM8766_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) wm8766_write(chip, WM8766_DAC_CTRL, data->wm8766_regs[WM8766_DAC_CTRL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) wm8766_write(chip, WM8766_INT_CTRL, WM8766_FMT_LJUST | WM8766_IWL_24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) wm8766_write(chip, WM8766_DAC_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) WM8766_ZCD | (chip->dac_mute ? WM8766_DMUTE_MASK : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) wm8766_write(chip, WM8766_LDA1, chip->dac_volume[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) wm8766_write(chip, WM8766_RDA1, chip->dac_volume[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) wm8766_write(chip, WM8766_LDA2, chip->dac_volume[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) wm8766_write(chip, WM8766_RDA2, chip->dac_volume[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) wm8766_write(chip, WM8766_LDA3, chip->dac_volume[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) wm8766_write(chip, WM8766_RDA3, chip->dac_volume[7] | WM8766_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void wm8776_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) data->wm8776_regs[WM8776_HPLVOL] = (0x79 - 60) | WM8776_HPZCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) data->wm8776_regs[WM8776_HPRVOL] = (0x79 - 60) | WM8776_HPZCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) data->wm8776_regs[WM8776_ADCIFCTRL] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) WM8776_ADCFMT_LJUST | WM8776_ADCWL_24 | WM8776_ADCMCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) data->wm8776_regs[WM8776_MSTRCTRL] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) WM8776_ADCRATE_256 | WM8776_DACRATE_256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) data->wm8776_regs[WM8776_PWRDOWN] = WM8776_HPPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) data->wm8776_regs[WM8776_ADCLVOL] = 0xa5 | WM8776_ZCA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) data->wm8776_regs[WM8776_ADCRVOL] = 0xa5 | WM8776_ZCA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) data->wm8776_regs[WM8776_ADCMUX] = 0x001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) wm8776_registers_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void wm8766_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) data->wm8766_regs[WM8766_DAC_CTRL] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) WM8766_PL_LEFT_LEFT | WM8766_PL_RIGHT_RIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) wm8766_registers_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static void xonar_ds_handle_hp_jack(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) bool hp_plugged;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) hp_plugged = !(oxygen_read16(chip, OXYGEN_GPIO_DATA) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) GPIO_DS_HP_DETECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) oxygen_write16_masked(chip, OXYGEN_GPIO_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) hp_plugged ? 0 : GPIO_DS_OUTPUT_FRONTLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) GPIO_DS_OUTPUT_FRONTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) reg = data->wm8766_regs[WM8766_DAC_CTRL] & ~WM8766_MUTEALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (hp_plugged)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) reg |= WM8766_MUTEALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) wm8766_write_cached(chip, WM8766_DAC_CTRL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) snd_jack_report(data->hp_jack, hp_plugged ? SND_JACK_HEADPHONE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static void xonar_ds_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) data->generic.anti_pop_delay = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) data->generic.output_enable_bit = GPIO_DS_OUTPUT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) wm8776_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) wm8766_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) GPIO_DS_INPUT_ROUTE | GPIO_DS_OUTPUT_FRONTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) oxygen_clear_bits16(chip, OXYGEN_GPIO_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) GPIO_DS_HP_DETECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) oxygen_set_bits16(chip, OXYGEN_GPIO_DATA, GPIO_DS_INPUT_ROUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) oxygen_set_bits16(chip, OXYGEN_GPIO_INTERRUPT_MASK, GPIO_DS_HP_DETECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) chip->interrupt_mask |= OXYGEN_INT_GPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) xonar_enable_output(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) snd_jack_new(chip->card, "Headphone",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) SND_JACK_HEADPHONE, &data->hp_jack, false, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) xonar_ds_handle_hp_jack(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) snd_component_add(chip->card, "WM8776");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) snd_component_add(chip->card, "WM8766");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static void xonar_hdav_slim_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) data->generic.anti_pop_delay = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) data->generic.output_enable_bit = GPIO_SLIM_OUTPUT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) wm8776_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) GPIO_SLIM_HDMI_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) GPIO_SLIM_FIRMWARE_CLK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) GPIO_SLIM_FIRMWARE_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) xonar_hdmi_init(chip, &data->hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) xonar_enable_output(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) snd_component_add(chip->card, "WM8776");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static void xonar_ds_cleanup(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) xonar_disable_output(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) wm8776_write(chip, WM8776_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void xonar_hdav_slim_cleanup(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) xonar_hdmi_cleanup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) xonar_disable_output(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) wm8776_write(chip, WM8776_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) msleep(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void xonar_ds_suspend(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) xonar_ds_cleanup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static void xonar_hdav_slim_suspend(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) xonar_hdav_slim_cleanup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static void xonar_ds_resume(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) wm8776_registers_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) wm8766_registers_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) xonar_enable_output(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) xonar_ds_handle_hp_jack(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void xonar_hdav_slim_resume(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) wm8776_registers_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) xonar_hdmi_resume(chip, &data->hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) xonar_enable_output(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static void wm8776_adc_hardware_filter(unsigned int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct snd_pcm_hardware *hardware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (channel == PCM_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) hardware->rates = SNDRV_PCM_RATE_32000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) SNDRV_PCM_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) SNDRV_PCM_RATE_64000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) SNDRV_PCM_RATE_88200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) SNDRV_PCM_RATE_96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) hardware->rate_max = 96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static void xonar_hdav_slim_hardware_filter(unsigned int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct snd_pcm_hardware *hardware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) wm8776_adc_hardware_filter(channel, hardware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) xonar_hdmi_pcm_hardware_filter(channel, hardware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static void set_wm87x6_dac_params(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static void set_wm8776_adc_params(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) reg = WM8776_ADCRATE_256 | WM8776_DACRATE_256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (params_rate(params) > 48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) reg |= WM8776_ADCOSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) wm8776_write_cached(chip, WM8776_MSTRCTRL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static void set_hdav_slim_dac_params(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) xonar_set_hdmi_params(chip, &data->hdmi, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static void update_wm8776_volume(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u8 to_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (chip->dac_volume[0] == chip->dac_volume[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (chip->dac_volume[0] != data->wm8776_regs[WM8776_DACLVOL] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) chip->dac_volume[1] != data->wm8776_regs[WM8776_DACRVOL]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) wm8776_write(chip, WM8776_DACMASTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) chip->dac_volume[0] | WM8776_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) data->wm8776_regs[WM8776_DACLVOL] = chip->dac_volume[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) data->wm8776_regs[WM8776_DACRVOL] = chip->dac_volume[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) to_change = (chip->dac_volume[0] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) data->wm8776_regs[WM8776_DACLVOL]) << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) to_change |= (chip->dac_volume[1] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) data->wm8776_regs[WM8776_DACLVOL]) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (to_change & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) wm8776_write(chip, WM8776_DACLVOL, chip->dac_volume[0] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ((to_change & 2) ? 0 : WM8776_UPDATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (to_change & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) wm8776_write(chip, WM8776_DACRVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) chip->dac_volume[1] | WM8776_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static void update_wm87x6_volume(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static const u8 wm8766_regs[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) WM8766_LDA1, WM8766_RDA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) WM8766_LDA2, WM8766_RDA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) WM8766_LDA3, WM8766_RDA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u8 to_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) update_wm8776_volume(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (chip->dac_volume[2] == chip->dac_volume[3] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) chip->dac_volume[2] == chip->dac_volume[4] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) chip->dac_volume[2] == chip->dac_volume[5] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) chip->dac_volume[2] == chip->dac_volume[6] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) chip->dac_volume[2] == chip->dac_volume[7]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) to_change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) for (i = 0; i < 6; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (chip->dac_volume[2] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) data->wm8766_regs[wm8766_regs[i]])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) to_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (to_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) wm8766_write(chip, WM8766_MASTDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) chip->dac_volume[2] | WM8766_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) for (i = 0; i < 6; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) data->wm8766_regs[wm8766_regs[i]] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) chip->dac_volume[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) to_change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) for (i = 0; i < 6; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) to_change |= (chip->dac_volume[2 + i] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) data->wm8766_regs[wm8766_regs[i]]) << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) for (i = 0; i < 6; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (to_change & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) wm8766_write(chip, wm8766_regs[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) chip->dac_volume[2 + i] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ((to_change & (0x3e << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ? 0 : WM8766_UPDATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static void update_wm8776_mute(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) wm8776_write_cached(chip, WM8776_DACMUTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) chip->dac_mute ? WM8776_DMUTE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static void update_wm87x6_mute(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) update_wm8776_mute(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) wm8766_write_cached(chip, WM8766_DAC_CTRL2, WM8766_ZCD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) (chip->dac_mute ? WM8766_DMUTE_MASK : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static void update_wm8766_center_lfe_mix(struct oxygen *chip, bool mixed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * The WM8766 can mix left and right channels, but this setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * applies to all three stereo pairs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) reg = data->wm8766_regs[WM8766_DAC_CTRL] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ~(WM8766_PL_LEFT_MASK | WM8766_PL_RIGHT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (mixed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) reg |= WM8766_PL_LEFT_LRMIX | WM8766_PL_RIGHT_LRMIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) reg |= WM8766_PL_LEFT_LEFT | WM8766_PL_RIGHT_RIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) wm8766_write_cached(chip, WM8766_DAC_CTRL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static void xonar_ds_gpio_changed(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) xonar_ds_handle_hp_jack(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static int wm8776_bit_switch_get(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u16 bit = ctl->private_value & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) unsigned int reg_index = (ctl->private_value >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) bool invert = (ctl->private_value >> 24) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) value->value.integer.value[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ((data->wm8776_regs[reg_index] & bit) != 0) ^ invert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int wm8776_bit_switch_put(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u16 bit = ctl->private_value & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u16 reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned int reg_index = (ctl->private_value >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) bool invert = (ctl->private_value >> 24) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) reg_value = data->wm8776_regs[reg_index] & ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (value->value.integer.value[0] ^ invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) reg_value |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) changed = reg_value != data->wm8776_regs[reg_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) wm8776_write(chip, reg_index, reg_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static int wm8776_field_enum_info(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct snd_ctl_elem_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static const char *const hld[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) "0 ms", "2.67 ms", "5.33 ms", "10.6 ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) "21.3 ms", "42.7 ms", "85.3 ms", "171 ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) "341 ms", "683 ms", "1.37 s", "2.73 s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) "5.46 s", "10.9 s", "21.8 s", "43.7 s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const char *const atk_lim[11] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) "0.25 ms", "0.5 ms", "1 ms", "2 ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) "4 ms", "8 ms", "16 ms", "32 ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) "64 ms", "128 ms", "256 ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static const char *const atk_alc[11] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) "8.40 ms", "16.8 ms", "33.6 ms", "67.2 ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) "134 ms", "269 ms", "538 ms", "1.08 s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) "2.15 s", "4.3 s", "8.6 s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static const char *const dcy_lim[11] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) "1.2 ms", "2.4 ms", "4.8 ms", "9.6 ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) "19.2 ms", "38.4 ms", "76.8 ms", "154 ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) "307 ms", "614 ms", "1.23 s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static const char *const dcy_alc[11] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) "33.5 ms", "67.0 ms", "134 ms", "268 ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) "536 ms", "1.07 s", "2.14 s", "4.29 s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) "8.58 s", "17.2 s", "34.3 s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static const char *const tranwin[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) "0 us", "62.5 us", "125 us", "250 us",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) "500 us", "1 ms", "2 ms", "4 ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u8 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) const char *const *names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) max = (ctl->private_value >> 12) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) switch ((ctl->private_value >> 24) & 0x1f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case WM8776_ALCCTRL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) names = hld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case WM8776_ALCCTRL3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (((ctl->private_value >> 20) & 0xf) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (ctl->private_value & LC_CONTROL_LIMITER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) names = atk_lim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) names = atk_alc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (ctl->private_value & LC_CONTROL_LIMITER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) names = dcy_lim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) names = dcy_alc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) case WM8776_LIMITER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) names = tranwin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return snd_ctl_enum_info(info, 1, max + 1, names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int wm8776_field_volume_info(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct snd_ctl_elem_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) info->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) info->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) info->value.integer.min = (ctl->private_value >> 8) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) info->value.integer.max = (ctl->private_value >> 12) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static void wm8776_field_set_from_ctl(struct snd_kcontrol *ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned int value, reg_index, mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u8 min, max, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u16 mask, reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) bool invert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if ((data->wm8776_regs[WM8776_ALCCTRL1] & WM8776_LCSEL_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) WM8776_LCSEL_LIMITER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) mode = LC_CONTROL_LIMITER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) mode = LC_CONTROL_ALC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (!(ctl->private_value & mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) value = ctl->private_value & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) min = (ctl->private_value >> 8) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) max = (ctl->private_value >> 12) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) mask = (ctl->private_value >> 16) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) shift = (ctl->private_value >> 20) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) reg_index = (ctl->private_value >> 24) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) invert = (ctl->private_value >> 29) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) value = max - (value - min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) reg_value = data->wm8776_regs[reg_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) reg_value &= ~(mask << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) reg_value |= value << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) wm8776_write_cached(chip, reg_index, reg_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static int wm8776_field_set(struct snd_kcontrol *ctl, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u8 min, max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) min = (ctl->private_value >> 8) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) max = (ctl->private_value >> 12) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (value < min || value > max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) changed = value != (ctl->private_value & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (changed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ctl->private_value = (ctl->private_value & ~0xf) | value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) wm8776_field_set_from_ctl(ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static int wm8776_field_enum_get(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) value->value.enumerated.item[0] = ctl->private_value & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static int wm8776_field_volume_get(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) value->value.integer.value[0] = ctl->private_value & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static int wm8776_field_enum_put(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return wm8776_field_set(ctl, value->value.enumerated.item[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static int wm8776_field_volume_put(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return wm8776_field_set(ctl, value->value.integer.value[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int wm8776_hp_vol_info(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct snd_ctl_elem_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) info->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) info->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) info->value.integer.min = 0x79 - 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) info->value.integer.max = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static int wm8776_hp_vol_get(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) value->value.integer.value[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) data->wm8776_regs[WM8776_HPLVOL] & WM8776_HPATT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) value->value.integer.value[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) data->wm8776_regs[WM8776_HPRVOL] & WM8776_HPATT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static int wm8776_hp_vol_put(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u8 to_update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) to_update = (value->value.integer.value[0] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) (data->wm8776_regs[WM8776_HPLVOL] & WM8776_HPATT_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) to_update |= (value->value.integer.value[1] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) (data->wm8776_regs[WM8776_HPRVOL] & WM8776_HPATT_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (value->value.integer.value[0] == value->value.integer.value[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (to_update) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) wm8776_write(chip, WM8776_HPMASTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) value->value.integer.value[0] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) WM8776_HPZCEN | WM8776_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) data->wm8776_regs[WM8776_HPLVOL] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) value->value.integer.value[0] | WM8776_HPZCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) data->wm8776_regs[WM8776_HPRVOL] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) value->value.integer.value[0] | WM8776_HPZCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (to_update & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) wm8776_write(chip, WM8776_HPLVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) value->value.integer.value[0] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) WM8776_HPZCEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ((to_update & 2) ? 0 : WM8776_UPDATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (to_update & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) wm8776_write(chip, WM8776_HPRVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) value->value.integer.value[1] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) WM8776_HPZCEN | WM8776_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return to_update != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static int wm8776_input_mux_get(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) unsigned int mux_bit = ctl->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) value->value.integer.value[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) !!(data->wm8776_regs[WM8776_ADCMUX] & mux_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static int wm8776_input_mux_put(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct snd_kcontrol *other_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) unsigned int mux_bit = ctl->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) reg = data->wm8776_regs[WM8776_ADCMUX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (value->value.integer.value[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) reg |= mux_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* line-in and mic-in are exclusive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) mux_bit ^= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (reg & mux_bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) reg &= ~mux_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (mux_bit == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) other_ctl = data->line_adcmux_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) other_ctl = data->mic_adcmux_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) &other_ctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) reg &= ~mux_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) changed = reg != data->wm8776_regs[WM8776_ADCMUX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (changed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) oxygen_write16_masked(chip, OXYGEN_GPIO_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) reg & 1 ? GPIO_DS_INPUT_ROUTE : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) GPIO_DS_INPUT_ROUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) wm8776_write(chip, WM8776_ADCMUX, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static int wm8776_input_vol_info(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct snd_ctl_elem_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) info->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) info->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) info->value.integer.min = 0xa5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) info->value.integer.max = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int wm8776_input_vol_get(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) value->value.integer.value[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) data->wm8776_regs[WM8776_ADCLVOL] & WM8776_AGMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) value->value.integer.value[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) data->wm8776_regs[WM8776_ADCRVOL] & WM8776_AGMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static int wm8776_input_vol_put(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) int changed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) changed = (value->value.integer.value[0] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) (data->wm8776_regs[WM8776_ADCLVOL] & WM8776_AGMASK)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) (value->value.integer.value[1] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) (data->wm8776_regs[WM8776_ADCRVOL] & WM8776_AGMASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) wm8776_write_cached(chip, WM8776_ADCLVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) value->value.integer.value[0] | WM8776_ZCA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) wm8776_write_cached(chip, WM8776_ADCRVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) value->value.integer.value[1] | WM8776_ZCA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static int wm8776_level_control_info(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct snd_ctl_elem_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static const char *const names[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) "None", "Peak Limiter", "Automatic Level Control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return snd_ctl_enum_info(info, 1, 3, names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static int wm8776_level_control_get(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (!(data->wm8776_regs[WM8776_ALCCTRL2] & WM8776_LCEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) value->value.enumerated.item[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) else if ((data->wm8776_regs[WM8776_ALCCTRL1] & WM8776_LCSEL_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) WM8776_LCSEL_LIMITER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) value->value.enumerated.item[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) value->value.enumerated.item[0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static void activate_control(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct snd_kcontrol *ctl, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) unsigned int access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (ctl->private_value & mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) access = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) access = SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if ((ctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_INACTIVE) != access) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ctl->vd[0].access ^= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &ctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static int wm8776_level_control_put(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) unsigned int mode = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) u16 ctrl1, ctrl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (value->value.enumerated.item[0] >= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) changed = value->value.enumerated.item[0] != ctl->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (changed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ctl->private_value = value->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) ctrl1 = data->wm8776_regs[WM8776_ALCCTRL1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ctrl2 = data->wm8776_regs[WM8776_ALCCTRL2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) switch (value->value.enumerated.item[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) wm8776_write_cached(chip, WM8776_ALCCTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ctrl2 & ~WM8776_LCEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) wm8776_write_cached(chip, WM8776_ALCCTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) (ctrl1 & ~WM8776_LCSEL_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) WM8776_LCSEL_LIMITER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) wm8776_write_cached(chip, WM8776_ALCCTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ctrl2 | WM8776_LCEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) mode = LC_CONTROL_LIMITER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) wm8776_write_cached(chip, WM8776_ALCCTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) (ctrl1 & ~WM8776_LCSEL_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) WM8776_LCSEL_ALC_STEREO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) wm8776_write_cached(chip, WM8776_ALCCTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ctrl2 | WM8776_LCEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) mode = LC_CONTROL_ALC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) for (i = 0; i < ARRAY_SIZE(data->lc_controls); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) activate_control(chip, data->lc_controls[i], mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static int hpf_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static const char *const names[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) "None", "High-pass Filter"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return snd_ctl_enum_info(info, 1, 2, names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static int hpf_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) value->value.enumerated.item[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) !(data->wm8776_regs[WM8776_ADCIFCTRL] & WM8776_ADCHPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static int hpf_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) reg = data->wm8776_regs[WM8776_ADCIFCTRL] & ~WM8776_ADCHPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (!value->value.enumerated.item[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) reg |= WM8776_ADCHPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) changed = reg != data->wm8776_regs[WM8776_ADCIFCTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) wm8776_write(chip, WM8776_ADCIFCTRL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define WM8776_BIT_SWITCH(xname, reg, bit, invert, flags) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .info = snd_ctl_boolean_mono_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .get = wm8776_bit_switch_get, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .put = wm8776_bit_switch_put, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .private_value = ((reg) << 16) | (bit) | ((invert) << 24) | (flags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define _WM8776_FIELD_CTL(xname, reg, shift, initval, min, max, mask, flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .private_value = (initval) | ((min) << 8) | ((max) << 12) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ((mask) << 16) | ((shift) << 20) | ((reg) << 24) | (flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define WM8776_FIELD_CTL_ENUM(xname, reg, shift, init, min, max, mask, flags) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) _WM8776_FIELD_CTL(xname " Capture Enum", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) reg, shift, init, min, max, mask, flags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) SNDRV_CTL_ELEM_ACCESS_INACTIVE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .info = wm8776_field_enum_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .get = wm8776_field_enum_get, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .put = wm8776_field_enum_put, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define WM8776_FIELD_CTL_VOLUME(a, b, c, d, e, f, g, h, tlv_p) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) _WM8776_FIELD_CTL(a " Capture Volume", b, c, d, e, f, g, h), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) SNDRV_CTL_ELEM_ACCESS_INACTIVE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .info = wm8776_field_volume_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .get = wm8776_field_volume_get, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .put = wm8776_field_volume_put, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .tlv = { .p = tlv_p }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static const DECLARE_TLV_DB_SCALE(wm87x6_dac_db_scale, -6000, 50, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static const DECLARE_TLV_DB_SCALE(wm8776_adc_db_scale, -2100, 50, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static const DECLARE_TLV_DB_SCALE(wm8776_hp_db_scale, -6000, 100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static const DECLARE_TLV_DB_SCALE(wm8776_lct_db_scale, -1600, 100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static const DECLARE_TLV_DB_SCALE(wm8776_maxgain_db_scale, 0, 400, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static const DECLARE_TLV_DB_SCALE(wm8776_ngth_db_scale, -7800, 600, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static const DECLARE_TLV_DB_SCALE(wm8776_maxatten_lim_db_scale, -1200, 100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static const DECLARE_TLV_DB_SCALE(wm8776_maxatten_alc_db_scale, -2100, 400, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static const struct snd_kcontrol_new ds_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .name = "Headphone Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .info = wm8776_hp_vol_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .get = wm8776_hp_vol_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .put = wm8776_hp_vol_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .tlv = { .p = wm8776_hp_db_scale },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) WM8776_BIT_SWITCH("Headphone Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) WM8776_PWRDOWN, WM8776_HPPD, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .name = "Input Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .info = wm8776_input_vol_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .get = wm8776_input_vol_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .put = wm8776_input_vol_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .tlv = { .p = wm8776_adc_db_scale },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .name = "Line Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .info = snd_ctl_boolean_mono_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .get = wm8776_input_mux_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .put = wm8776_input_mux_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .private_value = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .name = "Mic Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .info = snd_ctl_boolean_mono_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .get = wm8776_input_mux_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .put = wm8776_input_mux_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .private_value = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) WM8776_BIT_SWITCH("Front Mic Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) WM8776_ADCMUX, 1 << 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) WM8776_BIT_SWITCH("Aux Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) WM8776_ADCMUX, 1 << 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .name = "ADC Filter Capture Enum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .info = hpf_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .get = hpf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .put = hpf_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .name = "Level Control Capture Enum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .info = wm8776_level_control_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .get = wm8776_level_control_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .put = wm8776_level_control_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .private_value = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static const struct snd_kcontrol_new hdav_slim_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .name = "HDMI Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .info = snd_ctl_boolean_mono_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .get = xonar_gpio_bit_switch_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .put = xonar_gpio_bit_switch_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .private_value = GPIO_SLIM_HDMI_DISABLE | XONAR_GPIO_BIT_INVERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .name = "Headphone Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .info = wm8776_hp_vol_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .get = wm8776_hp_vol_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .put = wm8776_hp_vol_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .tlv = { .p = wm8776_hp_db_scale },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) WM8776_BIT_SWITCH("Headphone Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) WM8776_PWRDOWN, WM8776_HPPD, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .name = "Input Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .info = wm8776_input_vol_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .get = wm8776_input_vol_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .put = wm8776_input_vol_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .tlv = { .p = wm8776_adc_db_scale },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) WM8776_BIT_SWITCH("Mic Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) WM8776_ADCMUX, 1 << 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) WM8776_BIT_SWITCH("Aux Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) WM8776_ADCMUX, 1 << 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .name = "ADC Filter Capture Enum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .info = hpf_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .get = hpf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .put = hpf_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .name = "Level Control Capture Enum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .info = wm8776_level_control_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .get = wm8776_level_control_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .put = wm8776_level_control_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .private_value = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static const struct snd_kcontrol_new lc_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) WM8776_FIELD_CTL_VOLUME("Limiter Threshold",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) WM8776_ALCCTRL1, 0, 11, 0, 15, 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) LC_CONTROL_LIMITER, wm8776_lct_db_scale),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) WM8776_FIELD_CTL_ENUM("Limiter Attack Time",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) WM8776_ALCCTRL3, 0, 2, 0, 10, 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) LC_CONTROL_LIMITER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) WM8776_FIELD_CTL_ENUM("Limiter Decay Time",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) WM8776_ALCCTRL3, 4, 3, 0, 10, 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) LC_CONTROL_LIMITER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) WM8776_FIELD_CTL_ENUM("Limiter Transient Window",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) WM8776_LIMITER, 4, 2, 0, 7, 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) LC_CONTROL_LIMITER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) WM8776_FIELD_CTL_VOLUME("Limiter Maximum Attenuation",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) WM8776_LIMITER, 0, 6, 3, 12, 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) LC_CONTROL_LIMITER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) wm8776_maxatten_lim_db_scale),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) WM8776_FIELD_CTL_VOLUME("ALC Target Level",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) WM8776_ALCCTRL1, 0, 11, 0, 15, 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) LC_CONTROL_ALC, wm8776_lct_db_scale),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) WM8776_FIELD_CTL_ENUM("ALC Attack Time",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) WM8776_ALCCTRL3, 0, 2, 0, 10, 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) LC_CONTROL_ALC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) WM8776_FIELD_CTL_ENUM("ALC Decay Time",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) WM8776_ALCCTRL3, 4, 3, 0, 10, 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) LC_CONTROL_ALC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) WM8776_FIELD_CTL_VOLUME("ALC Maximum Gain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) WM8776_ALCCTRL1, 4, 7, 1, 7, 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) LC_CONTROL_ALC, wm8776_maxgain_db_scale),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) WM8776_FIELD_CTL_VOLUME("ALC Maximum Attenuation",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) WM8776_LIMITER, 0, 10, 10, 15, 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) LC_CONTROL_ALC, wm8776_maxatten_alc_db_scale),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) WM8776_FIELD_CTL_ENUM("ALC Hold Time",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) WM8776_ALCCTRL2, 0, 0, 0, 15, 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) LC_CONTROL_ALC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) WM8776_BIT_SWITCH("Noise Gate Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) WM8776_NOISEGATE, WM8776_NGAT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) LC_CONTROL_ALC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) WM8776_FIELD_CTL_VOLUME("Noise Gate Threshold",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) WM8776_NOISEGATE, 2, 0, 0, 7, 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) LC_CONTROL_ALC, wm8776_ngth_db_scale),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static int add_lc_controls(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) struct snd_kcontrol *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) BUILD_BUG_ON(ARRAY_SIZE(lc_controls) != ARRAY_SIZE(data->lc_controls));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) for (i = 0; i < ARRAY_SIZE(lc_controls); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) ctl = snd_ctl_new1(&lc_controls[i], chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (!ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) err = snd_ctl_add(chip->card, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) data->lc_controls[i] = ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) static int xonar_ds_mixer_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct snd_kcontrol *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) for (i = 0; i < ARRAY_SIZE(ds_controls); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ctl = snd_ctl_new1(&ds_controls[i], chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (!ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) err = snd_ctl_add(chip->card, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (!strcmp(ctl->id.name, "Line Capture Switch"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) data->line_adcmux_control = ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) else if (!strcmp(ctl->id.name, "Mic Capture Switch"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) data->mic_adcmux_control = ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (!data->line_adcmux_control || !data->mic_adcmux_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return add_lc_controls(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static int xonar_hdav_slim_mixer_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) struct snd_kcontrol *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) for (i = 0; i < ARRAY_SIZE(hdav_slim_controls); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ctl = snd_ctl_new1(&hdav_slim_controls[i], chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (!ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) err = snd_ctl_add(chip->card, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) return add_lc_controls(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static void dump_wm8776_registers(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) snd_iprintf(buffer, "\nWM8776:\n00:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) for (i = 0; i < 0x10; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) snd_iprintf(buffer, " %03x", data->wm8776_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) snd_iprintf(buffer, "\n10:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) for (i = 0x10; i < 0x17; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) snd_iprintf(buffer, " %03x", data->wm8776_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) snd_iprintf(buffer, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) static void dump_wm87x6_registers(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) struct xonar_wm87x6 *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) dump_wm8776_registers(chip, buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) snd_iprintf(buffer, "\nWM8766:\n00:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) for (i = 0; i < 0x10; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) snd_iprintf(buffer, " %03x", data->wm8766_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) snd_iprintf(buffer, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static const struct oxygen_model model_xonar_ds = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .longname = "Asus Virtuoso 66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .chip = "AV200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .init = xonar_ds_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .mixer_init = xonar_ds_mixer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .cleanup = xonar_ds_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .suspend = xonar_ds_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .resume = xonar_ds_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .pcm_hardware_filter = wm8776_adc_hardware_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .set_dac_params = set_wm87x6_dac_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .set_adc_params = set_wm8776_adc_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .update_dac_volume = update_wm87x6_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .update_dac_mute = update_wm87x6_mute,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .update_center_lfe_mix = update_wm8766_center_lfe_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .gpio_changed = xonar_ds_gpio_changed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .dump_registers = dump_wm87x6_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .dac_tlv = wm87x6_dac_db_scale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .model_data_size = sizeof(struct xonar_wm87x6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .device_config = PLAYBACK_0_TO_I2S |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) PLAYBACK_1_TO_SPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) CAPTURE_0_FROM_I2S_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) CAPTURE_1_FROM_SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .dac_channels_pcm = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .dac_channels_mixer = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .dac_volume_min = 255 - 2*60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .dac_volume_max = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .function_flags = OXYGEN_FUNCTION_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .dac_mclks = OXYGEN_MCLKS(256, 256, 128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .adc_mclks = OXYGEN_MCLKS(256, 256, 128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static const struct oxygen_model model_xonar_hdav_slim = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .shortname = "Xonar HDAV1.3 Slim",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .longname = "Asus Virtuoso 200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .chip = "AV200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .init = xonar_hdav_slim_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .mixer_init = xonar_hdav_slim_mixer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .cleanup = xonar_hdav_slim_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .suspend = xonar_hdav_slim_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .resume = xonar_hdav_slim_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .pcm_hardware_filter = xonar_hdav_slim_hardware_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .set_dac_params = set_hdav_slim_dac_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .set_adc_params = set_wm8776_adc_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .update_dac_volume = update_wm8776_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .update_dac_mute = update_wm8776_mute,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .uart_input = xonar_hdmi_uart_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .dump_registers = dump_wm8776_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .dac_tlv = wm87x6_dac_db_scale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .model_data_size = sizeof(struct xonar_wm87x6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .device_config = PLAYBACK_0_TO_I2S |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) PLAYBACK_1_TO_SPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) CAPTURE_0_FROM_I2S_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) CAPTURE_1_FROM_SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .dac_channels_pcm = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .dac_channels_mixer = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .dac_volume_min = 255 - 2*60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .dac_volume_max = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .function_flags = OXYGEN_FUNCTION_2WIRE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .dac_mclks = OXYGEN_MCLKS(256, 256, 128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .adc_mclks = OXYGEN_MCLKS(256, 256, 128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) int get_xonar_wm87x6_model(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) switch (id->subdevice) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) case 0x838e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) chip->model = model_xonar_ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) chip->model.shortname = "Xonar DS";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) case 0x8522:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) chip->model = model_xonar_ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) chip->model.shortname = "Xonar DSX";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) case 0x835e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) chip->model = model_xonar_hdav_slim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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