^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * card driver for models with PCM1796 DACs (Xonar D2/D2X/HDAV1.3/ST/STX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Xonar D2/D2X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * ------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * CMI8788:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * SPI 0 -> 1st PCM1796 (front)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * SPI 1 -> 2nd PCM1796 (surround)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * SPI 2 -> 3rd PCM1796 (center/LFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * SPI 4 -> 4th PCM1796 (back)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * GPIO 2 -> M0 of CS5381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * GPIO 3 -> M1 of CS5381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * GPIO 5 <- external power present (D2X only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * GPIO 7 -> ALT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * GPIO 8 -> enable output to speakers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * CM9780:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * LINE_OUT -> input of ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * AUX_IN <- aux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * VIDEO_IN <- CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * FMIC_IN <- mic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * GPO 0 -> route line-in (0) or AC97 output (1) to CS5381 input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Xonar HDAV1.3 (Deluxe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * ----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * CMI8788:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * I²C <-> PCM1796 (addr 1001100) (front)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * GPI 0 <- external power present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * GPIO 0 -> enable HDMI (0) or speaker (1) output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * GPIO 2 -> M0 of CS5381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * GPIO 3 -> M1 of CS5381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * GPIO 4 <- daughterboard detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * GPIO 5 <- daughterboard detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * GPIO 6 -> ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * GPIO 7 -> ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * GPIO 8 -> route input jack to line-in (0) or mic-in (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * UART <-> HDMI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * CM9780:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * LINE_OUT -> input of ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * AUX_IN <- aux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * CD_IN <- CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * MIC_IN <- mic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * GPO 0 -> route line-in (0) or AC97 output (1) to CS5381 input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * no daughterboard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * ----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * GPIO 4 <- 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * H6 daughterboard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * ----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * GPIO 4 <- 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * GPIO 5 <- 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * I²C <-> PCM1796 (addr 1001101) (surround)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * <-> PCM1796 (addr 1001110) (center/LFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * <-> PCM1796 (addr 1001111) (back)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * unknown daughterboard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * GPIO 4 <- 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * GPIO 5 <- 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * I²C <-> CS4362A (addr 0011000) (surround, center/LFE, back)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Xonar Essence ST (Deluxe)/STX (II)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * ----------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * CMI8788:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * I²C <-> PCM1792A (addr 1001100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * <-> CS2000 (addr 1001110) (ST only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * ADC1 MCLK -> REF_CLK of CS2000 (ST only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * GPI 0 <- external power present (STX only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * GPIO 0 -> enable output to speakers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * GPIO 1 -> route HP to front panel (0) or rear jack (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * GPIO 2 -> M0 of CS5381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * GPIO 3 -> M1 of CS5381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * GPIO 4 <- daughterboard detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * GPIO 5 <- daughterboard detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * GPIO 6 -> ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * GPIO 7 -> route output to speaker jacks (0) or HP (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * GPIO 8 -> route input jack to line-in (0) or mic-in (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * PCM1792A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * SCK <- CLK_OUT of CS2000 (ST only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * CM9780:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * LINE_OUT -> input of ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * AUX_IN <- aux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * MIC_IN <- mic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * GPO 0 -> route line-in (0) or AC97 output (1) to CS5381 input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * H6 daughterboard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * ----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * GPIO 4 <- 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * GPIO 5 <- 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Xonar Xense
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * CMI8788:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * I²C <-> PCM1796 (addr 1001100) (front)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * <-> CS4362A (addr 0011000) (surround, center/LFE, back)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * <-> CS2000 (addr 1001110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * ADC1 MCLK -> REF_CLK of CS2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * GPI 0 <- external power present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * GPIO 0 -> enable output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * GPIO 1 -> route HP to front panel (0) or rear jack (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * GPIO 2 -> M0 of CS5381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * GPIO 3 -> M1 of CS5381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * GPIO 4 -> enable output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * GPIO 5 -> enable output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * GPIO 6 -> ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * GPIO 7 -> route output to HP (0) or speaker (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * GPIO 8 -> route input jack to mic-in (0) or line-in (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * CM9780:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * LINE_OUT -> input of ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * AUX_IN <- aux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * VIDEO_IN <- ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * FMIC_IN <- mic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * GPO 0 -> route line-in (0) or AC97 output (1) to CS5381 input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * GPO 1 -> route mic-in from input jack (0) or front panel header (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #include "xonar.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #include "cm9780.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #include "pcm1796.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #include "cs2000.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define GPIO_D2X_EXT_POWER 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define GPIO_D2_ALT 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define GPIO_D2_OUTPUT_ENABLE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define GPI_EXT_POWER 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define GPIO_INPUT_ROUTE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define GPIO_HDAV_OUTPUT_ENABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define GPIO_HDAV_MAGIC 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define GPIO_DB_MASK 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define GPIO_DB_H6 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define GPIO_ST_OUTPUT_ENABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define GPIO_ST_HP_REAR 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define GPIO_ST_MAGIC 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define GPIO_ST_HP 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define GPIO_XENSE_OUTPUT_ENABLE (0x0001 | 0x0010 | 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define GPIO_XENSE_SPEAKERS 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define I2C_DEVICE_PCM1796(i) (0x98 + ((i) << 1)) /* 10011, ii, /W=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define I2C_DEVICE_CS2000 0x9c /* 100111, 0, /W=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PCM1796_REG_BASE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct xonar_pcm179x {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct xonar_generic generic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned int dacs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u8 pcm1796_regs[4][5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned int current_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) bool h6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) bool hp_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) s8 hp_gain_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) bool has_cs2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u8 cs2000_regs[0x1f];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) bool broken_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct xonar_hdav {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct xonar_pcm179x pcm179x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct xonar_hdmi hdmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static inline void pcm1796_write_spi(struct oxygen *chip, unsigned int codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* maps ALSA channel pair number to SPI output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const u8 codec_map[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 0, 1, 2, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) OXYGEN_SPI_DATA_LENGTH_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) OXYGEN_SPI_CLOCK_160 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) (codec_map[codec] << OXYGEN_SPI_CODEC_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) OXYGEN_SPI_CEN_LATCH_CLOCK_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) (reg << 8) | value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static inline void pcm1796_write_i2c(struct oxygen *chip, unsigned int codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) oxygen_write_i2c(chip, I2C_DEVICE_PCM1796(codec), reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void pcm1796_write(struct oxygen *chip, unsigned int codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if ((chip->model.function_flags & OXYGEN_FUNCTION_2WIRE_SPI_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) OXYGEN_FUNCTION_SPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pcm1796_write_spi(chip, codec, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pcm1796_write_i2c(chip, codec, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if ((unsigned int)(reg - PCM1796_REG_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) < ARRAY_SIZE(data->pcm1796_regs[codec]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) data->pcm1796_regs[codec][reg - PCM1796_REG_BASE] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void pcm1796_write_cached(struct oxygen *chip, unsigned int codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (value != data->pcm1796_regs[codec][reg - PCM1796_REG_BASE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pcm1796_write(chip, codec, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void cs2000_write(struct oxygen *chip, u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) oxygen_write_i2c(chip, I2C_DEVICE_CS2000, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) data->cs2000_regs[reg] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void cs2000_write_cached(struct oxygen *chip, u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (value != data->cs2000_regs[reg])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) cs2000_write(chip, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static void pcm1796_registers_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) s8 gain_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) gain_offset = data->hp_active ? data->hp_gain_offset : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) for (i = 0; i < data->dacs; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* set ATLD before ATL/ATR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pcm1796_write(chip, i, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) data->pcm1796_regs[0][18 - PCM1796_REG_BASE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) pcm1796_write(chip, i, 16, chip->dac_volume[i * 2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) + gain_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) pcm1796_write(chip, i, 17, chip->dac_volume[i * 2 + 1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) + gain_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pcm1796_write(chip, i, 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) data->pcm1796_regs[0][19 - PCM1796_REG_BASE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) pcm1796_write(chip, i, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) data->pcm1796_regs[0][20 - PCM1796_REG_BASE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pcm1796_write(chip, i, 21, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) gain_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static void pcm1796_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) data->pcm1796_regs[0][18 - PCM1796_REG_BASE] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PCM1796_FMT_24_I2S | PCM1796_ATLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (!data->broken_i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) data->pcm1796_regs[0][18 - PCM1796_REG_BASE] |= PCM1796_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) data->pcm1796_regs[0][19 - PCM1796_REG_BASE] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PCM1796_FLT_SHARP | PCM1796_ATS_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) data->pcm1796_regs[0][20 - PCM1796_REG_BASE] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) data->h6 ? PCM1796_OS_64 : PCM1796_OS_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) pcm1796_registers_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) data->current_rate = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static void xonar_d2_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) data->generic.anti_pop_delay = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) data->generic.output_enable_bit = GPIO_D2_OUTPUT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) data->dacs = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pcm1796_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_D2_ALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_D2_ALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) oxygen_ac97_set_bits(chip, 0, CM9780_JACK, CM9780_FMIC2MIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) xonar_init_cs53x1(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) xonar_enable_output(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) snd_component_add(chip->card, "PCM1796");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) snd_component_add(chip->card, "CS5381");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void xonar_d2x_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) data->generic.ext_power_reg = OXYGEN_GPIO_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) data->generic.ext_power_int_reg = OXYGEN_GPIO_INTERRUPT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) data->generic.ext_power_bit = GPIO_D2X_EXT_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) oxygen_clear_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_D2X_EXT_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) xonar_init_ext_power(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) xonar_d2_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static void xonar_hdav_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct xonar_hdav *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) OXYGEN_2WIRE_LENGTH_8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) OXYGEN_2WIRE_INTERRUPT_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) OXYGEN_2WIRE_SPEED_STANDARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) data->pcm179x.generic.anti_pop_delay = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) data->pcm179x.generic.output_enable_bit = GPIO_HDAV_OUTPUT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) data->pcm179x.generic.ext_power_reg = OXYGEN_GPI_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) data->pcm179x.generic.ext_power_int_reg = OXYGEN_GPI_INTERRUPT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) data->pcm179x.generic.ext_power_bit = GPI_EXT_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) data->pcm179x.dacs = chip->model.dac_channels_mixer / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) data->pcm179x.h6 = chip->model.dac_channels_mixer > 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) pcm1796_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) GPIO_HDAV_MAGIC | GPIO_INPUT_ROUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_INPUT_ROUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) xonar_init_cs53x1(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) xonar_init_ext_power(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) xonar_hdmi_init(chip, &data->hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) xonar_enable_output(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) snd_component_add(chip->card, "PCM1796");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) snd_component_add(chip->card, "CS5381");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static void xonar_st_init_i2c(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) OXYGEN_2WIRE_LENGTH_8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) OXYGEN_2WIRE_INTERRUPT_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) OXYGEN_2WIRE_SPEED_STANDARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static void xonar_st_init_common(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) data->generic.output_enable_bit = GPIO_ST_OUTPUT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) data->dacs = chip->model.dac_channels_mixer / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) data->h6 = chip->model.dac_channels_mixer > 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) data->hp_gain_offset = 2*-18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) pcm1796_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) GPIO_INPUT_ROUTE | GPIO_ST_HP_REAR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) GPIO_ST_MAGIC | GPIO_ST_HP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) GPIO_INPUT_ROUTE | GPIO_ST_HP_REAR | GPIO_ST_HP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) xonar_init_cs53x1(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) xonar_enable_output(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) snd_component_add(chip->card, "PCM1792A");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) snd_component_add(chip->card, "CS5381");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static void cs2000_registers_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) cs2000_write(chip, CS2000_GLOBAL_CFG, CS2000_FREEZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) cs2000_write(chip, CS2000_DEV_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) cs2000_write(chip, CS2000_DEV_CFG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) CS2000_R_MOD_SEL_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) (0 << CS2000_R_SEL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) CS2000_AUX_OUT_SRC_REF_CLK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) CS2000_EN_DEV_CFG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) cs2000_write(chip, CS2000_DEV_CFG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) (0 << CS2000_LOCK_CLK_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) CS2000_FRAC_N_SRC_STATIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) cs2000_write(chip, CS2000_RATIO_0 + 0, 0x00); /* 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) cs2000_write(chip, CS2000_RATIO_0 + 1, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) cs2000_write(chip, CS2000_RATIO_0 + 2, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) cs2000_write(chip, CS2000_RATIO_0 + 3, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) cs2000_write(chip, CS2000_FUN_CFG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) data->cs2000_regs[CS2000_FUN_CFG_1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) cs2000_write(chip, CS2000_FUN_CFG_2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) cs2000_write(chip, CS2000_GLOBAL_CFG, CS2000_EN_DEV_CFG_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) msleep(3); /* PLL lock delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static void xonar_st_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) data->generic.anti_pop_delay = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) data->h6 = chip->model.dac_channels_mixer > 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) data->has_cs2000 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) data->cs2000_regs[CS2000_FUN_CFG_1] = CS2000_REF_CLK_DIV_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) data->broken_i2c = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) OXYGEN_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) OXYGEN_I2S_FORMAT_I2S |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) OXYGEN_I2S_MCLK(data->h6 ? MCLK_256 : MCLK_512) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) OXYGEN_I2S_BITS_16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) OXYGEN_I2S_MASTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) OXYGEN_I2S_BCLK_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) xonar_st_init_i2c(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) cs2000_registers_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) xonar_st_init_common(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) snd_component_add(chip->card, "CS2000");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static void xonar_stx_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) xonar_st_init_i2c(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) data->generic.anti_pop_delay = 800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) data->generic.ext_power_reg = OXYGEN_GPI_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) data->generic.ext_power_int_reg = OXYGEN_GPI_INTERRUPT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) data->generic.ext_power_bit = GPI_EXT_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) xonar_init_ext_power(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) xonar_st_init_common(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static void xonar_xense_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) data->generic.ext_power_reg = OXYGEN_GPI_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) data->generic.ext_power_int_reg = OXYGEN_GPI_INTERRUPT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) data->generic.ext_power_bit = GPI_EXT_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) xonar_init_ext_power(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) data->generic.anti_pop_delay = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) data->has_cs2000 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) data->cs2000_regs[CS2000_FUN_CFG_1] = CS2000_REF_CLK_DIV_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) OXYGEN_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) OXYGEN_I2S_FORMAT_I2S |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) OXYGEN_I2S_MCLK(MCLK_512) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) OXYGEN_I2S_BITS_16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) OXYGEN_I2S_MASTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) OXYGEN_I2S_BCLK_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) xonar_st_init_i2c(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) cs2000_registers_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) data->generic.output_enable_bit = GPIO_XENSE_OUTPUT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) data->dacs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) data->hp_gain_offset = 2*-18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pcm1796_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) GPIO_INPUT_ROUTE | GPIO_ST_HP_REAR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) GPIO_ST_MAGIC | GPIO_XENSE_SPEAKERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) GPIO_INPUT_ROUTE | GPIO_ST_HP_REAR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) GPIO_XENSE_SPEAKERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) xonar_init_cs53x1(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) xonar_enable_output(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) snd_component_add(chip->card, "PCM1796");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) snd_component_add(chip->card, "CS5381");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) snd_component_add(chip->card, "CS2000");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static void xonar_d2_cleanup(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) xonar_disable_output(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static void xonar_hdav_cleanup(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) xonar_hdmi_cleanup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) xonar_disable_output(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) msleep(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static void xonar_st_cleanup(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) xonar_disable_output(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static void xonar_d2_suspend(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) xonar_d2_cleanup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static void xonar_hdav_suspend(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) xonar_hdav_cleanup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static void xonar_st_suspend(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) xonar_st_cleanup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static void xonar_d2_resume(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) pcm1796_registers_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) xonar_enable_output(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static void xonar_hdav_resume(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct xonar_hdav *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) pcm1796_registers_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) xonar_hdmi_resume(chip, &data->hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) xonar_enable_output(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static void xonar_stx_resume(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) pcm1796_registers_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) xonar_enable_output(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static void xonar_st_resume(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) cs2000_registers_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) xonar_stx_resume(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static void update_pcm1796_oversampling(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (data->current_rate <= 48000 && !data->h6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) reg = PCM1796_OS_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) reg = PCM1796_OS_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) for (i = 0; i < data->dacs; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) pcm1796_write_cached(chip, i, 20, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static void update_pcm1796_deemph(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) reg = data->pcm1796_regs[0][18 - PCM1796_REG_BASE] & ~PCM1796_DMF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (data->current_rate == 48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) reg |= PCM1796_DMF_48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) else if (data->current_rate == 44100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) reg |= PCM1796_DMF_441;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) else if (data->current_rate == 32000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) reg |= PCM1796_DMF_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) for (i = 0; i < data->dacs; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) pcm1796_write_cached(chip, i, 18, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static void set_pcm1796_params(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) data->current_rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) update_pcm1796_oversampling(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) update_pcm1796_deemph(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static void update_pcm1796_volume(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) s8 gain_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) gain_offset = data->hp_active ? data->hp_gain_offset : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) for (i = 0; i < data->dacs; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) pcm1796_write_cached(chip, i, 16, chip->dac_volume[i * 2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) + gain_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) pcm1796_write_cached(chip, i, 17, chip->dac_volume[i * 2 + 1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) + gain_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) gain_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static void update_pcm1796_mute(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) value = data->pcm1796_regs[0][18 - PCM1796_REG_BASE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (chip->dac_mute)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) value |= PCM1796_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) value &= ~PCM1796_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) for (i = 0; i < data->dacs; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) pcm1796_write_cached(chip, i, 18, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static void update_cs2000_rate(struct oxygen *chip, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u8 rate_mclk, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) case 64000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) rate_mclk = OXYGEN_RATE_32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) case 176400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) rate_mclk = OXYGEN_RATE_44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) rate_mclk = OXYGEN_RATE_48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (rate <= 96000 && (rate > 48000 || data->h6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) rate_mclk |= OXYGEN_I2S_MCLK(MCLK_256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) reg = CS2000_REF_CLK_DIV_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) rate_mclk |= OXYGEN_I2S_MCLK(MCLK_512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) reg = CS2000_REF_CLK_DIV_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT, rate_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) OXYGEN_I2S_RATE_MASK | OXYGEN_I2S_MCLK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) cs2000_write_cached(chip, CS2000_FUN_CFG_1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) msleep(3); /* PLL lock delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static void set_st_params(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) update_cs2000_rate(chip, params_rate(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) set_pcm1796_params(chip, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static void set_hdav_params(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct xonar_hdav *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) set_pcm1796_params(chip, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) xonar_set_hdmi_params(chip, &data->hdmi, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static const struct snd_kcontrol_new alt_switch = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .name = "Analog Loopback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .info = snd_ctl_boolean_mono_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .get = xonar_gpio_bit_switch_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .put = xonar_gpio_bit_switch_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .private_value = GPIO_D2_ALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static int rolloff_info(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct snd_ctl_elem_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static const char *const names[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) "Sharp Roll-off", "Slow Roll-off"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return snd_ctl_enum_info(info, 1, 2, names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static int rolloff_get(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) value->value.enumerated.item[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) (data->pcm1796_regs[0][19 - PCM1796_REG_BASE] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) PCM1796_FLT_MASK) != PCM1796_FLT_SHARP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static int rolloff_put(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) reg = data->pcm1796_regs[0][19 - PCM1796_REG_BASE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) reg &= ~PCM1796_FLT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (!value->value.enumerated.item[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) reg |= PCM1796_FLT_SHARP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) reg |= PCM1796_FLT_SLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) changed = reg != data->pcm1796_regs[0][19 - PCM1796_REG_BASE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (changed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) for (i = 0; i < data->dacs; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) pcm1796_write(chip, i, 19, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static const struct snd_kcontrol_new rolloff_control = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .name = "DAC Filter Playback Enum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .info = rolloff_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .get = rolloff_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .put = rolloff_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static int deemph_get(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) value->value.integer.value[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) !!(data->pcm1796_regs[0][18 - PCM1796_REG_BASE] & PCM1796_DME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static int deemph_put(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) reg = data->pcm1796_regs[0][18 - PCM1796_REG_BASE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (!value->value.integer.value[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) reg &= ~PCM1796_DME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) reg |= PCM1796_DME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) changed = reg != data->pcm1796_regs[0][18 - PCM1796_REG_BASE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (changed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) for (i = 0; i < data->dacs; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) pcm1796_write(chip, i, 18, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static const struct snd_kcontrol_new deemph_control = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .name = "De-emphasis Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .info = snd_ctl_boolean_mono_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .get = deemph_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .put = deemph_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static const struct snd_kcontrol_new hdav_hdmi_control = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .name = "HDMI Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .info = snd_ctl_boolean_mono_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .get = xonar_gpio_bit_switch_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .put = xonar_gpio_bit_switch_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .private_value = GPIO_HDAV_OUTPUT_ENABLE | XONAR_GPIO_BIT_INVERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static int st_output_switch_info(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct snd_ctl_elem_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static const char *const names[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) "Speakers", "Headphones", "FP Headphones"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return snd_ctl_enum_info(info, 1, 3, names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static int st_output_switch_get(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) u16 gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) gpio = oxygen_read16(chip, OXYGEN_GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (!(gpio & GPIO_ST_HP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) value->value.enumerated.item[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) else if (gpio & GPIO_ST_HP_REAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) value->value.enumerated.item[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) value->value.enumerated.item[0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static int st_output_switch_put(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) u16 gpio_old, gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) gpio_old = oxygen_read16(chip, OXYGEN_GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) gpio = gpio_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) switch (value->value.enumerated.item[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) gpio &= ~(GPIO_ST_HP | GPIO_ST_HP_REAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) gpio |= GPIO_ST_HP | GPIO_ST_HP_REAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) gpio = (gpio | GPIO_ST_HP) & ~GPIO_ST_HP_REAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) oxygen_write16(chip, OXYGEN_GPIO_DATA, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) data->hp_active = gpio & GPIO_ST_HP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) update_pcm1796_volume(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return gpio != gpio_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static int st_hp_volume_offset_info(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct snd_ctl_elem_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static const char *const names[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) "< 32 ohms", "32-64 ohms", "64-300 ohms", "300-600 ohms"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return snd_ctl_enum_info(info, 1, 4, names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static int st_hp_volume_offset_get(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (data->hp_gain_offset < 2*-12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) value->value.enumerated.item[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) else if (data->hp_gain_offset < 2*-6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) value->value.enumerated.item[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) else if (data->hp_gain_offset < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) value->value.enumerated.item[0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) value->value.enumerated.item[0] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static int st_hp_volume_offset_put(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static const s8 offsets[] = { 2*-18, 2*-12, 2*-6, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) s8 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (value->value.enumerated.item[0] > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) offset = offsets[value->value.enumerated.item[0]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) changed = offset != data->hp_gain_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (changed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) data->hp_gain_offset = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) update_pcm1796_volume(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static const struct snd_kcontrol_new st_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .name = "Analog Output",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .info = st_output_switch_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .get = st_output_switch_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .put = st_output_switch_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .name = "Headphones Impedance Playback Enum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .info = st_hp_volume_offset_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .get = st_hp_volume_offset_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .put = st_hp_volume_offset_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static int xense_output_switch_get(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) u16 gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) gpio = oxygen_read16(chip, OXYGEN_GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (gpio & GPIO_XENSE_SPEAKERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) value->value.enumerated.item[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) else if (!(gpio & GPIO_XENSE_SPEAKERS) && (gpio & GPIO_ST_HP_REAR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) value->value.enumerated.item[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) value->value.enumerated.item[0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static int xense_output_switch_put(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) u16 gpio_old, gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) gpio_old = oxygen_read16(chip, OXYGEN_GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) gpio = gpio_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) switch (value->value.enumerated.item[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) gpio |= GPIO_XENSE_SPEAKERS | GPIO_ST_HP_REAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) gpio = (gpio | GPIO_ST_HP_REAR) & ~GPIO_XENSE_SPEAKERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) gpio &= ~(GPIO_XENSE_SPEAKERS | GPIO_ST_HP_REAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) oxygen_write16(chip, OXYGEN_GPIO_DATA, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) data->hp_active = !(gpio & GPIO_XENSE_SPEAKERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) update_pcm1796_volume(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return gpio != gpio_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static const struct snd_kcontrol_new xense_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .name = "Analog Output",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .info = st_output_switch_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .get = xense_output_switch_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .put = xense_output_switch_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .name = "Headphones Impedance Playback Enum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .info = st_hp_volume_offset_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .get = st_hp_volume_offset_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .put = st_hp_volume_offset_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static void xonar_line_mic_ac97_switch(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) unsigned int reg, unsigned int mute)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (reg == AC97_LINE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) oxygen_write16_masked(chip, OXYGEN_GPIO_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) mute ? GPIO_INPUT_ROUTE : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) GPIO_INPUT_ROUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static const DECLARE_TLV_DB_SCALE(pcm1796_db_scale, -6000, 50, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static int xonar_d2_control_filter(struct snd_kcontrol_new *template)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (!strncmp(template->name, "CD Capture ", 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* CD in is actually connected to the video in pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) template->private_value ^= AC97_CD ^ AC97_VIDEO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static int xonar_st_h6_control_filter(struct snd_kcontrol_new *template)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (!strncmp(template->name, "Master Playback ", 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* no volume/mute, as I²C to the third DAC does not work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static int add_pcm1796_controls(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (!data->broken_i2c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) err = snd_ctl_add(chip->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) snd_ctl_new1(&rolloff_control, chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) err = snd_ctl_add(chip->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) snd_ctl_new1(&deemph_control, chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static int xonar_d2_mixer_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) err = snd_ctl_add(chip->card, snd_ctl_new1(&alt_switch, chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) err = add_pcm1796_controls(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static int xonar_hdav_mixer_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) err = snd_ctl_add(chip->card, snd_ctl_new1(&hdav_hdmi_control, chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) err = add_pcm1796_controls(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static int xonar_st_mixer_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) for (i = 0; i < ARRAY_SIZE(st_controls); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) err = snd_ctl_add(chip->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) snd_ctl_new1(&st_controls[i], chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) err = add_pcm1796_controls(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static int xonar_xense_mixer_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) for (i = 0; i < ARRAY_SIZE(xense_controls); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) err = snd_ctl_add(chip->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) snd_ctl_new1(&xense_controls[i], chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) err = add_pcm1796_controls(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static void dump_pcm1796_registers(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) unsigned int dac, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) for (dac = 0; dac < data->dacs; ++dac) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) snd_iprintf(buffer, "\nPCM1796 %u:", dac + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) for (i = 0; i < 5; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) snd_iprintf(buffer, " %02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) data->pcm1796_regs[dac][i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) snd_iprintf(buffer, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static void dump_cs2000_registers(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) struct xonar_pcm179x *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (data->has_cs2000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) snd_iprintf(buffer, "\nCS2000:\n00: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) for (i = 1; i < 0x10; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) snd_iprintf(buffer, " %02x", data->cs2000_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) snd_iprintf(buffer, "\n10:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) for (i = 0x10; i < 0x1f; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) snd_iprintf(buffer, " %02x", data->cs2000_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) snd_iprintf(buffer, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static void dump_st_registers(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) dump_pcm1796_registers(chip, buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) dump_cs2000_registers(chip, buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static const struct oxygen_model model_xonar_d2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .longname = "Asus Virtuoso 200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .chip = "AV200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .init = xonar_d2_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .control_filter = xonar_d2_control_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .mixer_init = xonar_d2_mixer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .cleanup = xonar_d2_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .suspend = xonar_d2_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .resume = xonar_d2_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .set_dac_params = set_pcm1796_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .set_adc_params = xonar_set_cs53x1_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .update_dac_volume = update_pcm1796_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .update_dac_mute = update_pcm1796_mute,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .dump_registers = dump_pcm1796_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .dac_tlv = pcm1796_db_scale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .model_data_size = sizeof(struct xonar_pcm179x),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .device_config = PLAYBACK_0_TO_I2S |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) PLAYBACK_1_TO_SPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) CAPTURE_0_FROM_I2S_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) CAPTURE_1_FROM_SPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) MIDI_OUTPUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) MIDI_INPUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) AC97_CD_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .dac_channels_pcm = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .dac_channels_mixer = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .dac_volume_min = 255 - 2*60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .dac_volume_max = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .misc_flags = OXYGEN_MISC_MIDI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .function_flags = OXYGEN_FUNCTION_SPI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) OXYGEN_FUNCTION_ENABLE_SPI_4_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .dac_mclks = OXYGEN_MCLKS(512, 128, 128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .adc_mclks = OXYGEN_MCLKS(256, 128, 128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .dac_i2s_format = OXYGEN_I2S_FORMAT_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) static const struct oxygen_model model_xonar_hdav = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .longname = "Asus Virtuoso 200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .chip = "AV200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .init = xonar_hdav_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .mixer_init = xonar_hdav_mixer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .cleanup = xonar_hdav_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .suspend = xonar_hdav_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .resume = xonar_hdav_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .pcm_hardware_filter = xonar_hdmi_pcm_hardware_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .set_dac_params = set_hdav_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .set_adc_params = xonar_set_cs53x1_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .update_dac_volume = update_pcm1796_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .update_dac_mute = update_pcm1796_mute,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .uart_input = xonar_hdmi_uart_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .ac97_switch = xonar_line_mic_ac97_switch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .dump_registers = dump_pcm1796_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .dac_tlv = pcm1796_db_scale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .model_data_size = sizeof(struct xonar_hdav),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .device_config = PLAYBACK_0_TO_I2S |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) PLAYBACK_1_TO_SPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) CAPTURE_0_FROM_I2S_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) CAPTURE_1_FROM_SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .dac_channels_pcm = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .dac_channels_mixer = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .dac_volume_min = 255 - 2*60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .dac_volume_max = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .misc_flags = OXYGEN_MISC_MIDI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .function_flags = OXYGEN_FUNCTION_2WIRE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .dac_mclks = OXYGEN_MCLKS(512, 128, 128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .adc_mclks = OXYGEN_MCLKS(256, 128, 128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .dac_i2s_format = OXYGEN_I2S_FORMAT_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) static const struct oxygen_model model_xonar_st = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .longname = "Asus Virtuoso 100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .chip = "AV200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .init = xonar_st_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .mixer_init = xonar_st_mixer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .cleanup = xonar_st_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .suspend = xonar_st_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .resume = xonar_st_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .set_dac_params = set_st_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .set_adc_params = xonar_set_cs53x1_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .update_dac_volume = update_pcm1796_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .update_dac_mute = update_pcm1796_mute,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .ac97_switch = xonar_line_mic_ac97_switch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .dump_registers = dump_st_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .dac_tlv = pcm1796_db_scale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .model_data_size = sizeof(struct xonar_pcm179x),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .device_config = PLAYBACK_0_TO_I2S |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) PLAYBACK_1_TO_SPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) CAPTURE_0_FROM_I2S_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) CAPTURE_1_FROM_SPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) AC97_FMIC_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .dac_channels_pcm = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .dac_channels_mixer = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .dac_volume_min = 255 - 2*60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .dac_volume_max = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .function_flags = OXYGEN_FUNCTION_2WIRE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .dac_mclks = OXYGEN_MCLKS(512, 128, 128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .adc_mclks = OXYGEN_MCLKS(256, 128, 128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .dac_i2s_format = OXYGEN_I2S_FORMAT_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) int get_xonar_pcm179x_model(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) switch (id->subdevice) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) case 0x8269:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) chip->model = model_xonar_d2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) chip->model.shortname = "Xonar D2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) case 0x82b7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) chip->model = model_xonar_d2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) chip->model.shortname = "Xonar D2X";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) chip->model.init = xonar_d2x_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) case 0x8314:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) chip->model = model_xonar_hdav;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) oxygen_clear_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_DB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) switch (oxygen_read16(chip, OXYGEN_GPIO_DATA) & GPIO_DB_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) chip->model.shortname = "Xonar HDAV1.3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) case GPIO_DB_H6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) chip->model.shortname = "Xonar HDAV1.3+H6";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) chip->model.dac_channels_mixer = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) chip->model.dac_mclks = OXYGEN_MCLKS(256, 128, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) case 0x835d:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) chip->model = model_xonar_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) oxygen_clear_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_DB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) switch (oxygen_read16(chip, OXYGEN_GPIO_DATA) & GPIO_DB_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) chip->model.shortname = "Xonar ST";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) case GPIO_DB_H6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) chip->model.shortname = "Xonar ST+H6";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) chip->model.control_filter = xonar_st_h6_control_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) chip->model.dac_channels_pcm = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) chip->model.dac_channels_mixer = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) chip->model.dac_volume_min = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) chip->model.dac_mclks = OXYGEN_MCLKS(256, 128, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) case 0x835c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) chip->model = model_xonar_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) chip->model.shortname = "Xonar STX";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) chip->model.init = xonar_stx_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) chip->model.resume = xonar_stx_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) chip->model.set_dac_params = set_pcm1796_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) case 0x85f4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) chip->model = model_xonar_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) oxygen_clear_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_DB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) switch (oxygen_read16(chip, OXYGEN_GPIO_DATA) & GPIO_DB_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) chip->model.shortname = "Xonar STX II";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) case GPIO_DB_H6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) chip->model.shortname = "Xonar STX II+H6";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) chip->model.dac_channels_pcm = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) chip->model.dac_channels_mixer = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) chip->model.dac_mclks = OXYGEN_MCLKS(256, 128, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) chip->model.init = xonar_stx_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) chip->model.resume = xonar_stx_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) chip->model.set_dac_params = set_pcm1796_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) case 0x8428:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) chip->model = model_xonar_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) chip->model.shortname = "Xonar Xense";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) chip->model.chip = "AV100";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) chip->model.init = xonar_xense_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) chip->model.mixer_init = xonar_xense_mixer_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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