^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * card driver for the Xonar DG/DGX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) Roman Volkov <v1ron@mail.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Xonar DG/DGX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * ------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * CS4245 and CS4361 both will mute all outputs if any clock ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * is invalid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * CMI8788:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * SPI 0 -> CS4245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Playback:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * I²S 1 -> CS4245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * I²S 2 -> CS4361 (center/LFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * I²S 3 -> CS4361 (surround)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * I²S 4 -> CS4361 (front)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Capture:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * I²S ADC 1 <- CS4245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * GPIO 3 <- ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * GPIO 4 <- headphone detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * GPIO 5 -> enable ADC analog circuit for the left channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * GPIO 6 -> enable ADC analog circuit for the right channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * GPIO 7 -> switch green rear output jack between CS4245 and the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * channel of CS4361 (mechanical relay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * GPIO 8 -> enable output to speakers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * CS4245:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * input 0 <- mic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * input 1 <- aux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * input 2 <- front mic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * input 4 <- line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * DAC out -> headphones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * aux out -> front panel headphones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include "oxygen.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include "xonar_dg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include "cs4245.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int cs4245_write_spi(struct oxygen *chip, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct dg *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) packet = reg << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) packet |= (CS4245_SPI_ADDRESS | CS4245_SPI_WRITE) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) packet |= data->cs4245_shadow[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) OXYGEN_SPI_DATA_LENGTH_3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) OXYGEN_SPI_CLOCK_1280 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) (0 << OXYGEN_SPI_CODEC_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) OXYGEN_SPI_CEN_LATCH_CLOCK_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) packet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int cs4245_read_spi(struct oxygen *chip, u8 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct dg *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ret = oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) OXYGEN_SPI_DATA_LENGTH_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) OXYGEN_SPI_CEN_LATCH_CLOCK_HI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) OXYGEN_SPI_CLOCK_1280 | (0 << OXYGEN_SPI_CODEC_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ((CS4245_SPI_ADDRESS | CS4245_SPI_WRITE) << 8) | addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ret = oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) OXYGEN_SPI_DATA_LENGTH_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) OXYGEN_SPI_CEN_LATCH_CLOCK_HI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) OXYGEN_SPI_CLOCK_1280 | (0 << OXYGEN_SPI_CODEC_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) (CS4245_SPI_ADDRESS | CS4245_SPI_READ) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) data->cs4245_shadow[addr] = oxygen_read8(chip, OXYGEN_SPI_DATA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int cs4245_shadow_control(struct oxygen *chip, enum cs4245_shadow_operation op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct dg *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned char addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) for (addr = 1; addr < ARRAY_SIZE(data->cs4245_shadow); addr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = (op == CS4245_SAVE_TO_SHADOW ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) cs4245_read_spi(chip, addr) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) cs4245_write_spi(chip, addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void cs4245_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct dg *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* save the initial state: codec version, registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) cs4245_shadow_control(chip, CS4245_SAVE_TO_SHADOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Power up the CODEC internals, enable soft ramp & zero cross, work in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * async. mode, enable aux output from DAC. Invert DAC output as in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Windows driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) data->cs4245_shadow[CS4245_POWER_CTRL] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) data->cs4245_shadow[CS4245_SIGNAL_SEL] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) CS4245_A_OUT_SEL_DAC | CS4245_ASYNCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) data->cs4245_shadow[CS4245_DAC_CTRL_1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) CS4245_DAC_FM_SINGLE | CS4245_DAC_DIF_LJUST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) data->cs4245_shadow[CS4245_DAC_CTRL_2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) CS4245_DAC_SOFT | CS4245_DAC_ZERO | CS4245_INVERT_DAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) data->cs4245_shadow[CS4245_ADC_CTRL] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) CS4245_ADC_FM_SINGLE | CS4245_ADC_DIF_LJUST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) data->cs4245_shadow[CS4245_ANALOG_IN] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) CS4245_PGA_SOFT | CS4245_PGA_ZERO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) data->cs4245_shadow[CS4245_PGA_B_CTRL] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) data->cs4245_shadow[CS4245_PGA_A_CTRL] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) data->cs4245_shadow[CS4245_DAC_A_CTRL] = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) data->cs4245_shadow[CS4245_DAC_B_CTRL] = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) cs4245_shadow_control(chip, CS4245_LOAD_FROM_SHADOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) snd_component_add(chip->card, "CS4245");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) void dg_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct dg *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) data->output_sel = PLAYBACK_DST_HP_FP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) data->input_sel = CAPTURE_SRC_MIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) cs4245_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) oxygen_write16(chip, OXYGEN_GPIO_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) GPIO_OUTPUT_ENABLE | GPIO_HP_REAR | GPIO_INPUT_ROUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* anti-pop delay, wait some time before enabling the output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) msleep(2500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) oxygen_write16(chip, OXYGEN_GPIO_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) GPIO_OUTPUT_ENABLE | GPIO_INPUT_ROUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) void dg_cleanup(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_OUTPUT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) void dg_suspend(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dg_cleanup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) void dg_resume(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) cs4245_shadow_control(chip, CS4245_LOAD_FROM_SHADOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) msleep(2500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) oxygen_set_bits16(chip, OXYGEN_GPIO_DATA, GPIO_OUTPUT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void set_cs4245_dac_params(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct dg *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned char dac_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned char mclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dac_ctrl = data->cs4245_shadow[CS4245_DAC_CTRL_1] & ~CS4245_DAC_FM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mclk_freq = data->cs4245_shadow[CS4245_MCLK_FREQ] & ~CS4245_MCLK1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (params_rate(params) <= 50000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dac_ctrl |= CS4245_DAC_FM_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) mclk_freq |= CS4245_MCLK_1 << CS4245_MCLK1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) } else if (params_rate(params) <= 100000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dac_ctrl |= CS4245_DAC_FM_DOUBLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mclk_freq |= CS4245_MCLK_1 << CS4245_MCLK1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dac_ctrl |= CS4245_DAC_FM_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mclk_freq |= CS4245_MCLK_2 << CS4245_MCLK1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) data->cs4245_shadow[CS4245_DAC_CTRL_1] = dac_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) data->cs4245_shadow[CS4245_MCLK_FREQ] = mclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) cs4245_write_spi(chip, CS4245_DAC_CTRL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) cs4245_write_spi(chip, CS4245_MCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) void set_cs4245_adc_params(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct dg *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned char adc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned char mclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) adc_ctrl = data->cs4245_shadow[CS4245_ADC_CTRL] & ~CS4245_ADC_FM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mclk_freq = data->cs4245_shadow[CS4245_MCLK_FREQ] & ~CS4245_MCLK2_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (params_rate(params) <= 50000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) adc_ctrl |= CS4245_ADC_FM_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mclk_freq |= CS4245_MCLK_1 << CS4245_MCLK2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) } else if (params_rate(params) <= 100000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) adc_ctrl |= CS4245_ADC_FM_DOUBLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mclk_freq |= CS4245_MCLK_1 << CS4245_MCLK2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) adc_ctrl |= CS4245_ADC_FM_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) mclk_freq |= CS4245_MCLK_2 << CS4245_MCLK2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) data->cs4245_shadow[CS4245_ADC_CTRL] = adc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) data->cs4245_shadow[CS4245_MCLK_FREQ] = mclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) cs4245_write_spi(chip, CS4245_ADC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) cs4245_write_spi(chip, CS4245_MCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static inline unsigned int shift_bits(unsigned int value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned int shift_from,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned int shift_to,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (shift_from < shift_to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return (value << (shift_to - shift_from)) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return (value >> (shift_from - shift_to)) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned int adjust_dg_dac_routing(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned int play_routing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct dg *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) switch (data->output_sel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case PLAYBACK_DST_HP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case PLAYBACK_DST_HP_FP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) oxygen_write8_masked(chip, OXYGEN_PLAY_ROUTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) OXYGEN_PLAY_MUTE23 | OXYGEN_PLAY_MUTE45 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) OXYGEN_PLAY_MUTE67, OXYGEN_PLAY_MUTE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case PLAYBACK_DST_MULTICH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) oxygen_write8_masked(chip, OXYGEN_PLAY_ROUTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) OXYGEN_PLAY_MUTE01, OXYGEN_PLAY_MUTE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return (play_routing & OXYGEN_PLAY_DAC0_SOURCE_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) shift_bits(play_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) OXYGEN_PLAY_DAC2_SOURCE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) OXYGEN_PLAY_DAC1_SOURCE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) OXYGEN_PLAY_DAC1_SOURCE_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) shift_bits(play_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) OXYGEN_PLAY_DAC1_SOURCE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) OXYGEN_PLAY_DAC2_SOURCE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) OXYGEN_PLAY_DAC2_SOURCE_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) shift_bits(play_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) OXYGEN_PLAY_DAC0_SOURCE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) OXYGEN_PLAY_DAC3_SOURCE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) OXYGEN_PLAY_DAC3_SOURCE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) void dump_cs4245_registers(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct dg *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) snd_iprintf(buffer, "\nCS4245:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) cs4245_read_spi(chip, CS4245_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) for (addr = 1; addr < ARRAY_SIZE(data->cs4245_shadow); addr++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) snd_iprintf(buffer, " %02x", data->cs4245_shadow[addr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) snd_iprintf(buffer, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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