^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef WM8776_H_INCLUDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define WM8776_H_INCLUDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * the following register names are from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * wm8776.h -- WM8776 ASoC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2009 Wolfson Microelectronics plc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define WM8776_HPLVOL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define WM8776_HPRVOL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define WM8776_HPMASTER 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define WM8776_DACLVOL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define WM8776_DACRVOL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define WM8776_DACMASTER 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define WM8776_PHASESWAP 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define WM8776_DACCTRL1 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define WM8776_DACMUTE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define WM8776_DACCTRL2 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define WM8776_DACIFCTRL 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define WM8776_ADCIFCTRL 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WM8776_MSTRCTRL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define WM8776_PWRDOWN 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define WM8776_ADCLVOL 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define WM8776_ADCRVOL 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define WM8776_ALCCTRL1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define WM8776_ALCCTRL2 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define WM8776_ALCCTRL3 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define WM8776_NOISEGATE 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define WM8776_LIMITER 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define WM8776_ADCMUX 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define WM8776_OUTMUX 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define WM8776_RESET 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* HPLVOL/HPRVOL/HPMASTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define WM8776_HPATT_MASK 0x07f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define WM8776_HPZCEN 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define WM8776_UPDATE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* DACLVOL/DACRVOL/DACMASTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define WM8776_DATT_MASK 0x0ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*#define WM8776_UPDATE 0x100*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* PHASESWAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define WM8776_PH_MASK 0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* DACCTRL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define WM8776_DZCEN 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define WM8776_ATC 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define WM8776_IZD 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define WM8776_TOD 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define WM8776_PL_LEFT_MASK 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define WM8776_PL_LEFT_MUTE 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define WM8776_PL_LEFT_LEFT 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define WM8776_PL_LEFT_RIGHT 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define WM8776_PL_LEFT_LRMIX 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define WM8776_PL_RIGHT_MASK 0x0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define WM8776_PL_RIGHT_MUTE 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define WM8776_PL_RIGHT_LEFT 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define WM8776_PL_RIGHT_RIGHT 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define WM8776_PL_RIGHT_LRMIX 0x0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* DACMUTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define WM8776_DMUTE 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* DACCTRL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define WM8776_DEEMPH 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define WM8776_DZFM_MASK 0x006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define WM8776_DZFM_NONE 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define WM8776_DZFM_LR 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define WM8776_DZFM_BOTH 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define WM8776_DZFM_EITHER 0x006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* DACIFCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define WM8776_DACFMT_MASK 0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define WM8776_DACFMT_RJUST 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define WM8776_DACFMT_LJUST 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define WM8776_DACFMT_I2S 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define WM8776_DACFMT_DSP 0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define WM8776_DACLRP 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define WM8776_DACBCP 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define WM8776_DACWL_MASK 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define WM8776_DACWL_16 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define WM8776_DACWL_20 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define WM8776_DACWL_24 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define WM8776_DACWL_32 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* ADCIFCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define WM8776_ADCFMT_MASK 0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define WM8776_ADCFMT_RJUST 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define WM8776_ADCFMT_LJUST 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define WM8776_ADCFMT_I2S 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define WM8776_ADCFMT_DSP 0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define WM8776_ADCLRP 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define WM8776_ADCBCP 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define WM8776_ADCWL_MASK 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define WM8776_ADCWL_16 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define WM8776_ADCWL_20 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define WM8776_ADCWL_24 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define WM8776_ADCWL_32 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define WM8776_ADCMCLK 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define WM8776_ADCHPD 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* MSTRCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define WM8776_ADCRATE_MASK 0x007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define WM8776_ADCRATE_256 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define WM8776_ADCRATE_384 0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define WM8776_ADCRATE_512 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define WM8776_ADCRATE_768 0x005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define WM8776_ADCOSR 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define WM8776_DACRATE_MASK 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define WM8776_DACRATE_128 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define WM8776_DACRATE_192 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define WM8776_DACRATE_256 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define WM8776_DACRATE_384 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define WM8776_DACRATE_512 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define WM8776_DACRATE_768 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define WM8776_DACMS 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define WM8776_ADCMS 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* PWRDOWN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define WM8776_PDWN 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define WM8776_ADCPD 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define WM8776_DACPD 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define WM8776_HPPD 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define WM8776_AINPD 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* ADCLVOL/ADCRVOL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define WM8776_AGMASK 0x0ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define WM8776_ZCA 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* ALCCTRL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define WM8776_LCT_MASK 0x00f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define WM8776_MAXGAIN_MASK 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define WM8776_LCSEL_MASK 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define WM8776_LCSEL_LIMITER 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define WM8776_LCSEL_ALC_RIGHT 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define WM8776_LCSEL_ALC_LEFT 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define WM8776_LCSEL_ALC_STEREO 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* ALCCTRL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define WM8776_HLD_MASK 0x00f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define WM8776_ALCZC 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define WM8776_LCEN 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* ALCCTRL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define WM8776_ATK_MASK 0x00f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define WM8776_DCY_MASK 0x0f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* NOISEGATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define WM8776_NGAT 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define WM8776_NGTH_MASK 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* LIMITER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define WM8776_MAXATTEN_MASK 0x00f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define WM8776_TRANWIN_MASK 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* ADCMUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define WM8776_AMX_MASK 0x01f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define WM8776_MUTERA 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define WM8776_MUTELA 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define WM8776_LRBOTH 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* OUTMUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define WM8776_MX_DAC 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define WM8776_MX_AUX 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define WM8776_MX_BYPASS 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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