^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef WM8766_H_INCLUDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define WM8766_H_INCLUDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define WM8766_LDA1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define WM8766_RDA1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define WM8766_DAC_CTRL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define WM8766_INT_CTRL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define WM8766_LDA2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define WM8766_RDA2 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define WM8766_LDA3 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define WM8766_RDA3 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define WM8766_MASTDA 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define WM8766_DAC_CTRL2 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define WM8766_DAC_CTRL3 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define WM8766_MUTE1 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define WM8766_MUTE2 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define WM8766_RESET 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* LDAx/RDAx/MASTDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define WM8766_ATT_MASK 0x0ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define WM8766_UPDATE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* DAC_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define WM8766_MUTEALL 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define WM8766_DEEMPALL 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WM8766_PWDN 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define WM8766_ATC 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define WM8766_IZD 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define WM8766_PL_LEFT_MASK 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define WM8766_PL_LEFT_MUTE 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define WM8766_PL_LEFT_LEFT 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define WM8766_PL_LEFT_RIGHT 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define WM8766_PL_LEFT_LRMIX 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define WM8766_PL_RIGHT_MASK 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define WM8766_PL_RIGHT_MUTE 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define WM8766_PL_RIGHT_LEFT 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define WM8766_PL_RIGHT_RIGHT 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define WM8766_PL_RIGHT_LRMIX 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* INT_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define WM8766_FMT_MASK 0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define WM8766_FMT_RJUST 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define WM8766_FMT_LJUST 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define WM8766_FMT_I2S 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define WM8766_FMT_DSP 0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define WM8766_LRP 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define WM8766_BCP 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define WM8766_IWL_MASK 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define WM8766_IWL_16 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define WM8766_IWL_20 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define WM8766_IWL_24 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define WM8766_IWL_32 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define WM8766_PHASE_MASK 0x1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* DAC_CTRL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define WM8766_ZCD 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define WM8766_DZFM_MASK 0x006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define WM8766_DMUTE_MASK 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define WM8766_DEEMP_MASK 0x1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* DAC_CTRL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define WM8766_DACPD_MASK 0x00e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define WM8766_PWRDNALL 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define WM8766_MS 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define WM8766_RATE_MASK 0x1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define WM8766_RATE_128 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define WM8766_RATE_192 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define WM8766_RATE_256 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define WM8766_RATE_384 0x0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define WM8766_RATE_512 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define WM8766_RATE_768 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* MUTE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define WM8766_MPD1 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* MUTE2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define WM8766_MPD2 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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