Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef OXYGEN_REGS_H_INCLUDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define OXYGEN_REGS_H_INCLUDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) /* recording channel A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define OXYGEN_DMA_A_ADDRESS		0x00	/* 32-bit base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define OXYGEN_DMA_A_COUNT		0x04	/* buffer counter (dwords) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define OXYGEN_DMA_A_TCOUNT		0x06	/* interrupt counter (dwords) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /* recording channel B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define OXYGEN_DMA_B_ADDRESS		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define OXYGEN_DMA_B_COUNT		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define OXYGEN_DMA_B_TCOUNT		0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /* recording channel C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define OXYGEN_DMA_C_ADDRESS		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define OXYGEN_DMA_C_COUNT		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define OXYGEN_DMA_C_TCOUNT		0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* SPDIF playback channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define OXYGEN_DMA_SPDIF_ADDRESS	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define OXYGEN_DMA_SPDIF_COUNT		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define OXYGEN_DMA_SPDIF_TCOUNT		0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* multichannel playback channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define OXYGEN_DMA_MULTICH_ADDRESS	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define OXYGEN_DMA_MULTICH_COUNT	0x24	/* 24 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define OXYGEN_DMA_MULTICH_TCOUNT	0x28	/* 24 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* AC'97 (front panel) playback channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define OXYGEN_DMA_AC97_ADDRESS		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define OXYGEN_DMA_AC97_COUNT		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define OXYGEN_DMA_AC97_TCOUNT		0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* all registers 0x00..0x36 return current position on read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define OXYGEN_DMA_STATUS		0x40	/* 1 = running, 0 = stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define  OXYGEN_CHANNEL_A		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define  OXYGEN_CHANNEL_B		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define  OXYGEN_CHANNEL_C		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define  OXYGEN_CHANNEL_SPDIF		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define  OXYGEN_CHANNEL_MULTICH		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define  OXYGEN_CHANNEL_AC97		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define OXYGEN_DMA_PAUSE		0x41	/* 1 = pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* OXYGEN_CHANNEL_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define OXYGEN_DMA_RESET		0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /* OXYGEN_CHANNEL_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define OXYGEN_PLAY_CHANNELS		0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define  OXYGEN_PLAY_CHANNELS_MASK	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define  OXYGEN_PLAY_CHANNELS_2		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define  OXYGEN_PLAY_CHANNELS_4		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define  OXYGEN_PLAY_CHANNELS_6		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define  OXYGEN_PLAY_CHANNELS_8		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define  OXYGEN_DMA_A_BURST_MASK	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define  OXYGEN_DMA_A_BURST_8		0x00	/* dwords */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define  OXYGEN_DMA_A_BURST_16		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define  OXYGEN_DMA_MULTICH_BURST_MASK	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define  OXYGEN_DMA_MULTICH_BURST_8	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define  OXYGEN_DMA_MULTICH_BURST_16	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define OXYGEN_INTERRUPT_MASK		0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* OXYGEN_CHANNEL_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define  OXYGEN_INT_SPDIF_IN_DETECT	0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define  OXYGEN_INT_MCU			0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define  OXYGEN_INT_2WIRE		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define  OXYGEN_INT_GPIO		0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define  OXYGEN_INT_MCB			0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define  OXYGEN_INT_AC97		0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define OXYGEN_INTERRUPT_STATUS		0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* OXYGEN_CHANNEL_* amd OXYGEN_INT_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define  OXYGEN_INT_MIDI		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define OXYGEN_MISC			0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define  OXYGEN_MISC_WRITE_PCI_SUBID	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define  OXYGEN_MISC_LATENCY_3F		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define  OXYGEN_MISC_REC_C_FROM_SPDIF	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define  OXYGEN_MISC_REC_B_FROM_AC97	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define  OXYGEN_MISC_REC_A_FROM_MULTICH	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define  OXYGEN_MISC_PCI_MEM_W_1_CLOCK	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define  OXYGEN_MISC_MIDI		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define  OXYGEN_MISC_CRYSTAL_MASK	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define  OXYGEN_MISC_CRYSTAL_24576	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define  OXYGEN_MISC_CRYSTAL_27		0x80	/* MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define OXYGEN_REC_FORMAT		0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define  OXYGEN_REC_FORMAT_A_MASK	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define  OXYGEN_REC_FORMAT_A_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define  OXYGEN_REC_FORMAT_B_MASK	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define  OXYGEN_REC_FORMAT_B_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define  OXYGEN_REC_FORMAT_C_MASK	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define  OXYGEN_REC_FORMAT_C_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define  OXYGEN_FORMAT_16		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define  OXYGEN_FORMAT_24		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define  OXYGEN_FORMAT_32		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OXYGEN_PLAY_FORMAT		0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define  OXYGEN_SPDIF_FORMAT_MASK	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define  OXYGEN_SPDIF_FORMAT_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define  OXYGEN_MULTICH_FORMAT_MASK	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define  OXYGEN_MULTICH_FORMAT_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* OXYGEN_FORMAT_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OXYGEN_REC_CHANNELS		0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define  OXYGEN_REC_CHANNELS_MASK	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define  OXYGEN_REC_CHANNELS_2_2_2	0x00	/* DMA A, B, C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define  OXYGEN_REC_CHANNELS_4_2_2	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define  OXYGEN_REC_CHANNELS_6_0_2	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define  OXYGEN_REC_CHANNELS_6_2_0	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define  OXYGEN_REC_CHANNELS_8_0_0	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OXYGEN_FUNCTION			0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define  OXYGEN_FUNCTION_CLOCK_MASK	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define  OXYGEN_FUNCTION_CLOCK_PLL	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define  OXYGEN_FUNCTION_CLOCK_CRYSTAL	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define  OXYGEN_FUNCTION_RESET_CODEC	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define  OXYGEN_FUNCTION_RESET_POL	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define  OXYGEN_FUNCTION_PWDN		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define  OXYGEN_FUNCTION_PWDN_EN	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define  OXYGEN_FUNCTION_PWDN_POL	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define  OXYGEN_FUNCTION_2WIRE_SPI_MASK	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define  OXYGEN_FUNCTION_SPI		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define  OXYGEN_FUNCTION_2WIRE		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define  OXYGEN_FUNCTION_ENABLE_SPI_4_5	0x80	/* 0 = EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OXYGEN_I2S_MULTICH_FORMAT	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define  OXYGEN_I2S_RATE_MASK		0x0007	/* LRCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define  OXYGEN_RATE_32000		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define  OXYGEN_RATE_44100		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define  OXYGEN_RATE_48000		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define  OXYGEN_RATE_64000		0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define  OXYGEN_RATE_88200		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define  OXYGEN_RATE_96000		0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define  OXYGEN_RATE_176400		0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define  OXYGEN_RATE_192000		0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define  OXYGEN_I2S_FORMAT_MASK		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define  OXYGEN_I2S_FORMAT_I2S		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define  OXYGEN_I2S_FORMAT_LJUST	0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define  OXYGEN_I2S_MCLK_MASK		0x0030	/* MCLK/LRCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define  OXYGEN_I2S_MCLK_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define  MCLK_128			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define  MCLK_256			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define  MCLK_512			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define  OXYGEN_I2S_MCLK(f)		(((f) & 3) << OXYGEN_I2S_MCLK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define  OXYGEN_I2S_BITS_MASK		0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define  OXYGEN_I2S_BITS_16		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define  OXYGEN_I2S_BITS_20		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define  OXYGEN_I2S_BITS_24		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define  OXYGEN_I2S_BITS_32		0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define  OXYGEN_I2S_MASTER		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define  OXYGEN_I2S_BCLK_MASK		0x0600	/* BCLK/LRCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define  OXYGEN_I2S_BCLK_64		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define  OXYGEN_I2S_BCLK_128		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define  OXYGEN_I2S_BCLK_256		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define  OXYGEN_I2S_MUTE_MCLK		0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define OXYGEN_I2S_A_FORMAT		0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define OXYGEN_I2S_B_FORMAT		0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define OXYGEN_I2S_C_FORMAT		0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* like OXYGEN_I2S_MULTICH_FORMAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define OXYGEN_SPDIF_CONTROL		0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define  OXYGEN_SPDIF_OUT_ENABLE	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define  OXYGEN_SPDIF_LOOPBACK		0x00000004	/* in to out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define  OXYGEN_SPDIF_SENSE_MASK	0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define  OXYGEN_SPDIF_LOCK_MASK		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define  OXYGEN_SPDIF_RATE_MASK		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define  OXYGEN_SPDIF_SPDVALID		0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define  OXYGEN_SPDIF_SENSE_PAR		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define  OXYGEN_SPDIF_LOCK_PAR		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define  OXYGEN_SPDIF_SENSE_STATUS	0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define  OXYGEN_SPDIF_LOCK_STATUS	0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define  OXYGEN_SPDIF_SENSE_INT		0x00002000	/* r/wc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define  OXYGEN_SPDIF_LOCK_INT		0x00004000	/* r/wc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define  OXYGEN_SPDIF_RATE_INT		0x00008000	/* r/wc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define  OXYGEN_SPDIF_IN_CLOCK_MASK	0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define  OXYGEN_SPDIF_IN_CLOCK_96	0x00000000	/* <= 96 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define  OXYGEN_SPDIF_IN_CLOCK_192	0x00010000	/* > 96 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define  OXYGEN_SPDIF_OUT_RATE_MASK	0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define  OXYGEN_SPDIF_OUT_RATE_SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* OXYGEN_RATE_* << OXYGEN_SPDIF_OUT_RATE_SHIFT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define OXYGEN_SPDIF_OUTPUT_BITS	0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define  OXYGEN_SPDIF_NONAUDIO		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define  OXYGEN_SPDIF_C			0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define  OXYGEN_SPDIF_PREEMPHASIS	0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define  OXYGEN_SPDIF_CATEGORY_MASK	0x000007f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define  OXYGEN_SPDIF_CATEGORY_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define  OXYGEN_SPDIF_ORIGINAL		0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define  OXYGEN_SPDIF_CS_RATE_MASK	0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define  OXYGEN_SPDIF_CS_RATE_SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define  OXYGEN_SPDIF_V			0x00010000	/* 0 = valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define OXYGEN_SPDIF_INPUT_BITS		0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* 32 bits, IEC958_AES_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define OXYGEN_EEPROM_CONTROL		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define  OXYGEN_EEPROM_ADDRESS_MASK	0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define  OXYGEN_EEPROM_DIR_MASK		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define  OXYGEN_EEPROM_DIR_READ		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define  OXYGEN_EEPROM_DIR_WRITE	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define OXYGEN_EEPROM_STATUS		0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define  OXYGEN_EEPROM_VALID		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define  OXYGEN_EEPROM_BUSY		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define OXYGEN_EEPROM_DATA		0x82	/* 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define OXYGEN_2WIRE_CONTROL		0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define  OXYGEN_2WIRE_DIR_MASK		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define  OXYGEN_2WIRE_DIR_WRITE		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define  OXYGEN_2WIRE_DIR_READ		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define  OXYGEN_2WIRE_ADDRESS_MASK	0xfe	/* slave device address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define  OXYGEN_2WIRE_ADDRESS_SHIFT	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define OXYGEN_2WIRE_MAP		0x91	/* address, 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define OXYGEN_2WIRE_DATA		0x92	/* data, 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define OXYGEN_2WIRE_BUS_STATUS		0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define  OXYGEN_2WIRE_BUSY		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define  OXYGEN_2WIRE_LENGTH_MASK	0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define  OXYGEN_2WIRE_LENGTH_8		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define  OXYGEN_2WIRE_LENGTH_16		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define  OXYGEN_2WIRE_MANUAL_READ	0x0004	/* 0 = auto read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define  OXYGEN_2WIRE_WRITE_MAP_ONLY	0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define  OXYGEN_2WIRE_SLAVE_AD_MASK	0x0030	/* AD0, AD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define  OXYGEN_2WIRE_INTERRUPT_MASK	0x0040	/* 0 = int. if not responding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define  OXYGEN_2WIRE_SLAVE_NO_RESPONSE	0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define  OXYGEN_2WIRE_SPEED_MASK	0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define  OXYGEN_2WIRE_SPEED_STANDARD	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define  OXYGEN_2WIRE_SPEED_FAST	0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define  OXYGEN_2WIRE_CLOCK_SYNC	0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define  OXYGEN_2WIRE_BUS_RESET		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define OXYGEN_SPI_CONTROL		0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define  OXYGEN_SPI_BUSY		0x01	/* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define  OXYGEN_SPI_TRIGGER		0x01	/* write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define  OXYGEN_SPI_DATA_LENGTH_MASK	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define  OXYGEN_SPI_DATA_LENGTH_2	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define  OXYGEN_SPI_DATA_LENGTH_3	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define  OXYGEN_SPI_CLOCK_MASK		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define  OXYGEN_SPI_CLOCK_160		0x00	/* ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define  OXYGEN_SPI_CLOCK_320		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define  OXYGEN_SPI_CLOCK_640		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define  OXYGEN_SPI_CLOCK_1280		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define  OXYGEN_SPI_CODEC_MASK		0x70	/* 0..5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define  OXYGEN_SPI_CODEC_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define  OXYGEN_SPI_CEN_MASK		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define  OXYGEN_SPI_CEN_LATCH_CLOCK_LO	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define  OXYGEN_SPI_CEN_LATCH_CLOCK_HI	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define OXYGEN_SPI_DATA1		0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define OXYGEN_SPI_DATA2		0x9a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define OXYGEN_SPI_DATA3		0x9b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define OXYGEN_MPU401			0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define OXYGEN_MPU401_CONTROL		0xa2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define  OXYGEN_MPU401_LOOPBACK		0x01	/* TXD to RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define OXYGEN_GPI_DATA			0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* bits 0..5 = pin XGPI0..XGPI5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define OXYGEN_GPI_INTERRUPT_MASK	0xa5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* bits 0..5, 1 = enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define OXYGEN_GPIO_DATA		0xa6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* bits 0..9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define OXYGEN_GPIO_CONTROL		0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* bits 0..9, 0 = input, 1 = output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define  OXYGEN_GPIO1_XSLAVE_RDY	0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define OXYGEN_GPIO_INTERRUPT_MASK	0xaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* bits 0..9, 1 = enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define OXYGEN_DEVICE_SENSE		0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define  OXYGEN_HEAD_PHONE_DETECT	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define  OXYGEN_HEAD_PHONE_MASK		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define  OXYGEN_HEAD_PHONE_PASSIVE_SPK	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define  OXYGEN_HEAD_PHONE_HP		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define  OXYGEN_HEAD_PHONE_ACTIVE_SPK	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define OXYGEN_MCU_2WIRE_DATA		0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define OXYGEN_MCU_2WIRE_MAP		0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define OXYGEN_MCU_2WIRE_STATUS		0xb3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define  OXYGEN_MCU_2WIRE_BUSY		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define  OXYGEN_MCU_2WIRE_LENGTH_MASK	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define  OXYGEN_MCU_2WIRE_LENGTH_1	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define  OXYGEN_MCU_2WIRE_LENGTH_2	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define  OXYGEN_MCU_2WIRE_LENGTH_3	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define  OXYGEN_MCU_2WIRE_WRITE		0x08	/* r/wc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define  OXYGEN_MCU_2WIRE_READ		0x10	/* r/wc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define  OXYGEN_MCU_2WIRE_DRV_XACT_FAIL	0x20	/* r/wc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define  OXYGEN_MCU_2WIRE_RESET		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define OXYGEN_MCU_2WIRE_CONTROL	0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define  OXYGEN_MCU_2WIRE_DRV_ACK	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define  OXYGEN_MCU_2WIRE_DRV_XACT	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define  OXYGEN_MCU_2WIRE_INT_MASK	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define  OXYGEN_MCU_2WIRE_SYNC_MASK	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define  OXYGEN_MCU_2WIRE_SYNC_RDY_PIN	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define  OXYGEN_MCU_2WIRE_SYNC_DATA	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define  OXYGEN_MCU_2WIRE_ADDRESS_MASK	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define  OXYGEN_MCU_2WIRE_ADDRESS_10	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define  OXYGEN_MCU_2WIRE_ADDRESS_12	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define  OXYGEN_MCU_2WIRE_ADDRESS_14	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define  OXYGEN_MCU_2WIRE_ADDRESS_16	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define  OXYGEN_MCU_2WIRE_INT_POL	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define  OXYGEN_MCU_2WIRE_SYNC_ENABLE	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define OXYGEN_PLAY_ROUTING		0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define  OXYGEN_PLAY_MUTE01		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define  OXYGEN_PLAY_MUTE23		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define  OXYGEN_PLAY_MUTE45		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define  OXYGEN_PLAY_MUTE67		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define  OXYGEN_PLAY_MUTE_MASK		0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define  OXYGEN_PLAY_MULTICH_MASK	0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define  OXYGEN_PLAY_MULTICH_I2S_DAC	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define  OXYGEN_PLAY_MULTICH_AC97	0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define  OXYGEN_PLAY_SPDIF_MASK		0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define  OXYGEN_PLAY_SPDIF_SPDIF	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define  OXYGEN_PLAY_SPDIF_MULTICH_01	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define  OXYGEN_PLAY_SPDIF_MULTICH_23	0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define  OXYGEN_PLAY_SPDIF_MULTICH_45	0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define  OXYGEN_PLAY_SPDIF_MULTICH_67	0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define  OXYGEN_PLAY_SPDIF_REC_A	0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define  OXYGEN_PLAY_SPDIF_REC_B	0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define  OXYGEN_PLAY_SPDIF_I2S_ADC_3	0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define  OXYGEN_PLAY_DAC0_SOURCE_MASK	0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define  OXYGEN_PLAY_DAC0_SOURCE_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define  OXYGEN_PLAY_DAC1_SOURCE_MASK	0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define  OXYGEN_PLAY_DAC1_SOURCE_SHIFT	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define  OXYGEN_PLAY_DAC2_SOURCE_MASK	0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define  OXYGEN_PLAY_DAC2_SOURCE_SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define  OXYGEN_PLAY_DAC3_SOURCE_MASK	0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define  OXYGEN_PLAY_DAC3_SOURCE_SHIFT	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define OXYGEN_REC_ROUTING		0xc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define  OXYGEN_MUTE_I2S_ADC_1		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define  OXYGEN_MUTE_I2S_ADC_2		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define  OXYGEN_MUTE_I2S_ADC_3		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define  OXYGEN_REC_A_ROUTE_MASK	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define  OXYGEN_REC_A_ROUTE_I2S_ADC_1	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define  OXYGEN_REC_A_ROUTE_AC97_0	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define  OXYGEN_REC_B_ROUTE_MASK	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define  OXYGEN_REC_B_ROUTE_I2S_ADC_2	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define  OXYGEN_REC_B_ROUTE_AC97_1	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define  OXYGEN_REC_C_ROUTE_MASK	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define  OXYGEN_REC_C_ROUTE_SPDIF	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define  OXYGEN_REC_C_ROUTE_I2S_ADC_3	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define OXYGEN_ADC_MONITOR		0xc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define  OXYGEN_ADC_MONITOR_A		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define  OXYGEN_ADC_MONITOR_A_HALF_VOL	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define  OXYGEN_ADC_MONITOR_B		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define  OXYGEN_ADC_MONITOR_B_HALF_VOL	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define  OXYGEN_ADC_MONITOR_C		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define  OXYGEN_ADC_MONITOR_C_HALF_VOL	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define OXYGEN_A_MONITOR_ROUTING	0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define  OXYGEN_A_MONITOR_ROUTE_0_MASK	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define  OXYGEN_A_MONITOR_ROUTE_0_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define  OXYGEN_A_MONITOR_ROUTE_1_MASK	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define  OXYGEN_A_MONITOR_ROUTE_1_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define  OXYGEN_A_MONITOR_ROUTE_2_MASK	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define  OXYGEN_A_MONITOR_ROUTE_2_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define  OXYGEN_A_MONITOR_ROUTE_3_MASK	0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define  OXYGEN_A_MONITOR_ROUTE_3_SHIFT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define OXYGEN_AC97_CONTROL		0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define  OXYGEN_AC97_COLD_RESET		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define  OXYGEN_AC97_SUSPENDED		0x0002	/* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define  OXYGEN_AC97_RESUME		0x0002	/* write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define  OXYGEN_AC97_CLOCK_DISABLE	0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define  OXYGEN_AC97_NO_CODEC_0		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define  OXYGEN_AC97_CODEC_0		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define  OXYGEN_AC97_CODEC_1		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define OXYGEN_AC97_INTERRUPT_MASK	0xd2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define  OXYGEN_AC97_INT_READ_DONE	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define  OXYGEN_AC97_INT_WRITE_DONE	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define  OXYGEN_AC97_INT_CODEC_0	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define  OXYGEN_AC97_INT_CODEC_1	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define OXYGEN_AC97_INTERRUPT_STATUS	0xd3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* OXYGEN_AC97_INT_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define OXYGEN_AC97_OUT_CONFIG		0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define  OXYGEN_AC97_CODEC1_SLOT3	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define  OXYGEN_AC97_CODEC1_SLOT3_VSR	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define  OXYGEN_AC97_CODEC1_SLOT4	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define  OXYGEN_AC97_CODEC1_SLOT4_VSR	0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define  OXYGEN_AC97_CODEC0_FRONTL	0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define  OXYGEN_AC97_CODEC0_FRONTR	0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define  OXYGEN_AC97_CODEC0_SIDEL	0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define  OXYGEN_AC97_CODEC0_SIDER	0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define  OXYGEN_AC97_CODEC0_CENTER	0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define  OXYGEN_AC97_CODEC0_BASE	0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define  OXYGEN_AC97_CODEC0_REARL	0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define  OXYGEN_AC97_CODEC0_REARR	0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define OXYGEN_AC97_IN_CONFIG		0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define  OXYGEN_AC97_CODEC1_LINEL	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define  OXYGEN_AC97_CODEC1_LINEL_VSR	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define  OXYGEN_AC97_CODEC1_LINEL_16	0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define  OXYGEN_AC97_CODEC1_LINEL_18	0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define  OXYGEN_AC97_CODEC1_LINEL_20	0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define  OXYGEN_AC97_CODEC1_LINER	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define  OXYGEN_AC97_CODEC1_LINER_VSR	0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define  OXYGEN_AC97_CODEC1_LINER_16	0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define  OXYGEN_AC97_CODEC1_LINER_18	0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define  OXYGEN_AC97_CODEC1_LINER_20	0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define  OXYGEN_AC97_CODEC0_LINEL	0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define  OXYGEN_AC97_CODEC0_LINER	0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define OXYGEN_AC97_REGS		0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define  OXYGEN_AC97_REG_DATA_MASK	0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define  OXYGEN_AC97_REG_ADDR_MASK	0x007f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define  OXYGEN_AC97_REG_ADDR_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define  OXYGEN_AC97_REG_DIR_MASK	0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define  OXYGEN_AC97_REG_DIR_WRITE	0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define  OXYGEN_AC97_REG_DIR_READ	0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define  OXYGEN_AC97_REG_CODEC_MASK	0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define  OXYGEN_AC97_REG_CODEC_SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define OXYGEN_TEST			0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define  OXYGEN_TEST_RAM_SUCCEEDED	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define  OXYGEN_TEST_PLAYBACK_RAM	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define  OXYGEN_TEST_RECORD_RAM		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define  OXYGEN_TEST_PLL		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define  OXYGEN_TEST_2WIRE_LOOPBACK	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define OXYGEN_DMA_FLUSH		0xe1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* OXYGEN_CHANNEL_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define OXYGEN_CODEC_VERSION		0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define  OXYGEN_CODEC_ID_MASK		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define OXYGEN_REVISION			0xe6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define  OXYGEN_PACKAGE_ID_MASK		0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define  OXYGEN_PACKAGE_ID_8786		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define  OXYGEN_PACKAGE_ID_8787		0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define  OXYGEN_PACKAGE_ID_8788		0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define  OXYGEN_REVISION_MASK		0xfff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define  OXYGEN_REVISION_2		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define OXYGEN_OFFSIN_48K		0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define OXYGEN_OFFSBASE_48K		0xe9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define  OXYGEN_OFFSBASE_MASK		0x0fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define OXYGEN_OFFSIN_44K		0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define OXYGEN_OFFSBASE_44K		0xed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #endif