^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * C-Media CMI8788 driver - main driver module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/asoundef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/mpu401.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "oxygen.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "cm9780.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MODULE_DESCRIPTION("C-Media CMI8788 helper library");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRIVER "oxygen"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static inline int oxygen_uart_input_ready(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void oxygen_read_uart(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (unlikely(!oxygen_uart_input_ready(chip))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* no data, but read it anyway to clear the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) oxygen_read8(chip, OXYGEN_MPU401);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 data = oxygen_read8(chip, OXYGEN_MPU401);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (data == MPU401_ACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) chip->uart_input_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) chip->uart_input[chip->uart_input_count++] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) } while (oxygen_uart_input_ready(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (chip->model.uart_input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) chip->model.uart_input(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct oxygen *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int status, clear, elapsed_streams, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) clear = status & (OXYGEN_CHANNEL_A |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) OXYGEN_CHANNEL_B |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) OXYGEN_CHANNEL_C |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) OXYGEN_CHANNEL_SPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) OXYGEN_CHANNEL_MULTICH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) OXYGEN_CHANNEL_AC97 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) OXYGEN_INT_SPDIF_IN_DETECT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) OXYGEN_INT_GPIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) OXYGEN_INT_AC97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (clear) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) chip->interrupt_mask & ~clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) chip->interrupt_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) elapsed_streams = status & chip->pcm_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) for (i = 0; i < PCM_COUNT; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if ((elapsed_streams & (1 << i)) && chip->streams[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) snd_pcm_period_elapsed(chip->streams[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) OXYGEN_SPDIF_RATE_INT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* write the interrupt bit(s) to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) schedule_work(&chip->spdif_input_bits_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (status & OXYGEN_INT_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) schedule_work(&chip->gpio_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (status & OXYGEN_INT_MIDI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (chip->midi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) snd_mpu401_uart_interrupt(0, chip->midi->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) oxygen_read_uart(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (status & OXYGEN_INT_AC97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) wake_up(&chip->ac97_waitqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void oxygen_spdif_input_bits_changed(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct oxygen *chip = container_of(work, struct oxygen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) spdif_input_bits_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * This function gets called when there is new activity on the SPDIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * input, or when we lose lock on the input signal, or when the rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) OXYGEN_SPDIF_LOCK_STATUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) == OXYGEN_SPDIF_SENSE_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * If we detect activity on the SPDIF input but cannot lock to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * a signal, the clock bit is likely to be wrong.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) OXYGEN_SPDIF_LOCK_STATUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) == OXYGEN_SPDIF_SENSE_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* nothing detected with either clock; give up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) == OXYGEN_SPDIF_IN_CLOCK_192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Reset clock to <= 96 kHz because this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * more likely to be received next time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) reg |= OXYGEN_SPDIF_IN_CLOCK_96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) chip->interrupt_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * We don't actually know that any channel status bits have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * changed, but let's send a notification just to be sure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void oxygen_gpio_changed(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (chip->model.gpio_changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) chip->model.gpio_changed(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static void oxygen_proc_read(struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct oxygen *chip = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) switch (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_PACKAGE_ID_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) case OXYGEN_PACKAGE_ID_8786: i = '6'; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) case OXYGEN_PACKAGE_ID_8787: i = '7'; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case OXYGEN_PACKAGE_ID_8788: i = '8'; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) default: i = '?'; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) snd_iprintf(buffer, "CMI878%c:\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) snd_iprintf(buffer, "%02x:", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) for (j = 0; j < 0x10; ++j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) snd_iprintf(buffer, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (mutex_lock_interruptible(&chip->mutex) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (chip->has_ac97_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) snd_iprintf(buffer, "\nAC97:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) for (i = 0; i < 0x80; i += 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) snd_iprintf(buffer, "%02x:", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) for (j = 0; j < 0x10; j += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) snd_iprintf(buffer, " %04x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) oxygen_read_ac97(chip, 0, i + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) snd_iprintf(buffer, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (chip->has_ac97_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) snd_iprintf(buffer, "\nAC97 2:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) for (i = 0; i < 0x80; i += 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) snd_iprintf(buffer, "%02x:", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) for (j = 0; j < 0x10; j += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) snd_iprintf(buffer, " %04x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) oxygen_read_ac97(chip, 1, i + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) snd_iprintf(buffer, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (chip->model.dump_registers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) chip->model.dump_registers(chip, buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void oxygen_proc_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) snd_card_ro_proc_new(chip->card, "oxygen", chip, oxygen_proc_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const struct pci_device_id *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u16 subdevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * Make sure the EEPROM pins are available, i.e., not used for SPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * (This function is called before we initialize or use SPI.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) oxygen_clear_bits8(chip, OXYGEN_FUNCTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) OXYGEN_FUNCTION_ENABLE_SPI_4_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * Read the subsystem device ID directly from the EEPROM, because the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * chip didn't if the first EEPROM word was overwritten.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) subdevice = oxygen_read_eeprom(chip, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* use default ID if EEPROM is missing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (subdevice == 0xffff && oxygen_read_eeprom(chip, 1) == 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) subdevice = 0x8788;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * We use only the subsystem device ID for searching because it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * unique even without the subsystem vendor ID, which may have been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * overwritten in the EEPROM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) for (; ids->vendor; ++ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (ids->subdevice == subdevice &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ids->driver_data != BROKEN_EEPROM_DRIVER_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return ids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static void oxygen_restore_eeprom(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u16 eeprom_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) eeprom_id = oxygen_read_eeprom(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (eeprom_id != OXYGEN_EEPROM_ID &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) (eeprom_id != 0xffff || id->subdevice != 0x8788)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * This function gets called only when a known card model has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * been detected, i.e., we know there is a valid subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * product ID at index 2 in the EEPROM. Therefore, we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * been able to deduce the correct subsystem vendor ID, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * this is enough information to restore the original EEPROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) oxygen_write_eeprom(chip, 1, id->subvendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) oxygen_write_eeprom(chip, 0, OXYGEN_EEPROM_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) oxygen_set_bits8(chip, OXYGEN_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) OXYGEN_MISC_WRITE_PCI_SUBID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) pci_write_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) id->subvendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pci_write_config_word(chip->pci, PCI_SUBSYSTEM_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) id->subdevice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) oxygen_clear_bits8(chip, OXYGEN_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) OXYGEN_MISC_WRITE_PCI_SUBID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_info(chip->card->dev, "EEPROM ID restored\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void configure_pcie_bridge(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) enum { PEX811X, PI7C9X110, XIO2001 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const struct pci_device_id bridge_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { PCI_VDEVICE(PLX, 0x8111), .driver_data = PEX811X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { PCI_VDEVICE(PLX, 0x8112), .driver_data = PEX811X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { PCI_DEVICE(0x12d8, 0xe110), .driver_data = PI7C9X110 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { PCI_VDEVICE(TI, 0x8240), .driver_data = XIO2001 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct pci_dev *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) const struct pci_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (!pci->bus || !pci->bus->self)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) bridge = pci->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) id = pci_match_id(bridge_ids, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (!id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) switch (id->driver_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) case PEX811X: /* PLX PEX8111/PEX8112 PCIe/PCI bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pci_read_config_dword(bridge, 0x48, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) tmp |= 1; /* enable blind prefetching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) tmp |= 1 << 11; /* enable beacon generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pci_write_config_dword(bridge, 0x48, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) pci_write_config_dword(bridge, 0x84, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pci_read_config_dword(bridge, 0x88, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) tmp &= ~(7 << 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) tmp |= 2 << 27; /* set prefetch size to 128 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pci_write_config_dword(bridge, 0x88, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case PI7C9X110: /* Pericom PI7C9X110 PCIe/PCI bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) pci_read_config_dword(bridge, 0x40, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) tmp |= 1; /* park the PCI arbiter to the sound chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) pci_write_config_dword(bridge, 0x40, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) case XIO2001: /* Texas Instruments XIO2001 PCIe/PCI bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) pci_read_config_dword(bridge, 0xe8, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) tmp &= ~0xf; /* request length limit: 64 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) tmp &= ~(0xf << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) tmp |= 1 << 8; /* request count limit: one buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) pci_write_config_dword(bridge, 0xe8, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static void oxygen_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) chip->dac_routing = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) for (i = 0; i < 8; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) chip->dac_volume[i] = chip->model.dac_volume_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) chip->dac_mute = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) chip->spdif_playback_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) chip->spdif_pcm_bits = chip->spdif_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (!(oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) oxygen_set_bits8(chip, OXYGEN_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) oxygen_write8_masked(chip, OXYGEN_FUNCTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) OXYGEN_FUNCTION_RESET_CODEC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) chip->model.function_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) OXYGEN_FUNCTION_RESET_CODEC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) OXYGEN_FUNCTION_2WIRE_SPI_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) OXYGEN_FUNCTION_ENABLE_SPI_4_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) OXYGEN_PLAY_CHANNELS_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) OXYGEN_DMA_A_BURST_8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) OXYGEN_DMA_MULTICH_BURST_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) oxygen_write8_masked(chip, OXYGEN_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) chip->model.misc_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) OXYGEN_MISC_WRITE_PCI_SUBID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) OXYGEN_MISC_REC_C_FROM_SPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) OXYGEN_MISC_REC_B_FROM_AC97 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) OXYGEN_MISC_REC_A_FROM_MULTICH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) OXYGEN_MISC_MIDI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) oxygen_write8(chip, OXYGEN_REC_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) OXYGEN_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) chip->model.dac_i2s_format |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) OXYGEN_I2S_MCLK(chip->model.dac_mclks) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) OXYGEN_I2S_BITS_16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) OXYGEN_I2S_MASTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) OXYGEN_I2S_BCLK_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) OXYGEN_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) chip->model.adc_i2s_format |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) OXYGEN_I2S_BITS_16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) OXYGEN_I2S_MASTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) OXYGEN_I2S_BCLK_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) OXYGEN_I2S_MASTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) OXYGEN_I2S_MUTE_MCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) CAPTURE_2_FROM_I2S_2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) OXYGEN_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) chip->model.adc_i2s_format |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) OXYGEN_I2S_BITS_16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) OXYGEN_I2S_MASTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) OXYGEN_I2S_BCLK_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) OXYGEN_I2S_MASTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) OXYGEN_I2S_MUTE_MCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (chip->model.device_config & CAPTURE_3_FROM_I2S_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) OXYGEN_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) chip->model.adc_i2s_format |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) OXYGEN_I2S_BITS_16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) OXYGEN_I2S_MASTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) OXYGEN_I2S_BCLK_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) OXYGEN_I2S_MASTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) OXYGEN_I2S_MUTE_MCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) OXYGEN_SPDIF_OUT_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) OXYGEN_SPDIF_LOOPBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) OXYGEN_SPDIF_SENSE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) OXYGEN_SPDIF_LOCK_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) OXYGEN_SPDIF_RATE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) OXYGEN_SPDIF_LOCK_PAR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) OXYGEN_SPDIF_IN_CLOCK_96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) OXYGEN_SPDIF_SENSE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) OXYGEN_SPDIF_LOCK_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) OXYGEN_SPDIF_RATE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) OXYGEN_SPDIF_SENSE_PAR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) OXYGEN_SPDIF_LOCK_PAR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) OXYGEN_SPDIF_IN_CLOCK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) OXYGEN_SPDIF_SENSE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) OXYGEN_SPDIF_LOCK_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) OXYGEN_SPDIF_RATE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) OXYGEN_2WIRE_LENGTH_8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) OXYGEN_2WIRE_INTERRUPT_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) OXYGEN_2WIRE_SPEED_STANDARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) OXYGEN_PLAY_MULTICH_I2S_DAC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) OXYGEN_PLAY_SPDIF_SPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) oxygen_write8(chip, OXYGEN_REC_ROUTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) OXYGEN_REC_C_ROUTE_SPDIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (chip->has_ac97_0 | chip->has_ac97_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) OXYGEN_AC97_INT_READ_DONE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) OXYGEN_AC97_INT_WRITE_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!(chip->has_ac97_0 | chip->has_ac97_1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) OXYGEN_AC97_CLOCK_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (!chip->has_ac97_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) OXYGEN_AC97_NO_CODEC_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) oxygen_write_ac97(chip, 0, AC97_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) CM9780_GPIO0IO | CM9780_GPIO1IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) CM9780_BSTSEL | CM9780_STRO_MIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) CM9780_MIX2FR | CM9780_PCBSW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) CM9780_RSOE | CM9780_CBOE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) CM9780_SSOE | CM9780_FROE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) CM9780_MIC2MIC | CM9780_LI2LI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) CM9780_GPO0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* power down unused ADCs and DACs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) AC97_PD_PR0 | AC97_PD_PR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (chip->has_ac97_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) OXYGEN_AC97_CODEC1_SLOT3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) OXYGEN_AC97_CODEC1_SLOT4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) oxygen_write_ac97(chip, 1, AC97_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static void oxygen_shutdown(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) chip->interrupt_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) chip->pcm_running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static void oxygen_card_free(struct snd_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct oxygen *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) oxygen_shutdown(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (chip->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) free_irq(chip->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) flush_work(&chip->spdif_input_bits_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) flush_work(&chip->gpio_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) chip->model.cleanup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) kfree(chip->model_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) mutex_destroy(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) pci_release_regions(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) pci_disable_device(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct module *owner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) const struct pci_device_id *ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int (*get_model)(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) const struct pci_device_id *id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct oxygen *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) const struct pci_device_id *pci_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) err = snd_card_new(&pci->dev, index, id, owner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) sizeof(*chip), &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) chip->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) chip->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) chip->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) spin_lock_init(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) mutex_init(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) INIT_WORK(&chip->spdif_input_bits_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) oxygen_spdif_input_bits_changed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) init_waitqueue_head(&chip->ac97_waitqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) err = pci_enable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) goto err_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) err = pci_request_regions(pci, DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dev_err(card->dev, "cannot reserve PCI resources\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) goto err_pci_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) dev_err(card->dev, "invalid PCI I/O range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) goto err_pci_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) chip->addr = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) pci_id = oxygen_search_pci_id(chip, ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (!pci_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) goto err_pci_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) oxygen_restore_eeprom(chip, pci_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) err = get_model(chip, pci_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) goto err_pci_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (chip->model.model_data_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) chip->model_data = kzalloc(chip->model.model_data_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (!chip->model_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) goto err_pci_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) card->private_free = oxygen_card_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) configure_pcie_bridge(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) oxygen_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) chip->model.init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) KBUILD_MODNAME, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dev_err(card->dev, "cannot grab interrupt %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) goto err_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) chip->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) card->sync_irq = chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) strcpy(card->driver, chip->model.chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) strcpy(card->shortname, chip->model.shortname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) sprintf(card->longname, "%s at %#lx, irq %i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) chip->model.longname, chip->addr, chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) strcpy(card->mixername, chip->model.chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) snd_component_add(card, chip->model.chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) err = oxygen_pcm_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) goto err_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) err = oxygen_mixer_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) goto err_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) unsigned int info_flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (chip->model.device_config & MIDI_OUTPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) info_flags |= MPU401_INFO_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (chip->model.device_config & MIDI_INPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) info_flags |= MPU401_INFO_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) chip->addr + OXYGEN_MPU401,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) info_flags, -1, &chip->midi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) goto err_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) oxygen_proc_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (chip->has_ac97_0 | chip->has_ac97_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) chip->interrupt_mask |= OXYGEN_INT_AC97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) err = snd_card_register(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) goto err_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) err_pci_regions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) pci_release_regions(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) err_pci_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) err_card:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) EXPORT_SYMBOL(oxygen_pci_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) void oxygen_pci_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) snd_card_free(pci_get_drvdata(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) EXPORT_SYMBOL(oxygen_pci_remove);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static int oxygen_pci_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct oxygen *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) unsigned int saved_interrupt_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (chip->model.suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) chip->model.suspend(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) saved_interrupt_mask = chip->interrupt_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) chip->interrupt_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) flush_work(&chip->spdif_input_bits_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) flush_work(&chip->gpio_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) chip->interrupt_mask = saved_interrupt_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const u32 ac97_registers_to_restore[2][0x40 / 32] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) { 0x18284fa2, 0x03060000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) { 0x00007fa6, 0x00200000 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static inline int is_bit_set(const u32 *bitmap, unsigned int bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return bitmap[bit / 32] & (1 << (bit & 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) oxygen_write_ac97(chip, codec, AC97_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) for (i = 1; i < 0x40; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (is_bit_set(ac97_registers_to_restore[codec], i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) oxygen_write_ac97(chip, codec, i * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) chip->saved_ac97_registers[codec][i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static int oxygen_pci_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct oxygen *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) for (i = 0; i < OXYGEN_IO_SIZE; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (is_bit_set(registers_to_restore, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) oxygen_write8(chip, i, chip->saved_registers._8[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (chip->has_ac97_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) oxygen_restore_ac97(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (chip->has_ac97_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) oxygen_restore_ac97(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (chip->model.resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) chip->model.resume(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) SIMPLE_DEV_PM_OPS(oxygen_pci_pm, oxygen_pci_suspend, oxygen_pci_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) EXPORT_SYMBOL(oxygen_pci_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) void oxygen_pci_shutdown(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct snd_card *card = pci_get_drvdata(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct oxygen *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) oxygen_shutdown(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) chip->model.cleanup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) EXPORT_SYMBOL(oxygen_pci_shutdown);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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