^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * C-Media CMI8788 driver for C-Media's reference design and similar models
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * CMI8788:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * SPI 0 -> 1st AK4396 (front)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * SPI 1 -> 2nd AK4396 (surround)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * SPI 2 -> 3rd AK4396 (center/LFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * SPI 3 -> WM8785
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * SPI 4 -> 4th AK4396 (back)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * GPIO 0 -> DFS0 of AK5385
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * GPIO 1 -> DFS1 of AK5385
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * X-Meridian models:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * GPIO 4 -> enable extension S/PDIF input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * GPIO 6 -> enable on-board S/PDIF input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Claro models:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * GPIO 6 -> S/PDIF from optical (0) or coaxial (1) input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * GPIO 8 -> enable headphone amplifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * CM9780:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * LINE_OUT -> input of ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * AUX_IN <- aux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * CD_IN <- CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * MIC_IN <- mic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * GPO 0 -> route line-in (0) or AC97 output (1) to ADC input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include "oxygen.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include "xonar_dg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include "ak4396.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include "wm8785.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MODULE_DESCRIPTION("C-Media CMI8788 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8786}"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ",{C-Media,CMI8787}"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ",{C-Media,CMI8788}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MODULE_PARM_DESC(index, "card index");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MODULE_PARM_DESC(id, "ID string");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MODULE_PARM_DESC(enable, "enable card");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MODEL_CMEDIA_REF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MODEL_MERIDIAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MODEL_MERIDIAN_2G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MODEL_CLARO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MODEL_CLARO_HALO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MODEL_FANTASIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MODEL_SERENADE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MODEL_2CH_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MODEL_HG2PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MODEL_XONAR_DG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MODEL_XONAR_DGX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const struct pci_device_id oxygen_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* C-Media's reference design */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { OXYGEN_PCI_SUBID(0x10b0, 0x0216), .driver_data = MODEL_CMEDIA_REF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { OXYGEN_PCI_SUBID(0x10b0, 0x0217), .driver_data = MODEL_CMEDIA_REF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { OXYGEN_PCI_SUBID(0x10b0, 0x0218), .driver_data = MODEL_CMEDIA_REF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { OXYGEN_PCI_SUBID(0x10b0, 0x0219), .driver_data = MODEL_CMEDIA_REF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { OXYGEN_PCI_SUBID(0x13f6, 0x0001), .driver_data = MODEL_CMEDIA_REF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { OXYGEN_PCI_SUBID(0x13f6, 0x0010), .driver_data = MODEL_CMEDIA_REF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { OXYGEN_PCI_SUBID(0x13f6, 0x8788), .driver_data = MODEL_CMEDIA_REF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { OXYGEN_PCI_SUBID(0x147a, 0xa017), .driver_data = MODEL_CMEDIA_REF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { OXYGEN_PCI_SUBID(0x1a58, 0x0910), .driver_data = MODEL_CMEDIA_REF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Asus Xonar DG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { OXYGEN_PCI_SUBID(0x1043, 0x8467), .driver_data = MODEL_XONAR_DG },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Asus Xonar DGX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { OXYGEN_PCI_SUBID(0x1043, 0x8521), .driver_data = MODEL_XONAR_DGX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* PCI 2.0 HD Audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { OXYGEN_PCI_SUBID(0x13f6, 0x8782), .driver_data = MODEL_2CH_OUTPUT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Kuroutoshikou CMI8787-HG2PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { OXYGEN_PCI_SUBID(0x13f6, 0xffff), .driver_data = MODEL_HG2PCI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* TempoTec HiFier Fantasia */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { OXYGEN_PCI_SUBID(0x14c3, 0x1710), .driver_data = MODEL_FANTASIA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* TempoTec HiFier Serenade */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { OXYGEN_PCI_SUBID(0x14c3, 0x1711), .driver_data = MODEL_SERENADE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* AuzenTech X-Meridian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { OXYGEN_PCI_SUBID(0x415a, 0x5431), .driver_data = MODEL_MERIDIAN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* AuzenTech X-Meridian 2G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { OXYGEN_PCI_SUBID(0x5431, 0x017a), .driver_data = MODEL_MERIDIAN_2G },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* HT-Omega Claro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { OXYGEN_PCI_SUBID(0x7284, 0x9761), .driver_data = MODEL_CLARO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* HT-Omega Claro halo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { OXYGEN_PCI_SUBID(0x7284, 0x9781), .driver_data = MODEL_CLARO_HALO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MODULE_DEVICE_TABLE(pci, oxygen_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GPIO_AK5385_DFS_MASK 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GPIO_AK5385_DFS_NORMAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GPIO_AK5385_DFS_DOUBLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GPIO_AK5385_DFS_QUAD 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GPIO_MERIDIAN_DIG_MASK 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GPIO_MERIDIAN_DIG_EXT 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GPIO_MERIDIAN_DIG_BOARD 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GPIO_CLARO_DIG_COAX 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GPIO_CLARO_HP 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct generic_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int dacs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 ak4396_regs[4][5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u16 wm8785_regs[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void ak4396_write(struct oxygen *chip, unsigned int codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* maps ALSA channel pair number to SPI output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const u8 codec_spi_map[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 0, 1, 2, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct generic_data *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) OXYGEN_SPI_DATA_LENGTH_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) OXYGEN_SPI_CLOCK_160 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) (codec_spi_map[codec] << OXYGEN_SPI_CODEC_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) OXYGEN_SPI_CEN_LATCH_CLOCK_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) AK4396_WRITE | (reg << 8) | value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) data->ak4396_regs[codec][reg] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void ak4396_write_cached(struct oxygen *chip, unsigned int codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct generic_data *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (value != data->ak4396_regs[codec][reg])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ak4396_write(chip, codec, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void wm8785_write(struct oxygen *chip, u8 reg, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct generic_data *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) OXYGEN_SPI_DATA_LENGTH_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) OXYGEN_SPI_CLOCK_160 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) (3 << OXYGEN_SPI_CODEC_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) OXYGEN_SPI_CEN_LATCH_CLOCK_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) (reg << 9) | value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (reg < ARRAY_SIZE(data->wm8785_regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) data->wm8785_regs[reg] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static void ak4396_registers_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct generic_data *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) for (i = 0; i < data->dacs; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ak4396_write(chip, i, AK4396_CONTROL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) AK4396_DIF_24_MSB | AK4396_RSTN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ak4396_write(chip, i, AK4396_CONTROL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) data->ak4396_regs[0][AK4396_CONTROL_2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ak4396_write(chip, i, AK4396_CONTROL_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) AK4396_PCM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ak4396_write(chip, i, AK4396_LCH_ATT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) chip->dac_volume[i * 2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ak4396_write(chip, i, AK4396_RCH_ATT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) chip->dac_volume[i * 2 + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void ak4396_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct generic_data *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) data->dacs = chip->model.dac_channels_pcm / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) data->ak4396_regs[0][AK4396_CONTROL_2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) AK4396_SMUTE | AK4396_DEM_OFF | AK4396_DFS_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ak4396_registers_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) snd_component_add(chip->card, "AK4396");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static void ak5385_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_AK5385_DFS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_AK5385_DFS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) snd_component_add(chip->card, "AK5385");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void wm8785_registers_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct generic_data *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) wm8785_write(chip, WM8785_R7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) wm8785_write(chip, WM8785_R0, data->wm8785_regs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) wm8785_write(chip, WM8785_R2, data->wm8785_regs[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void wm8785_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct generic_data *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) data->wm8785_regs[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) WM8785_MCR_SLAVE | WM8785_OSR_SINGLE | WM8785_FORMAT_LJUST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) data->wm8785_regs[2] = WM8785_HPFR | WM8785_HPFL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) wm8785_registers_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) snd_component_add(chip->card, "WM8785");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static void generic_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ak4396_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) wm8785_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void meridian_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) GPIO_MERIDIAN_DIG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) oxygen_write16_masked(chip, OXYGEN_GPIO_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) GPIO_MERIDIAN_DIG_BOARD, GPIO_MERIDIAN_DIG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ak4396_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ak5385_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static void claro_enable_hp(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) msleep(300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CLARO_HP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) oxygen_set_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_HP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void claro_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CLARO_DIG_COAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_DIG_COAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ak4396_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) wm8785_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) claro_enable_hp(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static void claro_halo_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CLARO_DIG_COAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_DIG_COAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ak4396_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ak5385_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) claro_enable_hp(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void fantasia_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ak4396_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) snd_component_add(chip->card, "CS5340");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static void stereo_output_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ak4396_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static void generic_cleanup(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static void claro_disable_hp(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_HP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void claro_cleanup(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) claro_disable_hp(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static void claro_suspend(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) claro_disable_hp(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static void generic_resume(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ak4396_registers_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) wm8785_registers_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static void meridian_resume(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ak4396_registers_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void claro_resume(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ak4396_registers_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) claro_enable_hp(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void stereo_resume(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ak4396_registers_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void set_ak4396_params(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct generic_data *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_DFS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (params_rate(params) <= 54000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) value |= AK4396_DFS_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) else if (params_rate(params) <= 108000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) value |= AK4396_DFS_DOUBLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) value |= AK4396_DFS_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) msleep(1); /* wait for the new MCLK to become stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (value != data->ak4396_regs[0][AK4396_CONTROL_2]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) for (i = 0; i < data->dacs; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ak4396_write(chip, i, AK4396_CONTROL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) AK4396_DIF_24_MSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ak4396_write(chip, i, AK4396_CONTROL_2, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ak4396_write(chip, i, AK4396_CONTROL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) AK4396_DIF_24_MSB | AK4396_RSTN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static void update_ak4396_volume(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct generic_data *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) for (i = 0; i < data->dacs; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ak4396_write_cached(chip, i, AK4396_LCH_ATT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) chip->dac_volume[i * 2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ak4396_write_cached(chip, i, AK4396_RCH_ATT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) chip->dac_volume[i * 2 + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static void update_ak4396_mute(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct generic_data *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_SMUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (chip->dac_mute)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) value |= AK4396_SMUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) for (i = 0; i < data->dacs; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ak4396_write_cached(chip, i, AK4396_CONTROL_2, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static void set_wm8785_params(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct generic_data *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) value = WM8785_MCR_SLAVE | WM8785_FORMAT_LJUST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (params_rate(params) <= 48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) value |= WM8785_OSR_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) else if (params_rate(params) <= 96000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) value |= WM8785_OSR_DOUBLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) value |= WM8785_OSR_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (value != data->wm8785_regs[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) wm8785_write(chip, WM8785_R7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) wm8785_write(chip, WM8785_R0, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) wm8785_write(chip, WM8785_R2, data->wm8785_regs[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static void set_ak5385_params(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (params_rate(params) <= 54000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) value = GPIO_AK5385_DFS_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) else if (params_rate(params) <= 108000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) value = GPIO_AK5385_DFS_DOUBLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) value = GPIO_AK5385_DFS_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) oxygen_write16_masked(chip, OXYGEN_GPIO_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) value, GPIO_AK5385_DFS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static void set_no_params(struct oxygen *chip, struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int rolloff_info(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct snd_ctl_elem_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static const char *const names[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) "Sharp Roll-off", "Slow Roll-off"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return snd_ctl_enum_info(info, 1, 2, names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int rolloff_get(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct generic_data *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) value->value.enumerated.item[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) (data->ak4396_regs[0][AK4396_CONTROL_2] & AK4396_SLOW) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static int rolloff_put(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct generic_data *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) reg = data->ak4396_regs[0][AK4396_CONTROL_2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (value->value.enumerated.item[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) reg |= AK4396_SLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) reg &= ~AK4396_SLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) changed = reg != data->ak4396_regs[0][AK4396_CONTROL_2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (changed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) for (i = 0; i < data->dacs; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ak4396_write(chip, i, AK4396_CONTROL_2, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static const struct snd_kcontrol_new rolloff_control = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .name = "DAC Filter Playback Enum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .info = rolloff_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .get = rolloff_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .put = rolloff_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static int hpf_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static const char *const names[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) "None", "High-pass Filter"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return snd_ctl_enum_info(info, 1, 2, names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int hpf_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct generic_data *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) value->value.enumerated.item[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) (data->wm8785_regs[WM8785_R2] & WM8785_HPFR) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int hpf_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct generic_data *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) reg = data->wm8785_regs[WM8785_R2] & ~(WM8785_HPFR | WM8785_HPFL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (value->value.enumerated.item[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) reg |= WM8785_HPFR | WM8785_HPFL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) changed = reg != data->wm8785_regs[WM8785_R2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) wm8785_write(chip, WM8785_R2, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const struct snd_kcontrol_new hpf_control = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .name = "ADC Filter Capture Enum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .info = hpf_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .get = hpf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .put = hpf_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static int meridian_dig_source_info(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct snd_ctl_elem_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static const char *const names[2] = { "On-board", "Extension" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return snd_ctl_enum_info(info, 1, 2, names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int claro_dig_source_info(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct snd_ctl_elem_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static const char *const names[2] = { "Optical", "Coaxial" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return snd_ctl_enum_info(info, 1, 2, names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int meridian_dig_source_get(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) value->value.enumerated.item[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) !!(oxygen_read16(chip, OXYGEN_GPIO_DATA) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) GPIO_MERIDIAN_DIG_EXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int claro_dig_source_get(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) value->value.enumerated.item[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) !!(oxygen_read16(chip, OXYGEN_GPIO_DATA) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) GPIO_CLARO_DIG_COAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static int meridian_dig_source_put(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u16 old_reg, new_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) old_reg = oxygen_read16(chip, OXYGEN_GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) new_reg = old_reg & ~GPIO_MERIDIAN_DIG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (value->value.enumerated.item[0] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) new_reg |= GPIO_MERIDIAN_DIG_BOARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) new_reg |= GPIO_MERIDIAN_DIG_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) changed = new_reg != old_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) oxygen_write16(chip, OXYGEN_GPIO_DATA, new_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int claro_dig_source_put(struct snd_kcontrol *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct oxygen *chip = ctl->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u16 old_reg, new_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) mutex_lock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) old_reg = oxygen_read16(chip, OXYGEN_GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) new_reg = old_reg & ~GPIO_CLARO_DIG_COAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (value->value.enumerated.item[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) new_reg |= GPIO_CLARO_DIG_COAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) changed = new_reg != old_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) oxygen_write16(chip, OXYGEN_GPIO_DATA, new_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) mutex_unlock(&chip->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static const struct snd_kcontrol_new meridian_dig_source_control = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .name = "IEC958 Source Capture Enum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .info = meridian_dig_source_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .get = meridian_dig_source_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .put = meridian_dig_source_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const struct snd_kcontrol_new claro_dig_source_control = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .name = "IEC958 Source Capture Enum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .info = claro_dig_source_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .get = claro_dig_source_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .put = claro_dig_source_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int generic_mixer_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return snd_ctl_add(chip->card, snd_ctl_new1(&rolloff_control, chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static int generic_wm8785_mixer_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) err = generic_mixer_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) err = snd_ctl_add(chip->card, snd_ctl_new1(&hpf_control, chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static int meridian_mixer_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) err = generic_mixer_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) err = snd_ctl_add(chip->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) snd_ctl_new1(&meridian_dig_source_control, chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int claro_mixer_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) err = generic_wm8785_mixer_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) err = snd_ctl_add(chip->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) snd_ctl_new1(&claro_dig_source_control, chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static int claro_halo_mixer_init(struct oxygen *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) err = generic_mixer_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) err = snd_ctl_add(chip->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) snd_ctl_new1(&claro_dig_source_control, chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static void dump_ak4396_registers(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct generic_data *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) unsigned int dac, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) for (dac = 0; dac < data->dacs; ++dac) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) snd_iprintf(buffer, "\nAK4396 %u:", dac + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) for (i = 0; i < 5; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) snd_iprintf(buffer, " %02x", data->ak4396_regs[dac][i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) snd_iprintf(buffer, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static void dump_wm8785_registers(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct generic_data *data = chip->model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) snd_iprintf(buffer, "\nWM8785:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) for (i = 0; i < 3; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) snd_iprintf(buffer, " %03x", data->wm8785_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) snd_iprintf(buffer, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static void dump_oxygen_registers(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dump_ak4396_registers(chip, buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) dump_wm8785_registers(chip, buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static const DECLARE_TLV_DB_LINEAR(ak4396_db_scale, TLV_DB_GAIN_MUTE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static const struct oxygen_model model_generic = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .shortname = "C-Media CMI8788",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .longname = "C-Media Oxygen HD Audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .chip = "CMI8788",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .init = generic_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .mixer_init = generic_wm8785_mixer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .cleanup = generic_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .resume = generic_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .set_dac_params = set_ak4396_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .set_adc_params = set_wm8785_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .update_dac_volume = update_ak4396_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .update_dac_mute = update_ak4396_mute,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .dump_registers = dump_oxygen_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .dac_tlv = ak4396_db_scale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .model_data_size = sizeof(struct generic_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .device_config = PLAYBACK_0_TO_I2S |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) PLAYBACK_1_TO_SPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PLAYBACK_2_TO_AC97_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) CAPTURE_0_FROM_I2S_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) CAPTURE_1_FROM_SPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) CAPTURE_2_FROM_AC97_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) AC97_CD_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .dac_channels_pcm = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .dac_channels_mixer = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .dac_volume_min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .dac_volume_max = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .function_flags = OXYGEN_FUNCTION_SPI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) OXYGEN_FUNCTION_ENABLE_SPI_4_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .dac_mclks = OXYGEN_MCLKS(256, 128, 128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .adc_mclks = OXYGEN_MCLKS(256, 256, 128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static int get_oxygen_model(struct oxygen *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static const char *const names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) [MODEL_MERIDIAN] = "AuzenTech X-Meridian",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) [MODEL_MERIDIAN_2G] = "AuzenTech X-Meridian 2G",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) [MODEL_CLARO] = "HT-Omega Claro",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) [MODEL_CLARO_HALO] = "HT-Omega Claro halo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) [MODEL_FANTASIA] = "TempoTec HiFier Fantasia",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) [MODEL_SERENADE] = "TempoTec HiFier Serenade",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) [MODEL_HG2PCI] = "CMI8787-HG2PCI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) [MODEL_XONAR_DG] = "Xonar DG",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) [MODEL_XONAR_DGX] = "Xonar DGX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) chip->model = model_generic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) switch (id->driver_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) case MODEL_MERIDIAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) case MODEL_MERIDIAN_2G:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) chip->model.init = meridian_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) chip->model.mixer_init = meridian_mixer_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) chip->model.resume = meridian_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) chip->model.set_adc_params = set_ak5385_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) chip->model.dump_registers = dump_ak4396_registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) chip->model.device_config = PLAYBACK_0_TO_I2S |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) PLAYBACK_1_TO_SPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) CAPTURE_0_FROM_I2S_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) CAPTURE_1_FROM_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (id->driver_data == MODEL_MERIDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) chip->model.device_config |= AC97_CD_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) case MODEL_CLARO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) chip->model.init = claro_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) chip->model.mixer_init = claro_mixer_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) chip->model.cleanup = claro_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) chip->model.suspend = claro_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) chip->model.resume = claro_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) case MODEL_CLARO_HALO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) chip->model.init = claro_halo_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) chip->model.mixer_init = claro_halo_mixer_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) chip->model.cleanup = claro_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) chip->model.suspend = claro_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) chip->model.resume = claro_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) chip->model.set_adc_params = set_ak5385_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) chip->model.dump_registers = dump_ak4396_registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) chip->model.device_config = PLAYBACK_0_TO_I2S |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) PLAYBACK_1_TO_SPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) CAPTURE_0_FROM_I2S_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) CAPTURE_1_FROM_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) case MODEL_FANTASIA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) case MODEL_SERENADE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) case MODEL_2CH_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) case MODEL_HG2PCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) chip->model.shortname = "C-Media CMI8787";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) chip->model.chip = "CMI8787";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (id->driver_data == MODEL_FANTASIA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) chip->model.init = fantasia_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) chip->model.init = stereo_output_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) chip->model.resume = stereo_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) chip->model.mixer_init = generic_mixer_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) chip->model.set_adc_params = set_no_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) chip->model.dump_registers = dump_ak4396_registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) chip->model.device_config = PLAYBACK_0_TO_I2S |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) PLAYBACK_1_TO_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (id->driver_data == MODEL_FANTASIA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) chip->model.device_config |= CAPTURE_0_FROM_I2S_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) chip->model.adc_mclks = OXYGEN_MCLKS(256, 128, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) chip->model.dac_channels_pcm = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) chip->model.dac_channels_mixer = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) case MODEL_XONAR_DG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) case MODEL_XONAR_DGX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) chip->model = model_xonar_dg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (id->driver_data == MODEL_MERIDIAN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) id->driver_data == MODEL_MERIDIAN_2G ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) id->driver_data == MODEL_CLARO_HALO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) chip->model.misc_flags = OXYGEN_MISC_MIDI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) chip->model.device_config |= MIDI_OUTPUT | MIDI_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (id->driver_data < ARRAY_SIZE(names) && names[id->driver_data])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) chip->model.shortname = names[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static int generic_oxygen_probe(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (dev >= SNDRV_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (!enable[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ++dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) err = oxygen_pci_probe(pci, index[dev], id[dev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) oxygen_ids, get_oxygen_model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (err >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ++dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static struct pci_driver oxygen_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .id_table = oxygen_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .probe = generic_oxygen_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .remove = oxygen_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .pm = &oxygen_pci_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) module_pci_driver(oxygen_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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