^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define CS4398_REV_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #define CS4398_PART_MASK 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define CS4398_PART_CS4398 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /* register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define CS4398_FM_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define CS4398_FM_SINGLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define CS4398_FM_DOUBLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CS4398_FM_QUAD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CS4398_FM_DSD 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CS4398_DEM_MASK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CS4398_DEM_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CS4398_DEM_44100 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CS4398_DEM_48000 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CS4398_DEM_32000 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CS4398_DIF_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CS4398_DIF_LJUST 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CS4398_DIF_I2S 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CS4398_DIF_RJUST_16 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CS4398_DIF_RJUST_24 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CS4398_DIF_RJUST_20 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CS4398_DIF_RJUST_18 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CS4398_DSD_SRC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CS4398_ATAPI_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CS4398_ATAPI_B_MUTE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CS4398_ATAPI_B_R 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CS4398_ATAPI_B_L 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CS4398_ATAPI_B_LR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CS4398_ATAPI_A_MUTE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CS4398_ATAPI_A_R 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CS4398_ATAPI_A_L 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CS4398_ATAPI_A_LR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CS4398_ATAPI_MIX_LR_VOL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CS4398_INVERT_B 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CS4398_INVERT_A 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CS4398_VOL_B_EQ_A 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* register 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CS4398_MUTEP_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CS4398_MUTEP_AUTO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CS4398_MUTEP_LOW 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CS4398_MUTEP_HIGH 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CS4398_MUTE_B 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CS4398_MUTE_A 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CS4398_MUTEC_A_EQ_B 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CS4398_DAMUTE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CS4398_PAMUTE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* register 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CS4398_VOL_A_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* register 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CS4398_VOL_B_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* register 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CS4398_DIR_DSD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CS4398_FILT_SEL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CS4398_RMP_DN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CS4398_RMP_UP 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CS4398_ZERO_CROSS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CS4398_SOFT_RAMP 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* register 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CS4398_MCLKDIV3 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CS4398_MCLKDIV2 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CS4398_FREEZE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CS4398_CPEN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CS4398_PDN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* register 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CS4398_DSD_PM_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CS4398_DSD_PM_MODE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CS4398_INVALID_DSD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CS4398_STATIC_DSD 0x08
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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