^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* register 01h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define CS4362A_PDN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #define CS4362A_DAC1_DIS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define CS4362A_DAC2_DIS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define CS4362A_DAC3_DIS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define CS4362A_MCLKDIV 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define CS4362A_FREEZE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define CS4362A_CPEN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* register 02h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CS4362A_DIF_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CS4362A_DIF_LJUST 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CS4362A_DIF_I2S 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CS4362A_DIF_RJUST_16 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CS4362A_DIF_RJUST_24 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CS4362A_DIF_RJUST_20 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CS4362A_DIF_RJUST_18 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* register 03h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CS4362A_MUTEC_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CS4362A_MUTEC_6 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CS4362A_MUTEC_1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CS4362A_MUTEC_3 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CS4362A_AMUTE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CS4362A_MUTEC_POL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CS4362A_RMP_UP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CS4362A_SNGLVOL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CS4362A_ZERO_CROSS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CS4362A_SOFT_RAMP 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* register 04h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CS4362A_RMP_DN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CS4362A_DEM_MASK 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CS4362A_DEM_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CS4362A_DEM_44100 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CS4362A_DEM_48000 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CS4362A_DEM_32000 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CS4362A_FILT_SEL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* register 05h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CS4362A_INV_A1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CS4362A_INV_B1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CS4362A_INV_A2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CS4362A_INV_B2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CS4362A_INV_A3 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CS4362A_INV_B3 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* register 06h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CS4362A_FM_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CS4362A_FM_SINGLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CS4362A_FM_DOUBLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CS4362A_FM_QUAD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CS4362A_FM_DSD 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CS4362A_ATAPI_MASK 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CS4362A_ATAPI_B_MUTE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CS4362A_ATAPI_B_R 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CS4362A_ATAPI_B_L 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CS4362A_ATAPI_B_LR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CS4362A_ATAPI_A_MUTE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CS4362A_ATAPI_A_R 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CS4362A_ATAPI_A_L 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CS4362A_ATAPI_A_LR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CS4362A_ATAPI_MIX_LR_VOL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CS4362A_A_EQ_B 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* register 07h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CS4362A_VOL_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CS4362A_MUTE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* register 08h: like 07h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* registers 09h..0Bh: like 06h..08h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* registers 0Ch..0Eh: like 06h..08h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* register 12h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CS4362A_REV_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CS4362A_PART_MASK 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CS4362A_PART_CS4362A 0x50
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags